* [Intel-gfx] [PATCH 01/15] drm/i915: Check pipe source size when using skl+ scalers
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
@ 2023-04-18 17:55 ` Ville Syrjala
2023-04-19 15:11 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 02/15] drm/i915: Relocate VBLANK_EVASION_TIME_US Ville Syrjala
` (18 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2023-04-18 17:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Ross Zwisler, stable
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The skl+ scalers only sample 12 bits of PIPESRC so we can't
do any plane scaling at all when the pipe source size is >4k.
Make sure the pipe source size is also below the scaler's src
size limits. Might not be 100% accurate, but should at least be
safe. We can refine the limits later if we discover that recent
hw is less restricted.
Cc: stable@vger.kernel.org
Tested-by: Ross Zwisler <zwisler@google.com>
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8357
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/skl_scaler.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index 473d53610b92..0e7e014fcc71 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -111,6 +111,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
+ int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
+ int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
int min_src_w, min_src_h, min_dst_w, min_dst_h;
int max_src_w, max_src_h, max_dst_w, max_dst_h;
@@ -207,6 +209,21 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
return -EINVAL;
}
+ /*
+ * The pipe scaler does not use all the bits of PIPESRC, at least
+ * on the earlier platforms. So even when we're scaling a plane
+ * the *pipe* source size must not be too large. For simplicity
+ * we assume the limits match the scaler source size limits. Might
+ * not be 100% accurate on all platforms, but good enough for now.
+ */
+ if (pipe_src_w > max_src_w || pipe_src_h > max_src_h) {
+ drm_dbg_kms(&dev_priv->drm,
+ "scaler_user index %u.%u: pipe src size %ux%u "
+ "is out of scaler range\n",
+ crtc->pipe, scaler_user, pipe_src_w, pipe_src_h);
+ return -EINVAL;
+ }
+
/* mark this plane as a scaler user in crtc_state */
scaler_state->scaler_users |= (1 << scaler_user);
drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
--
2.39.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH 01/15] drm/i915: Check pipe source size when using skl+ scalers
2023-04-18 17:55 ` [Intel-gfx] [PATCH 01/15] drm/i915: Check pipe source size when using skl+ scalers Ville Syrjala
@ 2023-04-19 15:11 ` Jani Nikula
0 siblings, 0 replies; 40+ messages in thread
From: Jani Nikula @ 2023-04-19 15:11 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: Ross Zwisler, stable
On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The skl+ scalers only sample 12 bits of PIPESRC so we can't
> do any plane scaling at all when the pipe source size is >4k.
>
> Make sure the pipe source size is also below the scaler's src
> size limits. Might not be 100% accurate, but should at least be
> safe. We can refine the limits later if we discover that recent
> hw is less restricted.
>
> Cc: stable@vger.kernel.org
> Tested-by: Ross Zwisler <zwisler@google.com>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8357
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_scaler.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index 473d53610b92..0e7e014fcc71 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -111,6 +111,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> const struct drm_display_mode *adjusted_mode =
> &crtc_state->hw.adjusted_mode;
> + int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
> + int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
> int min_src_w, min_src_h, min_dst_w, min_dst_h;
> int max_src_w, max_src_h, max_dst_w, max_dst_h;
>
> @@ -207,6 +209,21 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> return -EINVAL;
> }
>
> + /*
> + * The pipe scaler does not use all the bits of PIPESRC, at least
> + * on the earlier platforms. So even when we're scaling a plane
> + * the *pipe* source size must not be too large. For simplicity
> + * we assume the limits match the scaler source size limits. Might
> + * not be 100% accurate on all platforms, but good enough for now.
> + */
> + if (pipe_src_w > max_src_w || pipe_src_h > max_src_h) {
> + drm_dbg_kms(&dev_priv->drm,
> + "scaler_user index %u.%u: pipe src size %ux%u "
> + "is out of scaler range\n",
> + crtc->pipe, scaler_user, pipe_src_w, pipe_src_h);
> + return -EINVAL;
> + }
> +
> /* mark this plane as a scaler user in crtc_state */
> scaler_state->scaler_users |= (1 << scaler_user);
> drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH 02/15] drm/i915: Relocate VBLANK_EVASION_TIME_US
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
2023-04-18 17:55 ` [Intel-gfx] [PATCH 01/15] drm/i915: Check pipe source size when using skl+ scalers Ville Syrjala
@ 2023-04-18 17:55 ` Ville Syrjala
2023-04-19 15:13 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 03/15] drm/i915: Relocate intel_atomic_setup_scalers() Ville Syrjala
` (17 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2023-04-18 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move the VBLANK_EVASION_TIME_US definition to a slightly
better place.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crtc.h | 10 ++++++++++
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.h | 10 ----------
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h b/drivers/gpu/drm/i915/display/intel_crtc.h
index 73077137fb99..51a4c8df9e65 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.h
+++ b/drivers/gpu/drm/i915/display/intel_crtc.h
@@ -16,6 +16,16 @@ struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
+/*
+ * FIXME: We should instead only take spinlocks once for the entire update
+ * instead of once per mmio.
+ */
+#if IS_ENABLED(CONFIG_PROVE_LOCKING)
+#define VBLANK_EVASION_TIME_US 250
+#else
+#define VBLANK_EVASION_TIME_US 100
+#endif
+
int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
int usecs);
u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index abd16a2b1f7a..e72288662f02 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -12,6 +12,7 @@
#include "i915_debugfs.h"
#include "i915_irq.h"
#include "i915_reg.h"
+#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_crtc_state_dump.h"
#include "intel_display_debugfs.h"
@@ -30,7 +31,6 @@
#include "intel_panel.h"
#include "intel_psr.h"
#include "intel_psr_regs.h"
-#include "intel_sprite.h"
#include "intel_wm.h"
static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.h b/drivers/gpu/drm/i915/display/intel_sprite.h
index 4635c7ad23f9..91c6dca342b2 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.h
+++ b/drivers/gpu/drm/i915/display/intel_sprite.h
@@ -16,16 +16,6 @@ struct intel_crtc_state;
struct intel_plane_state;
enum pipe;
-/*
- * FIXME: We should instead only take spinlocks once for the entire update
- * instead of once per mmio.
- */
-#if IS_ENABLED(CONFIG_PROVE_LOCKING)
-#define VBLANK_EVASION_TIME_US 250
-#else
-#define VBLANK_EVASION_TIME_US 100
-#endif
-
struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
enum pipe pipe, int plane);
int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
--
2.39.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH 02/15] drm/i915: Relocate VBLANK_EVASION_TIME_US
2023-04-18 17:55 ` [Intel-gfx] [PATCH 02/15] drm/i915: Relocate VBLANK_EVASION_TIME_US Ville Syrjala
@ 2023-04-19 15:13 ` Jani Nikula
0 siblings, 0 replies; 40+ messages in thread
From: Jani Nikula @ 2023-04-19 15:13 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move the VBLANK_EVASION_TIME_US definition to a slightly
> better place.
I wish this could be hidden in intel_crtc.c but this is an improvement.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crtc.h | 10 ++++++++++
> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
> drivers/gpu/drm/i915/display/intel_sprite.h | 10 ----------
> 3 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h b/drivers/gpu/drm/i915/display/intel_crtc.h
> index 73077137fb99..51a4c8df9e65 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.h
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.h
> @@ -16,6 +16,16 @@ struct intel_atomic_state;
> struct intel_crtc;
> struct intel_crtc_state;
>
> +/*
> + * FIXME: We should instead only take spinlocks once for the entire update
> + * instead of once per mmio.
> + */
> +#if IS_ENABLED(CONFIG_PROVE_LOCKING)
> +#define VBLANK_EVASION_TIME_US 250
> +#else
> +#define VBLANK_EVASION_TIME_US 100
> +#endif
> +
> int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
> int usecs);
> u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index abd16a2b1f7a..e72288662f02 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -12,6 +12,7 @@
> #include "i915_debugfs.h"
> #include "i915_irq.h"
> #include "i915_reg.h"
> +#include "intel_crtc.h"
> #include "intel_de.h"
> #include "intel_crtc_state_dump.h"
> #include "intel_display_debugfs.h"
> @@ -30,7 +31,6 @@
> #include "intel_panel.h"
> #include "intel_psr.h"
> #include "intel_psr_regs.h"
> -#include "intel_sprite.h"
> #include "intel_wm.h"
>
> static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.h b/drivers/gpu/drm/i915/display/intel_sprite.h
> index 4635c7ad23f9..91c6dca342b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.h
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.h
> @@ -16,16 +16,6 @@ struct intel_crtc_state;
> struct intel_plane_state;
> enum pipe;
>
> -/*
> - * FIXME: We should instead only take spinlocks once for the entire update
> - * instead of once per mmio.
> - */
> -#if IS_ENABLED(CONFIG_PROVE_LOCKING)
> -#define VBLANK_EVASION_TIME_US 250
> -#else
> -#define VBLANK_EVASION_TIME_US 100
> -#endif
> -
> struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> enum pipe pipe, int plane);
> int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH 03/15] drm/i915: Relocate intel_atomic_setup_scalers()
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
2023-04-18 17:55 ` [Intel-gfx] [PATCH 01/15] drm/i915: Check pipe source size when using skl+ scalers Ville Syrjala
2023-04-18 17:55 ` [Intel-gfx] [PATCH 02/15] drm/i915: Relocate VBLANK_EVASION_TIME_US Ville Syrjala
@ 2023-04-18 17:55 ` Ville Syrjala
2023-04-19 15:16 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 04/15] drm/i915: Relocate skl_get_pfit_config() Ville Syrjala
` (16 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2023-04-18 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move intel_atomic_setup_scalers() next to the other scaler
code in skl_scaler.c.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 256 -------------------
drivers/gpu/drm/i915/display/intel_atomic.h | 4 -
drivers/gpu/drm/i915/display/skl_scaler.c | 257 ++++++++++++++++++++
drivers/gpu/drm/i915/display/skl_scaler.h | 10 +-
4 files changed, 265 insertions(+), 262 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 61011641f6ab..7cf51dd8c056 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -310,262 +310,6 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
kfree(crtc_state);
}
-static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
- int num_scalers_need, struct intel_crtc *intel_crtc,
- const char *name, int idx,
- struct intel_plane_state *plane_state,
- int *scaler_id)
-{
- struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
- int j;
- u32 mode;
-
- if (*scaler_id < 0) {
- /* find a free scaler */
- for (j = 0; j < intel_crtc->num_scalers; j++) {
- if (scaler_state->scalers[j].in_use)
- continue;
-
- *scaler_id = j;
- scaler_state->scalers[*scaler_id].in_use = 1;
- break;
- }
- }
-
- if (drm_WARN(&dev_priv->drm, *scaler_id < 0,
- "Cannot find scaler for %s:%d\n", name, idx))
- return -EINVAL;
-
- /* set scaler mode */
- if (plane_state && plane_state->hw.fb &&
- plane_state->hw.fb->format->is_yuv &&
- plane_state->hw.fb->format->num_planes > 1) {
- struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- if (DISPLAY_VER(dev_priv) == 9) {
- mode = SKL_PS_SCALER_MODE_NV12;
- } else if (icl_is_hdr_plane(dev_priv, plane->id)) {
- /*
- * On gen11+'s HDR planes we only use the scaler for
- * scaling. They have a dedicated chroma upsampler, so
- * we don't need the scaler to upsample the UV plane.
- */
- mode = PS_SCALER_MODE_NORMAL;
- } else {
- struct intel_plane *linked =
- plane_state->planar_linked_plane;
-
- mode = PS_SCALER_MODE_PLANAR;
-
- if (linked)
- mode |= PS_PLANE_Y_SEL(linked->id);
- }
- } else if (DISPLAY_VER(dev_priv) >= 10) {
- mode = PS_SCALER_MODE_NORMAL;
- } else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
- /*
- * when only 1 scaler is in use on a pipe with 2 scalers
- * scaler 0 operates in high quality (HQ) mode.
- * In this case use scaler 0 to take advantage of HQ mode
- */
- scaler_state->scalers[*scaler_id].in_use = 0;
- *scaler_id = 0;
- scaler_state->scalers[0].in_use = 1;
- mode = SKL_PS_SCALER_MODE_HQ;
- } else {
- mode = SKL_PS_SCALER_MODE_DYN;
- }
-
- /*
- * FIXME: we should also check the scaler factors for pfit, so
- * this shouldn't be tied directly to planes.
- */
- if (plane_state && plane_state->hw.fb) {
- const struct drm_framebuffer *fb = plane_state->hw.fb;
- const struct drm_rect *src = &plane_state->uapi.src;
- const struct drm_rect *dst = &plane_state->uapi.dst;
- int hscale, vscale, max_vscale, max_hscale;
-
- /*
- * FIXME: When two scalers are needed, but only one of
- * them needs to downscale, we should make sure that
- * the one that needs downscaling support is assigned
- * as the first scaler, so we don't reject downscaling
- * unnecessarily.
- */
-
- if (DISPLAY_VER(dev_priv) >= 14) {
- /*
- * On versions 14 and up, only the first
- * scaler supports a vertical scaling factor
- * of more than 1.0, while a horizontal
- * scaling factor of 3.0 is supported.
- */
- max_hscale = 0x30000 - 1;
- if (*scaler_id == 0)
- max_vscale = 0x30000 - 1;
- else
- max_vscale = 0x10000;
-
- } else if (DISPLAY_VER(dev_priv) >= 10 ||
- !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
- max_hscale = 0x30000 - 1;
- max_vscale = 0x30000 - 1;
- } else {
- max_hscale = 0x20000 - 1;
- max_vscale = 0x20000 - 1;
- }
-
- /*
- * FIXME: We should change the if-else block above to
- * support HQ vs dynamic scaler properly.
- */
-
- /* Check if required scaling is within limits */
- hscale = drm_rect_calc_hscale(src, dst, 1, max_hscale);
- vscale = drm_rect_calc_vscale(src, dst, 1, max_vscale);
-
- if (hscale < 0 || vscale < 0) {
- drm_dbg_kms(&dev_priv->drm,
- "Scaler %d doesn't support required plane scaling\n",
- *scaler_id);
- drm_rect_debug_print("src: ", src, true);
- drm_rect_debug_print("dst: ", dst, false);
-
- return -EINVAL;
- }
- }
-
- drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n",
- intel_crtc->pipe, *scaler_id, name, idx);
- scaler_state->scalers[*scaler_id].mode = mode;
-
- return 0;
-}
-
-/**
- * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
- * @dev_priv: i915 device
- * @intel_crtc: intel crtc
- * @crtc_state: incoming crtc_state to validate and setup scalers
- *
- * This function sets up scalers based on staged scaling requests for
- * a @crtc and its planes. It is called from crtc level check path. If request
- * is a supportable request, it attaches scalers to requested planes and crtc.
- *
- * This function takes into account the current scaler(s) in use by any planes
- * not being part of this atomic state
- *
- * Returns:
- * 0 - scalers were setup succesfully
- * error code - otherwise
- */
-int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
- struct intel_crtc *intel_crtc,
- struct intel_crtc_state *crtc_state)
-{
- struct drm_plane *plane = NULL;
- struct intel_plane *intel_plane;
- struct intel_plane_state *plane_state = NULL;
- struct intel_crtc_scaler_state *scaler_state =
- &crtc_state->scaler_state;
- struct drm_atomic_state *drm_state = crtc_state->uapi.state;
- struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
- int num_scalers_need;
- int i;
-
- num_scalers_need = hweight32(scaler_state->scaler_users);
-
- /*
- * High level flow:
- * - staged scaler requests are already in scaler_state->scaler_users
- * - check whether staged scaling requests can be supported
- * - add planes using scalers that aren't in current transaction
- * - assign scalers to requested users
- * - as part of plane commit, scalers will be committed
- * (i.e., either attached or detached) to respective planes in hw
- * - as part of crtc_commit, scaler will be either attached or detached
- * to crtc in hw
- */
-
- /* fail if required scalers > available scalers */
- if (num_scalers_need > intel_crtc->num_scalers){
- drm_dbg_kms(&dev_priv->drm,
- "Too many scaling requests %d > %d\n",
- num_scalers_need, intel_crtc->num_scalers);
- return -EINVAL;
- }
-
- /* walkthrough scaler_users bits and start assigning scalers */
- for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
- int *scaler_id;
- const char *name;
- int idx, ret;
-
- /* skip if scaler not required */
- if (!(scaler_state->scaler_users & (1 << i)))
- continue;
-
- if (i == SKL_CRTC_INDEX) {
- name = "CRTC";
- idx = intel_crtc->base.base.id;
-
- /* panel fitter case: assign as a crtc scaler */
- scaler_id = &scaler_state->scaler_id;
- } else {
- name = "PLANE";
-
- /* plane scaler case: assign as a plane scaler */
- /* find the plane that set the bit as scaler_user */
- plane = drm_state->planes[i].ptr;
-
- /*
- * to enable/disable hq mode, add planes that are using scaler
- * into this transaction
- */
- if (!plane) {
- struct drm_plane_state *state;
-
- /*
- * GLK+ scalers don't have a HQ mode so it
- * isn't necessary to change between HQ and dyn mode
- * on those platforms.
- */
- if (DISPLAY_VER(dev_priv) >= 10)
- continue;
-
- plane = drm_plane_from_index(&dev_priv->drm, i);
- state = drm_atomic_get_plane_state(drm_state, plane);
- if (IS_ERR(state)) {
- drm_dbg_kms(&dev_priv->drm,
- "Failed to add [PLANE:%d] to drm_state\n",
- plane->base.id);
- return PTR_ERR(state);
- }
- }
-
- intel_plane = to_intel_plane(plane);
- idx = plane->base.id;
-
- /* plane on different crtc cannot be a scaler user of this crtc */
- if (drm_WARN_ON(&dev_priv->drm,
- intel_plane->pipe != intel_crtc->pipe))
- continue;
-
- plane_state = intel_atomic_get_new_plane_state(intel_state,
- intel_plane);
- scaler_id = &plane_state->scaler_id;
- }
-
- ret = intel_atomic_setup_scaler(scaler_state, num_scalers_need,
- intel_crtc, name, idx,
- plane_state, scaler_id);
- if (ret < 0)
- return ret;
- }
-
- return 0;
-}
-
struct drm_atomic_state *
intel_atomic_state_alloc(struct drm_device *dev)
{
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
index 1dc439983dd9..e506f6a87344 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -52,8 +52,4 @@ struct intel_crtc_state *
intel_atomic_get_crtc_state(struct drm_atomic_state *state,
struct intel_crtc *crtc);
-int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
- struct intel_crtc *intel_crtc,
- struct intel_crtc_state *crtc_state);
-
#endif /* __INTEL_ATOMIC_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index 0e7e014fcc71..62443834f64e 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -348,6 +348,263 @@ int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
return 0;
}
+static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
+ int num_scalers_need, struct intel_crtc *intel_crtc,
+ const char *name, int idx,
+ struct intel_plane_state *plane_state,
+ int *scaler_id)
+{
+ struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
+ int j;
+ u32 mode;
+
+ if (*scaler_id < 0) {
+ /* find a free scaler */
+ for (j = 0; j < intel_crtc->num_scalers; j++) {
+ if (scaler_state->scalers[j].in_use)
+ continue;
+
+ *scaler_id = j;
+ scaler_state->scalers[*scaler_id].in_use = 1;
+ break;
+ }
+ }
+
+ if (drm_WARN(&dev_priv->drm, *scaler_id < 0,
+ "Cannot find scaler for %s:%d\n", name, idx))
+ return -EINVAL;
+
+ /* set scaler mode */
+ if (plane_state && plane_state->hw.fb &&
+ plane_state->hw.fb->format->is_yuv &&
+ plane_state->hw.fb->format->num_planes > 1) {
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+
+ if (DISPLAY_VER(dev_priv) == 9) {
+ mode = SKL_PS_SCALER_MODE_NV12;
+ } else if (icl_is_hdr_plane(dev_priv, plane->id)) {
+ /*
+ * On gen11+'s HDR planes we only use the scaler for
+ * scaling. They have a dedicated chroma upsampler, so
+ * we don't need the scaler to upsample the UV plane.
+ */
+ mode = PS_SCALER_MODE_NORMAL;
+ } else {
+ struct intel_plane *linked =
+ plane_state->planar_linked_plane;
+
+ mode = PS_SCALER_MODE_PLANAR;
+
+ if (linked)
+ mode |= PS_PLANE_Y_SEL(linked->id);
+ }
+ } else if (DISPLAY_VER(dev_priv) >= 10) {
+ mode = PS_SCALER_MODE_NORMAL;
+ } else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
+ /*
+ * when only 1 scaler is in use on a pipe with 2 scalers
+ * scaler 0 operates in high quality (HQ) mode.
+ * In this case use scaler 0 to take advantage of HQ mode
+ */
+ scaler_state->scalers[*scaler_id].in_use = 0;
+ *scaler_id = 0;
+ scaler_state->scalers[0].in_use = 1;
+ mode = SKL_PS_SCALER_MODE_HQ;
+ } else {
+ mode = SKL_PS_SCALER_MODE_DYN;
+ }
+
+ /*
+ * FIXME: we should also check the scaler factors for pfit, so
+ * this shouldn't be tied directly to planes.
+ */
+ if (plane_state && plane_state->hw.fb) {
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_rect *src = &plane_state->uapi.src;
+ const struct drm_rect *dst = &plane_state->uapi.dst;
+ int hscale, vscale, max_vscale, max_hscale;
+
+ /*
+ * FIXME: When two scalers are needed, but only one of
+ * them needs to downscale, we should make sure that
+ * the one that needs downscaling support is assigned
+ * as the first scaler, so we don't reject downscaling
+ * unnecessarily.
+ */
+
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ /*
+ * On versions 14 and up, only the first
+ * scaler supports a vertical scaling factor
+ * of more than 1.0, while a horizontal
+ * scaling factor of 3.0 is supported.
+ */
+ max_hscale = 0x30000 - 1;
+ if (*scaler_id == 0)
+ max_vscale = 0x30000 - 1;
+ else
+ max_vscale = 0x10000;
+
+ } else if (DISPLAY_VER(dev_priv) >= 10 ||
+ !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
+ max_hscale = 0x30000 - 1;
+ max_vscale = 0x30000 - 1;
+ } else {
+ max_hscale = 0x20000 - 1;
+ max_vscale = 0x20000 - 1;
+ }
+
+ /*
+ * FIXME: We should change the if-else block above to
+ * support HQ vs dynamic scaler properly.
+ */
+
+ /* Check if required scaling is within limits */
+ hscale = drm_rect_calc_hscale(src, dst, 1, max_hscale);
+ vscale = drm_rect_calc_vscale(src, dst, 1, max_vscale);
+
+ if (hscale < 0 || vscale < 0) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Scaler %d doesn't support required plane scaling\n",
+ *scaler_id);
+ drm_rect_debug_print("src: ", src, true);
+ drm_rect_debug_print("dst: ", dst, false);
+
+ return -EINVAL;
+ }
+ }
+
+ drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n",
+ intel_crtc->pipe, *scaler_id, name, idx);
+ scaler_state->scalers[*scaler_id].mode = mode;
+
+ return 0;
+}
+
+/**
+ * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
+ * @dev_priv: i915 device
+ * @intel_crtc: intel crtc
+ * @crtc_state: incoming crtc_state to validate and setup scalers
+ *
+ * This function sets up scalers based on staged scaling requests for
+ * a @crtc and its planes. It is called from crtc level check path. If request
+ * is a supportable request, it attaches scalers to requested planes and crtc.
+ *
+ * This function takes into account the current scaler(s) in use by any planes
+ * not being part of this atomic state
+ *
+ * Returns:
+ * 0 - scalers were setup successfully
+ * error code - otherwise
+ */
+int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
+ struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_plane *plane = NULL;
+ struct intel_plane *intel_plane;
+ struct intel_plane_state *plane_state = NULL;
+ struct intel_crtc_scaler_state *scaler_state =
+ &crtc_state->scaler_state;
+ struct drm_atomic_state *drm_state = crtc_state->uapi.state;
+ struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
+ int num_scalers_need;
+ int i;
+
+ num_scalers_need = hweight32(scaler_state->scaler_users);
+
+ /*
+ * High level flow:
+ * - staged scaler requests are already in scaler_state->scaler_users
+ * - check whether staged scaling requests can be supported
+ * - add planes using scalers that aren't in current transaction
+ * - assign scalers to requested users
+ * - as part of plane commit, scalers will be committed
+ * (i.e., either attached or detached) to respective planes in hw
+ * - as part of crtc_commit, scaler will be either attached or detached
+ * to crtc in hw
+ */
+
+ /* fail if required scalers > available scalers */
+ if (num_scalers_need > intel_crtc->num_scalers) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Too many scaling requests %d > %d\n",
+ num_scalers_need, intel_crtc->num_scalers);
+ return -EINVAL;
+ }
+
+ /* walkthrough scaler_users bits and start assigning scalers */
+ for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
+ int *scaler_id;
+ const char *name;
+ int idx, ret;
+
+ /* skip if scaler not required */
+ if (!(scaler_state->scaler_users & (1 << i)))
+ continue;
+
+ if (i == SKL_CRTC_INDEX) {
+ name = "CRTC";
+ idx = intel_crtc->base.base.id;
+
+ /* panel fitter case: assign as a crtc scaler */
+ scaler_id = &scaler_state->scaler_id;
+ } else {
+ name = "PLANE";
+
+ /* plane scaler case: assign as a plane scaler */
+ /* find the plane that set the bit as scaler_user */
+ plane = drm_state->planes[i].ptr;
+
+ /*
+ * to enable/disable hq mode, add planes that are using scaler
+ * into this transaction
+ */
+ if (!plane) {
+ struct drm_plane_state *state;
+
+ /*
+ * GLK+ scalers don't have a HQ mode so it
+ * isn't necessary to change between HQ and dyn mode
+ * on those platforms.
+ */
+ if (DISPLAY_VER(dev_priv) >= 10)
+ continue;
+
+ plane = drm_plane_from_index(&dev_priv->drm, i);
+ state = drm_atomic_get_plane_state(drm_state, plane);
+ if (IS_ERR(state)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Failed to add [PLANE:%d] to drm_state\n",
+ plane->base.id);
+ return PTR_ERR(state);
+ }
+ }
+
+ intel_plane = to_intel_plane(plane);
+ idx = plane->base.id;
+
+ /* plane on different crtc cannot be a scaler user of this crtc */
+ if (drm_WARN_ON(&dev_priv->drm,
+ intel_plane->pipe != intel_crtc->pipe))
+ continue;
+
+ plane_state = intel_atomic_get_new_plane_state(intel_state,
+ intel_plane);
+ scaler_id = &plane_state->scaler_id;
+ }
+
+ ret = intel_atomic_setup_scaler(scaler_state, num_scalers_need,
+ intel_crtc, name, idx,
+ plane_state, scaler_id);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
static int glk_coef_tap(int i)
{
return i % 7;
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h
index 0097d5d08e10..f040f6ac061f 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.h
+++ b/drivers/gpu/drm/i915/display/skl_scaler.h
@@ -8,17 +8,22 @@
#include <linux/types.h>
enum drm_scaling_filter;
+enum pipe;
struct drm_i915_private;
+struct intel_crtc;
struct intel_crtc_state;
-struct intel_plane_state;
struct intel_plane;
-enum pipe;
+struct intel_plane_state;
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state);
+int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
+ struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state);
+
void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
void skl_program_plane_scaler(struct intel_plane *plane,
@@ -26,4 +31,5 @@ void skl_program_plane_scaler(struct intel_plane *plane,
const struct intel_plane_state *plane_state);
void skl_detach_scalers(const struct intel_crtc_state *crtc_state);
void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state);
+
#endif
--
2.39.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH 03/15] drm/i915: Relocate intel_atomic_setup_scalers()
2023-04-18 17:55 ` [Intel-gfx] [PATCH 03/15] drm/i915: Relocate intel_atomic_setup_scalers() Ville Syrjala
@ 2023-04-19 15:16 ` Jani Nikula
0 siblings, 0 replies; 40+ messages in thread
From: Jani Nikula @ 2023-04-19 15:16 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move intel_atomic_setup_scalers() next to the other scaler
> code in skl_scaler.c.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 256 -------------------
> drivers/gpu/drm/i915/display/intel_atomic.h | 4 -
> drivers/gpu/drm/i915/display/skl_scaler.c | 257 ++++++++++++++++++++
> drivers/gpu/drm/i915/display/skl_scaler.h | 10 +-
> 4 files changed, 265 insertions(+), 262 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 61011641f6ab..7cf51dd8c056 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -310,262 +310,6 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
> kfree(crtc_state);
> }
>
> -static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
> - int num_scalers_need, struct intel_crtc *intel_crtc,
> - const char *name, int idx,
> - struct intel_plane_state *plane_state,
> - int *scaler_id)
> -{
> - struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> - int j;
> - u32 mode;
> -
> - if (*scaler_id < 0) {
> - /* find a free scaler */
> - for (j = 0; j < intel_crtc->num_scalers; j++) {
> - if (scaler_state->scalers[j].in_use)
> - continue;
> -
> - *scaler_id = j;
> - scaler_state->scalers[*scaler_id].in_use = 1;
> - break;
> - }
> - }
> -
> - if (drm_WARN(&dev_priv->drm, *scaler_id < 0,
> - "Cannot find scaler for %s:%d\n", name, idx))
> - return -EINVAL;
> -
> - /* set scaler mode */
> - if (plane_state && plane_state->hw.fb &&
> - plane_state->hw.fb->format->is_yuv &&
> - plane_state->hw.fb->format->num_planes > 1) {
> - struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> - if (DISPLAY_VER(dev_priv) == 9) {
> - mode = SKL_PS_SCALER_MODE_NV12;
> - } else if (icl_is_hdr_plane(dev_priv, plane->id)) {
> - /*
> - * On gen11+'s HDR planes we only use the scaler for
> - * scaling. They have a dedicated chroma upsampler, so
> - * we don't need the scaler to upsample the UV plane.
> - */
> - mode = PS_SCALER_MODE_NORMAL;
> - } else {
> - struct intel_plane *linked =
> - plane_state->planar_linked_plane;
> -
> - mode = PS_SCALER_MODE_PLANAR;
> -
> - if (linked)
> - mode |= PS_PLANE_Y_SEL(linked->id);
> - }
> - } else if (DISPLAY_VER(dev_priv) >= 10) {
> - mode = PS_SCALER_MODE_NORMAL;
> - } else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
> - /*
> - * when only 1 scaler is in use on a pipe with 2 scalers
> - * scaler 0 operates in high quality (HQ) mode.
> - * In this case use scaler 0 to take advantage of HQ mode
> - */
> - scaler_state->scalers[*scaler_id].in_use = 0;
> - *scaler_id = 0;
> - scaler_state->scalers[0].in_use = 1;
> - mode = SKL_PS_SCALER_MODE_HQ;
> - } else {
> - mode = SKL_PS_SCALER_MODE_DYN;
> - }
> -
> - /*
> - * FIXME: we should also check the scaler factors for pfit, so
> - * this shouldn't be tied directly to planes.
> - */
> - if (plane_state && plane_state->hw.fb) {
> - const struct drm_framebuffer *fb = plane_state->hw.fb;
> - const struct drm_rect *src = &plane_state->uapi.src;
> - const struct drm_rect *dst = &plane_state->uapi.dst;
> - int hscale, vscale, max_vscale, max_hscale;
> -
> - /*
> - * FIXME: When two scalers are needed, but only one of
> - * them needs to downscale, we should make sure that
> - * the one that needs downscaling support is assigned
> - * as the first scaler, so we don't reject downscaling
> - * unnecessarily.
> - */
> -
> - if (DISPLAY_VER(dev_priv) >= 14) {
> - /*
> - * On versions 14 and up, only the first
> - * scaler supports a vertical scaling factor
> - * of more than 1.0, while a horizontal
> - * scaling factor of 3.0 is supported.
> - */
> - max_hscale = 0x30000 - 1;
> - if (*scaler_id == 0)
> - max_vscale = 0x30000 - 1;
> - else
> - max_vscale = 0x10000;
> -
> - } else if (DISPLAY_VER(dev_priv) >= 10 ||
> - !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
> - max_hscale = 0x30000 - 1;
> - max_vscale = 0x30000 - 1;
> - } else {
> - max_hscale = 0x20000 - 1;
> - max_vscale = 0x20000 - 1;
> - }
> -
> - /*
> - * FIXME: We should change the if-else block above to
> - * support HQ vs dynamic scaler properly.
> - */
> -
> - /* Check if required scaling is within limits */
> - hscale = drm_rect_calc_hscale(src, dst, 1, max_hscale);
> - vscale = drm_rect_calc_vscale(src, dst, 1, max_vscale);
> -
> - if (hscale < 0 || vscale < 0) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Scaler %d doesn't support required plane scaling\n",
> - *scaler_id);
> - drm_rect_debug_print("src: ", src, true);
> - drm_rect_debug_print("dst: ", dst, false);
> -
> - return -EINVAL;
> - }
> - }
> -
> - drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n",
> - intel_crtc->pipe, *scaler_id, name, idx);
> - scaler_state->scalers[*scaler_id].mode = mode;
> -
> - return 0;
> -}
> -
> -/**
> - * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
> - * @dev_priv: i915 device
> - * @intel_crtc: intel crtc
> - * @crtc_state: incoming crtc_state to validate and setup scalers
> - *
> - * This function sets up scalers based on staged scaling requests for
> - * a @crtc and its planes. It is called from crtc level check path. If request
> - * is a supportable request, it attaches scalers to requested planes and crtc.
> - *
> - * This function takes into account the current scaler(s) in use by any planes
> - * not being part of this atomic state
> - *
> - * Returns:
> - * 0 - scalers were setup succesfully
> - * error code - otherwise
> - */
> -int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> - struct intel_crtc *intel_crtc,
> - struct intel_crtc_state *crtc_state)
> -{
> - struct drm_plane *plane = NULL;
> - struct intel_plane *intel_plane;
> - struct intel_plane_state *plane_state = NULL;
> - struct intel_crtc_scaler_state *scaler_state =
> - &crtc_state->scaler_state;
> - struct drm_atomic_state *drm_state = crtc_state->uapi.state;
> - struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
> - int num_scalers_need;
> - int i;
> -
> - num_scalers_need = hweight32(scaler_state->scaler_users);
> -
> - /*
> - * High level flow:
> - * - staged scaler requests are already in scaler_state->scaler_users
> - * - check whether staged scaling requests can be supported
> - * - add planes using scalers that aren't in current transaction
> - * - assign scalers to requested users
> - * - as part of plane commit, scalers will be committed
> - * (i.e., either attached or detached) to respective planes in hw
> - * - as part of crtc_commit, scaler will be either attached or detached
> - * to crtc in hw
> - */
> -
> - /* fail if required scalers > available scalers */
> - if (num_scalers_need > intel_crtc->num_scalers){
> - drm_dbg_kms(&dev_priv->drm,
> - "Too many scaling requests %d > %d\n",
> - num_scalers_need, intel_crtc->num_scalers);
> - return -EINVAL;
> - }
> -
> - /* walkthrough scaler_users bits and start assigning scalers */
> - for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
> - int *scaler_id;
> - const char *name;
> - int idx, ret;
> -
> - /* skip if scaler not required */
> - if (!(scaler_state->scaler_users & (1 << i)))
> - continue;
> -
> - if (i == SKL_CRTC_INDEX) {
> - name = "CRTC";
> - idx = intel_crtc->base.base.id;
> -
> - /* panel fitter case: assign as a crtc scaler */
> - scaler_id = &scaler_state->scaler_id;
> - } else {
> - name = "PLANE";
> -
> - /* plane scaler case: assign as a plane scaler */
> - /* find the plane that set the bit as scaler_user */
> - plane = drm_state->planes[i].ptr;
> -
> - /*
> - * to enable/disable hq mode, add planes that are using scaler
> - * into this transaction
> - */
> - if (!plane) {
> - struct drm_plane_state *state;
> -
> - /*
> - * GLK+ scalers don't have a HQ mode so it
> - * isn't necessary to change between HQ and dyn mode
> - * on those platforms.
> - */
> - if (DISPLAY_VER(dev_priv) >= 10)
> - continue;
> -
> - plane = drm_plane_from_index(&dev_priv->drm, i);
> - state = drm_atomic_get_plane_state(drm_state, plane);
> - if (IS_ERR(state)) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Failed to add [PLANE:%d] to drm_state\n",
> - plane->base.id);
> - return PTR_ERR(state);
> - }
> - }
> -
> - intel_plane = to_intel_plane(plane);
> - idx = plane->base.id;
> -
> - /* plane on different crtc cannot be a scaler user of this crtc */
> - if (drm_WARN_ON(&dev_priv->drm,
> - intel_plane->pipe != intel_crtc->pipe))
> - continue;
> -
> - plane_state = intel_atomic_get_new_plane_state(intel_state,
> - intel_plane);
> - scaler_id = &plane_state->scaler_id;
> - }
> -
> - ret = intel_atomic_setup_scaler(scaler_state, num_scalers_need,
> - intel_crtc, name, idx,
> - plane_state, scaler_id);
> - if (ret < 0)
> - return ret;
> - }
> -
> - return 0;
> -}
> -
> struct drm_atomic_state *
> intel_atomic_state_alloc(struct drm_device *dev)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 1dc439983dd9..e506f6a87344 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -52,8 +52,4 @@ struct intel_crtc_state *
> intel_atomic_get_crtc_state(struct drm_atomic_state *state,
> struct intel_crtc *crtc);
>
> -int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> - struct intel_crtc *intel_crtc,
> - struct intel_crtc_state *crtc_state);
> -
> #endif /* __INTEL_ATOMIC_H__ */
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index 0e7e014fcc71..62443834f64e 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -348,6 +348,263 @@ int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
> return 0;
> }
>
> +static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
> + int num_scalers_need, struct intel_crtc *intel_crtc,
> + const char *name, int idx,
> + struct intel_plane_state *plane_state,
> + int *scaler_id)
> +{
> + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> + int j;
> + u32 mode;
> +
> + if (*scaler_id < 0) {
> + /* find a free scaler */
> + for (j = 0; j < intel_crtc->num_scalers; j++) {
> + if (scaler_state->scalers[j].in_use)
> + continue;
> +
> + *scaler_id = j;
> + scaler_state->scalers[*scaler_id].in_use = 1;
> + break;
> + }
> + }
> +
> + if (drm_WARN(&dev_priv->drm, *scaler_id < 0,
> + "Cannot find scaler for %s:%d\n", name, idx))
> + return -EINVAL;
> +
> + /* set scaler mode */
> + if (plane_state && plane_state->hw.fb &&
> + plane_state->hw.fb->format->is_yuv &&
> + plane_state->hw.fb->format->num_planes > 1) {
> + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> +
> + if (DISPLAY_VER(dev_priv) == 9) {
> + mode = SKL_PS_SCALER_MODE_NV12;
> + } else if (icl_is_hdr_plane(dev_priv, plane->id)) {
> + /*
> + * On gen11+'s HDR planes we only use the scaler for
> + * scaling. They have a dedicated chroma upsampler, so
> + * we don't need the scaler to upsample the UV plane.
> + */
> + mode = PS_SCALER_MODE_NORMAL;
> + } else {
> + struct intel_plane *linked =
> + plane_state->planar_linked_plane;
> +
> + mode = PS_SCALER_MODE_PLANAR;
> +
> + if (linked)
> + mode |= PS_PLANE_Y_SEL(linked->id);
> + }
> + } else if (DISPLAY_VER(dev_priv) >= 10) {
> + mode = PS_SCALER_MODE_NORMAL;
> + } else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
> + /*
> + * when only 1 scaler is in use on a pipe with 2 scalers
> + * scaler 0 operates in high quality (HQ) mode.
> + * In this case use scaler 0 to take advantage of HQ mode
> + */
> + scaler_state->scalers[*scaler_id].in_use = 0;
> + *scaler_id = 0;
> + scaler_state->scalers[0].in_use = 1;
> + mode = SKL_PS_SCALER_MODE_HQ;
> + } else {
> + mode = SKL_PS_SCALER_MODE_DYN;
> + }
> +
> + /*
> + * FIXME: we should also check the scaler factors for pfit, so
> + * this shouldn't be tied directly to planes.
> + */
> + if (plane_state && plane_state->hw.fb) {
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
> + const struct drm_rect *src = &plane_state->uapi.src;
> + const struct drm_rect *dst = &plane_state->uapi.dst;
> + int hscale, vscale, max_vscale, max_hscale;
> +
> + /*
> + * FIXME: When two scalers are needed, but only one of
> + * them needs to downscale, we should make sure that
> + * the one that needs downscaling support is assigned
> + * as the first scaler, so we don't reject downscaling
> + * unnecessarily.
> + */
> +
> + if (DISPLAY_VER(dev_priv) >= 14) {
> + /*
> + * On versions 14 and up, only the first
> + * scaler supports a vertical scaling factor
> + * of more than 1.0, while a horizontal
> + * scaling factor of 3.0 is supported.
> + */
> + max_hscale = 0x30000 - 1;
> + if (*scaler_id == 0)
> + max_vscale = 0x30000 - 1;
> + else
> + max_vscale = 0x10000;
> +
> + } else if (DISPLAY_VER(dev_priv) >= 10 ||
> + !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
> + max_hscale = 0x30000 - 1;
> + max_vscale = 0x30000 - 1;
> + } else {
> + max_hscale = 0x20000 - 1;
> + max_vscale = 0x20000 - 1;
> + }
> +
> + /*
> + * FIXME: We should change the if-else block above to
> + * support HQ vs dynamic scaler properly.
> + */
> +
> + /* Check if required scaling is within limits */
> + hscale = drm_rect_calc_hscale(src, dst, 1, max_hscale);
> + vscale = drm_rect_calc_vscale(src, dst, 1, max_vscale);
> +
> + if (hscale < 0 || vscale < 0) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Scaler %d doesn't support required plane scaling\n",
> + *scaler_id);
> + drm_rect_debug_print("src: ", src, true);
> + drm_rect_debug_print("dst: ", dst, false);
> +
> + return -EINVAL;
> + }
> + }
> +
> + drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n",
> + intel_crtc->pipe, *scaler_id, name, idx);
> + scaler_state->scalers[*scaler_id].mode = mode;
> +
> + return 0;
> +}
> +
> +/**
> + * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
> + * @dev_priv: i915 device
> + * @intel_crtc: intel crtc
> + * @crtc_state: incoming crtc_state to validate and setup scalers
> + *
> + * This function sets up scalers based on staged scaling requests for
> + * a @crtc and its planes. It is called from crtc level check path. If request
> + * is a supportable request, it attaches scalers to requested planes and crtc.
> + *
> + * This function takes into account the current scaler(s) in use by any planes
> + * not being part of this atomic state
> + *
> + * Returns:
> + * 0 - scalers were setup successfully
> + * error code - otherwise
> + */
> +int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> + struct intel_crtc *intel_crtc,
> + struct intel_crtc_state *crtc_state)
> +{
> + struct drm_plane *plane = NULL;
> + struct intel_plane *intel_plane;
> + struct intel_plane_state *plane_state = NULL;
> + struct intel_crtc_scaler_state *scaler_state =
> + &crtc_state->scaler_state;
> + struct drm_atomic_state *drm_state = crtc_state->uapi.state;
> + struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
> + int num_scalers_need;
> + int i;
> +
> + num_scalers_need = hweight32(scaler_state->scaler_users);
> +
> + /*
> + * High level flow:
> + * - staged scaler requests are already in scaler_state->scaler_users
> + * - check whether staged scaling requests can be supported
> + * - add planes using scalers that aren't in current transaction
> + * - assign scalers to requested users
> + * - as part of plane commit, scalers will be committed
> + * (i.e., either attached or detached) to respective planes in hw
> + * - as part of crtc_commit, scaler will be either attached or detached
> + * to crtc in hw
> + */
> +
> + /* fail if required scalers > available scalers */
> + if (num_scalers_need > intel_crtc->num_scalers) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Too many scaling requests %d > %d\n",
> + num_scalers_need, intel_crtc->num_scalers);
> + return -EINVAL;
> + }
> +
> + /* walkthrough scaler_users bits and start assigning scalers */
> + for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
> + int *scaler_id;
> + const char *name;
> + int idx, ret;
> +
> + /* skip if scaler not required */
> + if (!(scaler_state->scaler_users & (1 << i)))
> + continue;
> +
> + if (i == SKL_CRTC_INDEX) {
> + name = "CRTC";
> + idx = intel_crtc->base.base.id;
> +
> + /* panel fitter case: assign as a crtc scaler */
> + scaler_id = &scaler_state->scaler_id;
> + } else {
> + name = "PLANE";
> +
> + /* plane scaler case: assign as a plane scaler */
> + /* find the plane that set the bit as scaler_user */
> + plane = drm_state->planes[i].ptr;
> +
> + /*
> + * to enable/disable hq mode, add planes that are using scaler
> + * into this transaction
> + */
> + if (!plane) {
> + struct drm_plane_state *state;
> +
> + /*
> + * GLK+ scalers don't have a HQ mode so it
> + * isn't necessary to change between HQ and dyn mode
> + * on those platforms.
> + */
> + if (DISPLAY_VER(dev_priv) >= 10)
> + continue;
> +
> + plane = drm_plane_from_index(&dev_priv->drm, i);
> + state = drm_atomic_get_plane_state(drm_state, plane);
> + if (IS_ERR(state)) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Failed to add [PLANE:%d] to drm_state\n",
> + plane->base.id);
> + return PTR_ERR(state);
> + }
> + }
> +
> + intel_plane = to_intel_plane(plane);
> + idx = plane->base.id;
> +
> + /* plane on different crtc cannot be a scaler user of this crtc */
> + if (drm_WARN_ON(&dev_priv->drm,
> + intel_plane->pipe != intel_crtc->pipe))
> + continue;
> +
> + plane_state = intel_atomic_get_new_plane_state(intel_state,
> + intel_plane);
> + scaler_id = &plane_state->scaler_id;
> + }
> +
> + ret = intel_atomic_setup_scaler(scaler_state, num_scalers_need,
> + intel_crtc, name, idx,
> + plane_state, scaler_id);
> + if (ret < 0)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> static int glk_coef_tap(int i)
> {
> return i % 7;
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h
> index 0097d5d08e10..f040f6ac061f 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.h
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.h
> @@ -8,17 +8,22 @@
> #include <linux/types.h>
>
> enum drm_scaling_filter;
> +enum pipe;
> struct drm_i915_private;
> +struct intel_crtc;
> struct intel_crtc_state;
> -struct intel_plane_state;
> struct intel_plane;
> -enum pipe;
> +struct intel_plane_state;
>
> int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
>
> int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
> struct intel_plane_state *plane_state);
>
> +int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> + struct intel_crtc *intel_crtc,
> + struct intel_crtc_state *crtc_state);
> +
> void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
>
> void skl_program_plane_scaler(struct intel_plane *plane,
> @@ -26,4 +31,5 @@ void skl_program_plane_scaler(struct intel_plane *plane,
> const struct intel_plane_state *plane_state);
> void skl_detach_scalers(const struct intel_crtc_state *crtc_state);
> void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state);
> +
> #endif
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH 04/15] drm/i915: Relocate skl_get_pfit_config()
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
` (2 preceding siblings ...)
2023-04-18 17:55 ` [Intel-gfx] [PATCH 03/15] drm/i915: Relocate intel_atomic_setup_scalers() Ville Syrjala
@ 2023-04-18 17:55 ` Ville Syrjala
2023-04-19 15:17 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 05/15] drm/i915: Use REG_BIT() & co for the pre-ilk pfit registers Ville Syrjala
` (15 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2023-04-18 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move skl_get_pfit_config() next to the other skl+ scaler code
and rename it to skl_scaler_get_config() so that it has a consistnet
namespace.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 49 ++------------------
drivers/gpu/drm/i915/display/skl_scaler.c | 37 +++++++++++++++
drivers/gpu/drm/i915/display/skl_scaler.h | 2 +
3 files changed, 43 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1c264c17b6e4..a450d62e431c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3224,49 +3224,6 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
}
-static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
- u32 pos, u32 size)
-{
- drm_rect_init(&crtc_state->pch_pfit.dst,
- pos >> 16, pos & 0xffff,
- size >> 16, size & 0xffff);
-}
-
-static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
- int id = -1;
- int i;
-
- /* find scaler attached to this pipe */
- for (i = 0; i < crtc->num_scalers; i++) {
- u32 ctl, pos, size;
-
- ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
- if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
- continue;
-
- id = i;
- crtc_state->pch_pfit.enabled = true;
-
- pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
- size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
-
- ilk_get_pfit_pos_size(crtc_state, pos, size);
-
- scaler_state->scalers[i].in_use = true;
- break;
- }
-
- scaler_state->scaler_id = id;
- if (id >= 0)
- scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
- else
- scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
-}
-
static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -3282,7 +3239,9 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
- ilk_get_pfit_pos_size(crtc_state, pos, size);
+ drm_rect_init(&crtc_state->pch_pfit.dst,
+ pos >> 16, pos & 0xffff,
+ size >> 16, size & 0xffff);
/*
* We currently do not free assignements of panel fitters on
@@ -3773,7 +3732,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
if (DISPLAY_VER(dev_priv) >= 9)
- skl_get_pfit_config(pipe_config);
+ skl_scaler_get_config(pipe_config);
else
ilk_get_pfit_config(pipe_config);
}
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index 62443834f64e..ec930aec21c4 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -856,3 +856,40 @@ void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
for (i = 0; i < crtc->num_scalers; i++)
skl_detach_scaler(crtc, i);
}
+
+void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
+ int id = -1;
+ int i;
+
+ /* find scaler attached to this pipe */
+ for (i = 0; i < crtc->num_scalers; i++) {
+ u32 ctl, pos, size;
+
+ ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
+ if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
+ continue;
+
+ id = i;
+ crtc_state->pch_pfit.enabled = true;
+
+ pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
+ size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
+
+ drm_rect_init(&crtc_state->pch_pfit.dst,
+ pos >> 16, pos & 0xffff,
+ size >> 16, size & 0xffff);
+
+ scaler_state->scalers[i].in_use = true;
+ break;
+ }
+
+ scaler_state->scaler_id = id;
+ if (id >= 0)
+ scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
+ else
+ scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
+}
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h
index f040f6ac061f..63f93ca03c89 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.h
+++ b/drivers/gpu/drm/i915/display/skl_scaler.h
@@ -32,4 +32,6 @@ void skl_program_plane_scaler(struct intel_plane *plane,
void skl_detach_scalers(const struct intel_crtc_state *crtc_state);
void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state);
+void skl_scaler_get_config(struct intel_crtc_state *crtc_state);
+
#endif
--
2.39.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH 04/15] drm/i915: Relocate skl_get_pfit_config()
2023-04-18 17:55 ` [Intel-gfx] [PATCH 04/15] drm/i915: Relocate skl_get_pfit_config() Ville Syrjala
@ 2023-04-19 15:17 ` Jani Nikula
0 siblings, 0 replies; 40+ messages in thread
From: Jani Nikula @ 2023-04-19 15:17 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move skl_get_pfit_config() next to the other skl+ scaler code
> and rename it to skl_scaler_get_config() so that it has a consistnet
> namespace.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 49 ++------------------
> drivers/gpu/drm/i915/display/skl_scaler.c | 37 +++++++++++++++
> drivers/gpu/drm/i915/display/skl_scaler.h | 2 +
> 3 files changed, 43 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1c264c17b6e4..a450d62e431c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3224,49 +3224,6 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
> PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
> }
>
> -static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
> - u32 pos, u32 size)
> -{
> - drm_rect_init(&crtc_state->pch_pfit.dst,
> - pos >> 16, pos & 0xffff,
> - size >> 16, size & 0xffff);
> -}
> -
> -static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
> -{
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
> - int id = -1;
> - int i;
> -
> - /* find scaler attached to this pipe */
> - for (i = 0; i < crtc->num_scalers; i++) {
> - u32 ctl, pos, size;
> -
> - ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
> - if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
> - continue;
> -
> - id = i;
> - crtc_state->pch_pfit.enabled = true;
> -
> - pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
> - size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
> -
> - ilk_get_pfit_pos_size(crtc_state, pos, size);
> -
> - scaler_state->scalers[i].in_use = true;
> - break;
> - }
> -
> - scaler_state->scaler_id = id;
> - if (id >= 0)
> - scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
> - else
> - scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
> -}
> -
> static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -3282,7 +3239,9 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
> pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
> size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
>
> - ilk_get_pfit_pos_size(crtc_state, pos, size);
> + drm_rect_init(&crtc_state->pch_pfit.dst,
> + pos >> 16, pos & 0xffff,
> + size >> 16, size & 0xffff);
>
> /*
> * We currently do not free assignements of panel fitters on
> @@ -3773,7 +3732,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
> POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
> if (DISPLAY_VER(dev_priv) >= 9)
> - skl_get_pfit_config(pipe_config);
> + skl_scaler_get_config(pipe_config);
> else
> ilk_get_pfit_config(pipe_config);
> }
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index 62443834f64e..ec930aec21c4 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -856,3 +856,40 @@ void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
> for (i = 0; i < crtc->num_scalers; i++)
> skl_detach_scaler(crtc, i);
> }
> +
> +void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
> + int id = -1;
> + int i;
> +
> + /* find scaler attached to this pipe */
> + for (i = 0; i < crtc->num_scalers; i++) {
> + u32 ctl, pos, size;
> +
> + ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
> + if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
> + continue;
> +
> + id = i;
> + crtc_state->pch_pfit.enabled = true;
> +
> + pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
> + size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
> +
> + drm_rect_init(&crtc_state->pch_pfit.dst,
> + pos >> 16, pos & 0xffff,
> + size >> 16, size & 0xffff);
> +
> + scaler_state->scalers[i].in_use = true;
> + break;
> + }
> +
> + scaler_state->scaler_id = id;
> + if (id >= 0)
> + scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
> + else
> + scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
> +}
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h
> index f040f6ac061f..63f93ca03c89 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.h
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.h
> @@ -32,4 +32,6 @@ void skl_program_plane_scaler(struct intel_plane *plane,
> void skl_detach_scalers(const struct intel_crtc_state *crtc_state);
> void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state);
>
> +void skl_scaler_get_config(struct intel_crtc_state *crtc_state);
> +
> #endif
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH 05/15] drm/i915: Use REG_BIT() & co for the pre-ilk pfit registers
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
` (3 preceding siblings ...)
2023-04-18 17:55 ` [Intel-gfx] [PATCH 04/15] drm/i915: Relocate skl_get_pfit_config() Ville Syrjala
@ 2023-04-18 17:55 ` Ville Syrjala
2023-04-19 15:28 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 06/15] drm/i915: Namespace pfit registers properly Ville Syrjala
` (14 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2023-04-18 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Modernize the gmch pfit register definitions using REG_BIT/etc.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 15 +++---
drivers/gpu/drm/i915/display/intel_overlay.c | 16 +++---
drivers/gpu/drm/i915/display/intel_panel.c | 8 +--
drivers/gpu/drm/i915/i915_reg.h | 54 ++++++++++----------
4 files changed, 48 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a450d62e431c..ea1b0e87ae35 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2749,6 +2749,7 @@ static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe;
u32 tmp;
if (!i9xx_has_pfit(dev_priv))
@@ -2759,13 +2760,13 @@ static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
return;
/* Check whether the pfit is attached to our pipe. */
- if (DISPLAY_VER(dev_priv) < 4) {
- if (crtc->pipe != PIPE_B)
- return;
- } else {
- if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
- return;
- }
+ if (DISPLAY_VER(dev_priv) >= 4)
+ pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
+ else
+ pipe = PIPE_B;
+
+ if (pipe != crtc->pipe)
+ return;
crtc_state->gmch_pfit.control = tmp;
crtc_state->gmch_pfit.pgm_ratios =
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index c12bdca8da9b..1813ab5056a1 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -935,21 +935,25 @@ static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
{
struct drm_i915_private *dev_priv = overlay->i915;
- u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL);
u32 ratio;
/* XXX: This is not the same logic as in the xorg driver, but more in
* line with the intel documentation for the i965
*/
if (DISPLAY_VER(dev_priv) >= 4) {
+ u32 tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
+
/* on i965 use the PGM reg to read out the autoscaler values */
- ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
+ ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp);
} else {
- if (pfit_control & VERT_AUTO_SCALE)
- ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
+ u32 tmp;
+
+ if (intel_de_read(dev_priv, PFIT_CONTROL) & VERT_AUTO_SCALE)
+ tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
else
- ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
- ratio >>= PFIT_VERT_SCALE_SHIFT;
+ tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
+
+ ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp);
}
overlay->pfit_vscale_ratio = ratio;
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 9acdd68b2dbc..71cd08f44ed0 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -564,8 +564,8 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
bits = panel_fitter_scaling(pipe_src_h,
adjusted_mode->crtc_vdisplay);
- *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
- bits << PFIT_VERT_SCALE_SHIFT);
+ *pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(bits) |
+ PFIT_VERT_SCALE(bits));
*pfit_control |= (PFIT_ENABLE |
VERT_INTERP_BILINEAR |
HORIZ_INTERP_BILINEAR);
@@ -579,8 +579,8 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
bits = panel_fitter_scaling(pipe_src_w,
adjusted_mode->crtc_hdisplay);
- *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
- bits << PFIT_VERT_SCALE_SHIFT);
+ *pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(bits) |
+ PFIT_VERT_SCALE(bits));
*pfit_control |= (PFIT_ENABLE |
VERT_INTERP_BILINEAR |
HORIZ_INTERP_BILINEAR);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f472baf242dc..cb8611aaaa5e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2337,35 +2337,33 @@
/* Panel fitting */
#define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
-#define PFIT_ENABLE (1 << 31)
-#define PFIT_PIPE_MASK (3 << 29)
-#define PFIT_PIPE_SHIFT 29
-#define PFIT_PIPE(pipe) ((pipe) << 29)
-#define VERT_INTERP_DISABLE (0 << 10)
-#define VERT_INTERP_BILINEAR (1 << 10)
-#define VERT_INTERP_MASK (3 << 10)
-#define VERT_AUTO_SCALE (1 << 9)
-#define HORIZ_INTERP_DISABLE (0 << 6)
-#define HORIZ_INTERP_BILINEAR (1 << 6)
-#define HORIZ_INTERP_MASK (3 << 6)
-#define HORIZ_AUTO_SCALE (1 << 5)
-#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
-#define PFIT_FILTER_FUZZY (0 << 24)
-#define PFIT_SCALING_AUTO (0 << 26)
-#define PFIT_SCALING_PROGRAMMED (1 << 26)
-#define PFIT_SCALING_PILLAR (2 << 26)
-#define PFIT_SCALING_LETTER (3 << 26)
+#define PFIT_ENABLE REG_BIT(31)
+#define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */
+#define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe))
+#define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */
+#define PFIT_SCALING_AUTO REG_FIELD_PREP(PFIT_SCALING_MASK, 0)
+#define PFIT_SCALING_PROGRAMMED REG_FIELD_PREP(PFIT_SCALING_MASK, 1)
+#define PFIT_SCALING_PILLAR REG_FIELD_PREP(PFIT_SCALING_MASK, 2)
+#define PFIT_SCALING_LETTER REG_FIELD_PREP(PFIT_SCALING_MASK, 3)
+#define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */
+#define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0)
+#define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1)
+#define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2)
+#define VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */
+#define VERT_INTERP_BILINEAR REG_FIELD_PREP(VERT_INTERP_MASK, 1)
+#define VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */
+#define HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */
+#define HORIZ_INTERP_BILINEAR REG_FIELD_PREP(HORIZ_INTERP_MASK, 1)
+#define HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */
+#define PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */
+
#define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
-/* Pre-965 */
-#define PFIT_VERT_SCALE_SHIFT 20
-#define PFIT_VERT_SCALE_MASK 0xfff00000
-#define PFIT_HORIZ_SCALE_SHIFT 4
-#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
-/* 965+ */
-#define PFIT_VERT_SCALE_SHIFT_965 16
-#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
-#define PFIT_HORIZ_SCALE_SHIFT_965 0
-#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
+#define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */
+#define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x))
+#define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */
+#define PFIT_HORIZ_SCALE(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK, (x))
+#define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */
+#define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */
#define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
--
2.39.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH 05/15] drm/i915: Use REG_BIT() & co for the pre-ilk pfit registers
2023-04-18 17:55 ` [Intel-gfx] [PATCH 05/15] drm/i915: Use REG_BIT() & co for the pre-ilk pfit registers Ville Syrjala
@ 2023-04-19 15:28 ` Jani Nikula
0 siblings, 0 replies; 40+ messages in thread
From: Jani Nikula @ 2023-04-19 15:28 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Modernize the gmch pfit register definitions using REG_BIT/etc.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 15 +++---
> drivers/gpu/drm/i915/display/intel_overlay.c | 16 +++---
> drivers/gpu/drm/i915/display/intel_panel.c | 8 +--
> drivers/gpu/drm/i915/i915_reg.h | 54 ++++++++++----------
> 4 files changed, 48 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a450d62e431c..ea1b0e87ae35 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2749,6 +2749,7 @@ static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe;
> u32 tmp;
>
> if (!i9xx_has_pfit(dev_priv))
> @@ -2759,13 +2760,13 @@ static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
> return;
>
> /* Check whether the pfit is attached to our pipe. */
> - if (DISPLAY_VER(dev_priv) < 4) {
> - if (crtc->pipe != PIPE_B)
> - return;
> - } else {
> - if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
> - return;
> - }
> + if (DISPLAY_VER(dev_priv) >= 4)
> + pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
> + else
> + pipe = PIPE_B;
> +
> + if (pipe != crtc->pipe)
> + return;
>
> crtc_state->gmch_pfit.control = tmp;
> crtc_state->gmch_pfit.pgm_ratios =
> diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
> index c12bdca8da9b..1813ab5056a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/display/intel_overlay.c
> @@ -935,21 +935,25 @@ static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
> static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
> {
> struct drm_i915_private *dev_priv = overlay->i915;
> - u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL);
> u32 ratio;
>
> /* XXX: This is not the same logic as in the xorg driver, but more in
> * line with the intel documentation for the i965
> */
> if (DISPLAY_VER(dev_priv) >= 4) {
> + u32 tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
> +
> /* on i965 use the PGM reg to read out the autoscaler values */
> - ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
> + ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp);
> } else {
> - if (pfit_control & VERT_AUTO_SCALE)
> - ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
> + u32 tmp;
> +
> + if (intel_de_read(dev_priv, PFIT_CONTROL) & VERT_AUTO_SCALE)
> + tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
> else
> - ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
> - ratio >>= PFIT_VERT_SCALE_SHIFT;
> + tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
> +
> + ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp);
> }
>
> overlay->pfit_vscale_ratio = ratio;
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
> index 9acdd68b2dbc..71cd08f44ed0 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.c
> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> @@ -564,8 +564,8 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
> bits = panel_fitter_scaling(pipe_src_h,
> adjusted_mode->crtc_vdisplay);
>
> - *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
> - bits << PFIT_VERT_SCALE_SHIFT);
> + *pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(bits) |
> + PFIT_VERT_SCALE(bits));
> *pfit_control |= (PFIT_ENABLE |
> VERT_INTERP_BILINEAR |
> HORIZ_INTERP_BILINEAR);
> @@ -579,8 +579,8 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
> bits = panel_fitter_scaling(pipe_src_w,
> adjusted_mode->crtc_hdisplay);
>
> - *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
> - bits << PFIT_VERT_SCALE_SHIFT);
> + *pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(bits) |
> + PFIT_VERT_SCALE(bits));
> *pfit_control |= (PFIT_ENABLE |
> VERT_INTERP_BILINEAR |
> HORIZ_INTERP_BILINEAR);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f472baf242dc..cb8611aaaa5e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2337,35 +2337,33 @@
>
> /* Panel fitting */
> #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
> -#define PFIT_ENABLE (1 << 31)
> -#define PFIT_PIPE_MASK (3 << 29)
> -#define PFIT_PIPE_SHIFT 29
> -#define PFIT_PIPE(pipe) ((pipe) << 29)
> -#define VERT_INTERP_DISABLE (0 << 10)
> -#define VERT_INTERP_BILINEAR (1 << 10)
> -#define VERT_INTERP_MASK (3 << 10)
> -#define VERT_AUTO_SCALE (1 << 9)
> -#define HORIZ_INTERP_DISABLE (0 << 6)
> -#define HORIZ_INTERP_BILINEAR (1 << 6)
> -#define HORIZ_INTERP_MASK (3 << 6)
> -#define HORIZ_AUTO_SCALE (1 << 5)
> -#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
> -#define PFIT_FILTER_FUZZY (0 << 24)
> -#define PFIT_SCALING_AUTO (0 << 26)
> -#define PFIT_SCALING_PROGRAMMED (1 << 26)
> -#define PFIT_SCALING_PILLAR (2 << 26)
> -#define PFIT_SCALING_LETTER (3 << 26)
> +#define PFIT_ENABLE REG_BIT(31)
> +#define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */
> +#define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe))
> +#define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */
> +#define PFIT_SCALING_AUTO REG_FIELD_PREP(PFIT_SCALING_MASK, 0)
> +#define PFIT_SCALING_PROGRAMMED REG_FIELD_PREP(PFIT_SCALING_MASK, 1)
> +#define PFIT_SCALING_PILLAR REG_FIELD_PREP(PFIT_SCALING_MASK, 2)
> +#define PFIT_SCALING_LETTER REG_FIELD_PREP(PFIT_SCALING_MASK, 3)
> +#define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */
> +#define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0)
> +#define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1)
> +#define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2)
> +#define VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */
> +#define VERT_INTERP_BILINEAR REG_FIELD_PREP(VERT_INTERP_MASK, 1)
> +#define VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */
> +#define HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */
> +#define HORIZ_INTERP_BILINEAR REG_FIELD_PREP(HORIZ_INTERP_MASK, 1)
> +#define HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */
> +#define PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */
> +
> #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
> -/* Pre-965 */
> -#define PFIT_VERT_SCALE_SHIFT 20
> -#define PFIT_VERT_SCALE_MASK 0xfff00000
> -#define PFIT_HORIZ_SCALE_SHIFT 4
> -#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
> -/* 965+ */
> -#define PFIT_VERT_SCALE_SHIFT_965 16
> -#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
> -#define PFIT_HORIZ_SCALE_SHIFT_965 0
> -#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
> +#define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */
> +#define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x))
> +#define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */
> +#define PFIT_HORIZ_SCALE(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK, (x))
> +#define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */
> +#define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */
>
> #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH 06/15] drm/i915: Namespace pfit registers properly
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
` (4 preceding siblings ...)
2023-04-18 17:55 ` [Intel-gfx] [PATCH 05/15] drm/i915: Use REG_BIT() & co for the pre-ilk pfit registers Ville Syrjala
@ 2023-04-18 17:55 ` Ville Syrjala
2023-04-19 15:28 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 07/15] drm/i915: Use REG_BIT() & co. for ilk+ pfit registers Ville Syrjala
` (13 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2023-04-18 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Give the PFIT_CONTROL bits a consistent namespace.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/display/intel_panel.c | 25 ++++++++++----------
drivers/gpu/drm/i915/i915_reg.h | 14 +++++------
4 files changed, 22 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 0de44b3631cd..8e9a3d72b83b 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -150,7 +150,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
if (DISPLAY_VER(dev_priv) < 4) {
tmp = intel_de_read(dev_priv, PFIT_CONTROL);
- crtc_state->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
+ crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE;
}
crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock;
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 1813ab5056a1..d6fe2bbabe55 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -948,7 +948,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
} else {
u32 tmp;
- if (intel_de_read(dev_priv, PFIT_CONTROL) & VERT_AUTO_SCALE)
+ if (intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_VERT_AUTO_SCALE)
tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
else
tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 71cd08f44ed0..9232a305b1e6 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -567,8 +567,8 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
*pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(bits) |
PFIT_VERT_SCALE(bits));
*pfit_control |= (PFIT_ENABLE |
- VERT_INTERP_BILINEAR |
- HORIZ_INTERP_BILINEAR);
+ PFIT_VERT_INTERP_BILINEAR |
+ PFIT_HORIZ_INTERP_BILINEAR);
}
} else if (scaled_width < scaled_height) { /* letter */
centre_vertically(adjusted_mode,
@@ -582,15 +582,16 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
*pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(bits) |
PFIT_VERT_SCALE(bits));
*pfit_control |= (PFIT_ENABLE |
- VERT_INTERP_BILINEAR |
- HORIZ_INTERP_BILINEAR);
+ PFIT_VERT_INTERP_BILINEAR |
+ PFIT_HORIZ_INTERP_BILINEAR);
}
} else {
/* Aspects match, Let hw scale both directions */
*pfit_control |= (PFIT_ENABLE |
- VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
- VERT_INTERP_BILINEAR |
- HORIZ_INTERP_BILINEAR);
+ PFIT_VERT_AUTO_SCALE |
+ PFIT_HORIZ_AUTO_SCALE |
+ PFIT_VERT_INTERP_BILINEAR |
+ PFIT_HORIZ_INTERP_BILINEAR);
}
}
@@ -638,10 +639,10 @@ static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
if (DISPLAY_VER(dev_priv) >= 4)
pfit_control |= PFIT_SCALING_AUTO;
else
- pfit_control |= (VERT_AUTO_SCALE |
- VERT_INTERP_BILINEAR |
- HORIZ_AUTO_SCALE |
- HORIZ_INTERP_BILINEAR);
+ pfit_control |= (PFIT_VERT_AUTO_SCALE |
+ PFIT_VERT_INTERP_BILINEAR |
+ PFIT_HORIZ_AUTO_SCALE |
+ PFIT_HORIZ_INTERP_BILINEAR);
}
break;
default:
@@ -662,7 +663,7 @@ static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
/* Make sure pre-965 set dither correctly for 18bpp panels. */
if (DISPLAY_VER(dev_priv) < 4 && crtc_state->pipe_bpp == 18)
- pfit_control |= PANEL_8TO6_DITHER_ENABLE;
+ pfit_control |= PFIT_PANEL_8TO6_DITHER_ENABLE;
crtc_state->gmch_pfit.control = pfit_control;
crtc_state->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cb8611aaaa5e..eea739e0b48a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2349,13 +2349,13 @@
#define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0)
#define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1)
#define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2)
-#define VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */
-#define VERT_INTERP_BILINEAR REG_FIELD_PREP(VERT_INTERP_MASK, 1)
-#define VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */
-#define HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */
-#define HORIZ_INTERP_BILINEAR REG_FIELD_PREP(HORIZ_INTERP_MASK, 1)
-#define HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */
-#define PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */
+#define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */
+#define PFIT_VERT_INTERP_BILINEAR REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1)
+#define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */
+#define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */
+#define PFIT_HORIZ_INTERP_BILINEAR REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1)
+#define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */
+#define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */
#define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
#define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */
--
2.39.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH 06/15] drm/i915: Namespace pfit registers properly
2023-04-18 17:55 ` [Intel-gfx] [PATCH 06/15] drm/i915: Namespace pfit registers properly Ville Syrjala
@ 2023-04-19 15:28 ` Jani Nikula
0 siblings, 0 replies; 40+ messages in thread
From: Jani Nikula @ 2023-04-19 15:28 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Give the PFIT_CONTROL bits a consistent namespace.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
> drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
> drivers/gpu/drm/i915/display/intel_panel.c | 25 ++++++++++----------
> drivers/gpu/drm/i915/i915_reg.h | 14 +++++------
> 4 files changed, 22 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
> index 0de44b3631cd..8e9a3d72b83b 100644
> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> @@ -150,7 +150,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
> if (DISPLAY_VER(dev_priv) < 4) {
> tmp = intel_de_read(dev_priv, PFIT_CONTROL);
>
> - crtc_state->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
> + crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE;
> }
>
> crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock;
> diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
> index 1813ab5056a1..d6fe2bbabe55 100644
> --- a/drivers/gpu/drm/i915/display/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/display/intel_overlay.c
> @@ -948,7 +948,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
> } else {
> u32 tmp;
>
> - if (intel_de_read(dev_priv, PFIT_CONTROL) & VERT_AUTO_SCALE)
> + if (intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_VERT_AUTO_SCALE)
> tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
> else
> tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
> index 71cd08f44ed0..9232a305b1e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.c
> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> @@ -567,8 +567,8 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
> *pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(bits) |
> PFIT_VERT_SCALE(bits));
> *pfit_control |= (PFIT_ENABLE |
> - VERT_INTERP_BILINEAR |
> - HORIZ_INTERP_BILINEAR);
> + PFIT_VERT_INTERP_BILINEAR |
> + PFIT_HORIZ_INTERP_BILINEAR);
> }
> } else if (scaled_width < scaled_height) { /* letter */
> centre_vertically(adjusted_mode,
> @@ -582,15 +582,16 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
> *pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(bits) |
> PFIT_VERT_SCALE(bits));
> *pfit_control |= (PFIT_ENABLE |
> - VERT_INTERP_BILINEAR |
> - HORIZ_INTERP_BILINEAR);
> + PFIT_VERT_INTERP_BILINEAR |
> + PFIT_HORIZ_INTERP_BILINEAR);
> }
> } else {
> /* Aspects match, Let hw scale both directions */
> *pfit_control |= (PFIT_ENABLE |
> - VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
> - VERT_INTERP_BILINEAR |
> - HORIZ_INTERP_BILINEAR);
> + PFIT_VERT_AUTO_SCALE |
> + PFIT_HORIZ_AUTO_SCALE |
> + PFIT_VERT_INTERP_BILINEAR |
> + PFIT_HORIZ_INTERP_BILINEAR);
> }
> }
>
> @@ -638,10 +639,10 @@ static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
> if (DISPLAY_VER(dev_priv) >= 4)
> pfit_control |= PFIT_SCALING_AUTO;
> else
> - pfit_control |= (VERT_AUTO_SCALE |
> - VERT_INTERP_BILINEAR |
> - HORIZ_AUTO_SCALE |
> - HORIZ_INTERP_BILINEAR);
> + pfit_control |= (PFIT_VERT_AUTO_SCALE |
> + PFIT_VERT_INTERP_BILINEAR |
> + PFIT_HORIZ_AUTO_SCALE |
> + PFIT_HORIZ_INTERP_BILINEAR);
> }
> break;
> default:
> @@ -662,7 +663,7 @@ static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
>
> /* Make sure pre-965 set dither correctly for 18bpp panels. */
> if (DISPLAY_VER(dev_priv) < 4 && crtc_state->pipe_bpp == 18)
> - pfit_control |= PANEL_8TO6_DITHER_ENABLE;
> + pfit_control |= PFIT_PANEL_8TO6_DITHER_ENABLE;
>
> crtc_state->gmch_pfit.control = pfit_control;
> crtc_state->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index cb8611aaaa5e..eea739e0b48a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2349,13 +2349,13 @@
> #define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0)
> #define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1)
> #define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2)
> -#define VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */
> -#define VERT_INTERP_BILINEAR REG_FIELD_PREP(VERT_INTERP_MASK, 1)
> -#define VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */
> -#define HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */
> -#define HORIZ_INTERP_BILINEAR REG_FIELD_PREP(HORIZ_INTERP_MASK, 1)
> -#define HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */
> -#define PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */
> +#define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */
> +#define PFIT_VERT_INTERP_BILINEAR REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1)
> +#define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */
> +#define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */
> +#define PFIT_HORIZ_INTERP_BILINEAR REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1)
> +#define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */
> +#define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */
>
> #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
> #define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH 07/15] drm/i915: Use REG_BIT() & co. for ilk+ pfit registers
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
` (5 preceding siblings ...)
2023-04-18 17:55 ` [Intel-gfx] [PATCH 06/15] drm/i915: Namespace pfit registers properly Ville Syrjala
@ 2023-04-18 17:55 ` Ville Syrjala
2023-04-19 15:29 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 08/15] drm/i915: Drop a useless forward declararion Ville Syrjala
` (12 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2023-04-18 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Polish the ilk+ pfit registers with REG_BIT() & co., and
also take the opportunity to unify the ivb/hsw vs. not checks
in ilk_pfit_enable() and ilk_get_pfit_config().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++--
drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++----------
2 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ea1b0e87ae35..e9000ed15e7f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3230,11 +3230,17 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 ctl, pos, size;
+ enum pipe pipe;
ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
if ((ctl & PF_ENABLE) == 0)
return;
+ if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
+ pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl);
+ else
+ pipe = crtc->pipe;
+
crtc_state->pch_pfit.enabled = true;
pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
@@ -3249,8 +3255,7 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
* ivb/hsw (since we don't use the higher upscaling modes which
* differentiates them) so just WARN about this case for now.
*/
- drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 &&
- (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
+ drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe);
}
static bool ilk_get_pipe_config(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eea739e0b48a..3c02f6c70733 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4008,16 +4008,16 @@
/* CPU panel fitter */
/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
-#define _PFA_CTL_1 0x68080
-#define _PFB_CTL_1 0x68880
-#define PF_ENABLE (1 << 31)
-#define PF_PIPE_SEL_MASK_IVB (3 << 29)
-#define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29)
-#define PF_FILTER_MASK (3 << 23)
-#define PF_FILTER_PROGRAMMED (0 << 23)
-#define PF_FILTER_MED_3x3 (1 << 23)
-#define PF_FILTER_EDGE_ENHANCE (2 << 23)
-#define PF_FILTER_EDGE_SOFTEN (3 << 23)
+#define _PFA_CTL_1 0x68080
+#define _PFB_CTL_1 0x68880
+#define PF_ENABLE REG_BIT(31)
+#define PF_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) /* ivb/hsw */
+#define PF_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe))
+#define PF_FILTER_MASK REG_GENMASK(24, 23)
+#define PF_FILTER_PROGRAMMED REG_FIELD_PREP(PF_FILTER_MASK, 0)
+#define PF_FILTER_MED_3x3 REG_FIELD_PREP(PF_FILTER_MASK, 1)
+#define PF_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 2)
+#define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3)
#define _PFA_WIN_SZ 0x68074
#define _PFB_WIN_SZ 0x68874
#define _PFA_WIN_POS 0x68070
--
2.39.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH 07/15] drm/i915: Use REG_BIT() & co. for ilk+ pfit registers
2023-04-18 17:55 ` [Intel-gfx] [PATCH 07/15] drm/i915: Use REG_BIT() & co. for ilk+ pfit registers Ville Syrjala
@ 2023-04-19 15:29 ` Jani Nikula
0 siblings, 0 replies; 40+ messages in thread
From: Jani Nikula @ 2023-04-19 15:29 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Polish the ilk+ pfit registers with REG_BIT() & co., and
> also take the opportunity to unify the ivb/hsw vs. not checks
> in ilk_pfit_enable() and ilk_get_pfit_config().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++--
> drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++----------
> 2 files changed, 17 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ea1b0e87ae35..e9000ed15e7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3230,11 +3230,17 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 ctl, pos, size;
> + enum pipe pipe;
>
> ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
> if ((ctl & PF_ENABLE) == 0)
> return;
>
> + if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
> + pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl);
> + else
> + pipe = crtc->pipe;
> +
> crtc_state->pch_pfit.enabled = true;
>
> pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
> @@ -3249,8 +3255,7 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
> * ivb/hsw (since we don't use the higher upscaling modes which
> * differentiates them) so just WARN about this case for now.
> */
> - drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 &&
> - (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
> + drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe);
> }
>
> static bool ilk_get_pipe_config(struct intel_crtc *crtc,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eea739e0b48a..3c02f6c70733 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4008,16 +4008,16 @@
>
> /* CPU panel fitter */
> /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
> -#define _PFA_CTL_1 0x68080
> -#define _PFB_CTL_1 0x68880
> -#define PF_ENABLE (1 << 31)
> -#define PF_PIPE_SEL_MASK_IVB (3 << 29)
> -#define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29)
> -#define PF_FILTER_MASK (3 << 23)
> -#define PF_FILTER_PROGRAMMED (0 << 23)
> -#define PF_FILTER_MED_3x3 (1 << 23)
> -#define PF_FILTER_EDGE_ENHANCE (2 << 23)
> -#define PF_FILTER_EDGE_SOFTEN (3 << 23)
> +#define _PFA_CTL_1 0x68080
> +#define _PFB_CTL_1 0x68880
> +#define PF_ENABLE REG_BIT(31)
> +#define PF_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) /* ivb/hsw */
> +#define PF_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe))
> +#define PF_FILTER_MASK REG_GENMASK(24, 23)
> +#define PF_FILTER_PROGRAMMED REG_FIELD_PREP(PF_FILTER_MASK, 0)
> +#define PF_FILTER_MED_3x3 REG_FIELD_PREP(PF_FILTER_MASK, 1)
> +#define PF_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 2)
> +#define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3)
> #define _PFA_WIN_SZ 0x68074
> #define _PFB_WIN_SZ 0x68874
> #define _PFA_WIN_POS 0x68070
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH 08/15] drm/i915: Drop a useless forward declararion
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
` (6 preceding siblings ...)
2023-04-18 17:55 ` [Intel-gfx] [PATCH 07/15] drm/i915: Use REG_BIT() & co. for ilk+ pfit registers Ville Syrjala
@ 2023-04-18 17:55 ` Ville Syrjala
2023-04-19 15:30 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 09/15] drm/i915: Define bitmasks for ilk pfit window pos/size Ville Syrjala
` (11 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2023-04-18 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
ilk_pfit_enable() is defined before the first use. No need
for a forwared declaration.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e9000ed15e7f..fb49d0ed61b4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -123,7 +123,6 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state);
-static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
/* returns HPLL frequency in kHz */
int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
--
2.39.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH 08/15] drm/i915: Drop a useless forward declararion
2023-04-18 17:55 ` [Intel-gfx] [PATCH 08/15] drm/i915: Drop a useless forward declararion Ville Syrjala
@ 2023-04-19 15:30 ` Jani Nikula
0 siblings, 0 replies; 40+ messages in thread
From: Jani Nikula @ 2023-04-19 15:30 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> ilk_pfit_enable() is defined before the first use. No need
> for a forwared declaration.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e9000ed15e7f..fb49d0ed61b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -123,7 +123,6 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
> static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
> static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state);
> -static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
>
> /* returns HPLL frequency in kHz */
> int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH 09/15] drm/i915: Define bitmasks for ilk pfit window pos/size
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
` (7 preceding siblings ...)
2023-04-18 17:55 ` [Intel-gfx] [PATCH 08/15] drm/i915: Drop a useless forward declararion Ville Syrjala
@ 2023-04-18 17:55 ` Ville Syrjala
2023-04-19 15:34 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 10/15] drm/i915: Remove dead scaler register defines Ville Syrjala
` (10 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2023-04-18 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Define and use the bitmasks for the x/y components
of the ilk+ panel filter window pos/size registers.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++----
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index fb49d0ed61b4..626a5f41a1f1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -812,8 +812,10 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
else
intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
PF_FILTER_MED_3x3);
- intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
- intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
+ intel_de_write_fw(dev_priv, PF_WIN_POS(pipe),
+ PF_WIN_XPOS(x) | PF_WIN_YPOS(y));
+ intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe),
+ PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height));
}
static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
@@ -3246,8 +3248,10 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
drm_rect_init(&crtc_state->pch_pfit.dst,
- pos >> 16, pos & 0xffff,
- size >> 16, size & 0xffff);
+ REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),
+ REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),
+ REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),
+ REG_FIELD_GET(PF_WIN_YSIZE_MASK, size));
/*
* We currently do not free assignements of panel fitters on
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3c02f6c70733..75e1f30adda1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4020,8 +4020,16 @@
#define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3)
#define _PFA_WIN_SZ 0x68074
#define _PFB_WIN_SZ 0x68874
+#define PF_WIN_XSIZE_MASK REG_GENMASK(28, 16)
+#define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w))
+#define PF_WIN_YSIZE_MASK REG_GENMASK(11, 0)
+#define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h))
#define _PFA_WIN_POS 0x68070
#define _PFB_WIN_POS 0x68870
+#define PF_WIN_XPOS_MASK REG_GENMASK(28, 16)
+#define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x))
+#define PF_WIN_YPOS_MASK REG_GENMASK(11, 0)
+#define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y))
#define _PFA_VSCALE 0x68084
#define _PFB_VSCALE 0x68884
#define _PFA_HSCALE 0x68090
--
2.39.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH 09/15] drm/i915: Define bitmasks for ilk pfit window pos/size
2023-04-18 17:55 ` [Intel-gfx] [PATCH 09/15] drm/i915: Define bitmasks for ilk pfit window pos/size Ville Syrjala
@ 2023-04-19 15:34 ` Jani Nikula
2023-04-20 12:09 ` Ville Syrjälä
0 siblings, 1 reply; 40+ messages in thread
From: Jani Nikula @ 2023-04-19 15:34 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Define and use the bitmasks for the x/y components
> of the ilk+ panel filter window pos/size registers.
This reduces the field sizes by 3-4 bits. Maybe that's what they're in
the spec, but it's at least worth mentioning here.
BR,
Jani.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++----
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> 2 files changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index fb49d0ed61b4..626a5f41a1f1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -812,8 +812,10 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
> else
> intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
> PF_FILTER_MED_3x3);
> - intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
> - intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
> + intel_de_write_fw(dev_priv, PF_WIN_POS(pipe),
> + PF_WIN_XPOS(x) | PF_WIN_YPOS(y));
> + intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe),
> + PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height));
> }
>
> static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
> @@ -3246,8 +3248,10 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
> size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
>
> drm_rect_init(&crtc_state->pch_pfit.dst,
> - pos >> 16, pos & 0xffff,
> - size >> 16, size & 0xffff);
> + REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),
> + REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),
> + REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),
> + REG_FIELD_GET(PF_WIN_YSIZE_MASK, size));
>
> /*
> * We currently do not free assignements of panel fitters on
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3c02f6c70733..75e1f30adda1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4020,8 +4020,16 @@
> #define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3)
> #define _PFA_WIN_SZ 0x68074
> #define _PFB_WIN_SZ 0x68874
> +#define PF_WIN_XSIZE_MASK REG_GENMASK(28, 16)
> +#define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w))
> +#define PF_WIN_YSIZE_MASK REG_GENMASK(11, 0)
> +#define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h))
> #define _PFA_WIN_POS 0x68070
> #define _PFB_WIN_POS 0x68870
> +#define PF_WIN_XPOS_MASK REG_GENMASK(28, 16)
> +#define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x))
> +#define PF_WIN_YPOS_MASK REG_GENMASK(11, 0)
> +#define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y))
> #define _PFA_VSCALE 0x68084
> #define _PFB_VSCALE 0x68884
> #define _PFA_HSCALE 0x68090
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [Intel-gfx] [PATCH 09/15] drm/i915: Define bitmasks for ilk pfit window pos/size
2023-04-19 15:34 ` Jani Nikula
@ 2023-04-20 12:09 ` Ville Syrjälä
2023-04-25 10:49 ` Ville Syrjälä
0 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjälä @ 2023-04-20 12:09 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Apr 19, 2023 at 06:34:00PM +0300, Jani Nikula wrote:
> On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Define and use the bitmasks for the x/y components
> > of the ilk+ panel filter window pos/size registers.
>
> This reduces the field sizes by 3-4 bits. Maybe that's what they're in
> the spec, but it's at least worth mentioning here.
Aye. I just double checked this and on BDW these are in
fact the only bits that can be set in the registers. On
older hw every bit can apparently be set, but resumably
the high bits just have no effect. And intel_mode_valid()
will anyway reject modes with bigger hdisplay/vdisplay
so we should never see out of bounds values here.
>
> BR,
> Jani.
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++----
> > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> > 2 files changed, 16 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index fb49d0ed61b4..626a5f41a1f1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -812,8 +812,10 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
> > else
> > intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
> > PF_FILTER_MED_3x3);
> > - intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
> > - intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
> > + intel_de_write_fw(dev_priv, PF_WIN_POS(pipe),
> > + PF_WIN_XPOS(x) | PF_WIN_YPOS(y));
> > + intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe),
> > + PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height));
> > }
> >
> > static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
> > @@ -3246,8 +3248,10 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
> > size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
> >
> > drm_rect_init(&crtc_state->pch_pfit.dst,
> > - pos >> 16, pos & 0xffff,
> > - size >> 16, size & 0xffff);
> > + REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),
> > + REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),
> > + REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),
> > + REG_FIELD_GET(PF_WIN_YSIZE_MASK, size));
> >
> > /*
> > * We currently do not free assignements of panel fitters on
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 3c02f6c70733..75e1f30adda1 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4020,8 +4020,16 @@
> > #define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3)
> > #define _PFA_WIN_SZ 0x68074
> > #define _PFB_WIN_SZ 0x68874
> > +#define PF_WIN_XSIZE_MASK REG_GENMASK(28, 16)
> > +#define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w))
> > +#define PF_WIN_YSIZE_MASK REG_GENMASK(11, 0)
> > +#define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h))
> > #define _PFA_WIN_POS 0x68070
> > #define _PFB_WIN_POS 0x68870
> > +#define PF_WIN_XPOS_MASK REG_GENMASK(28, 16)
> > +#define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x))
> > +#define PF_WIN_YPOS_MASK REG_GENMASK(11, 0)
> > +#define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y))
> > #define _PFA_VSCALE 0x68084
> > #define _PFB_VSCALE 0x68884
> > #define _PFA_HSCALE 0x68090
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [Intel-gfx] [PATCH 09/15] drm/i915: Define bitmasks for ilk pfit window pos/size
2023-04-20 12:09 ` Ville Syrjälä
@ 2023-04-25 10:49 ` Ville Syrjälä
0 siblings, 0 replies; 40+ messages in thread
From: Ville Syrjälä @ 2023-04-25 10:49 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Apr 20, 2023 at 03:09:11PM +0300, Ville Syrjälä wrote:
> On Wed, Apr 19, 2023 at 06:34:00PM +0300, Jani Nikula wrote:
> > On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Define and use the bitmasks for the x/y components
> > > of the ilk+ panel filter window pos/size registers.
> >
> > This reduces the field sizes by 3-4 bits. Maybe that's what they're in
> > the spec, but it's at least worth mentioning here.
>
> Aye. I just double checked this and on BDW these are in
> fact the only bits that can be set in the registers. On
> older hw every bit can apparently be set, but resumably
> the high bits just have no effect. And intel_mode_valid()
> will anyway reject modes with bigger hdisplay/vdisplay
> so we should never see out of bounds values here.
After pondering this a bit more, I think I'll go back to
16bit masks to make the thing more future proof. Seems unlikely
we'd get any other kinds of bits getting added to these registers
and we are using the full 16 bit masks also for the transcoder
timing registers and PIPESRC.
>
> >
> > BR,
> > Jani.
> >
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++----
> > > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> > > 2 files changed, 16 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index fb49d0ed61b4..626a5f41a1f1 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -812,8 +812,10 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
> > > else
> > > intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
> > > PF_FILTER_MED_3x3);
> > > - intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
> > > - intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
> > > + intel_de_write_fw(dev_priv, PF_WIN_POS(pipe),
> > > + PF_WIN_XPOS(x) | PF_WIN_YPOS(y));
> > > + intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe),
> > > + PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height));
> > > }
> > >
> > > static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
> > > @@ -3246,8 +3248,10 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
> > > size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
> > >
> > > drm_rect_init(&crtc_state->pch_pfit.dst,
> > > - pos >> 16, pos & 0xffff,
> > > - size >> 16, size & 0xffff);
> > > + REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),
> > > + REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),
> > > + REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),
> > > + REG_FIELD_GET(PF_WIN_YSIZE_MASK, size));
> > >
> > > /*
> > > * We currently do not free assignements of panel fitters on
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 3c02f6c70733..75e1f30adda1 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -4020,8 +4020,16 @@
> > > #define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3)
> > > #define _PFA_WIN_SZ 0x68074
> > > #define _PFB_WIN_SZ 0x68874
> > > +#define PF_WIN_XSIZE_MASK REG_GENMASK(28, 16)
> > > +#define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w))
> > > +#define PF_WIN_YSIZE_MASK REG_GENMASK(11, 0)
> > > +#define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h))
> > > #define _PFA_WIN_POS 0x68070
> > > #define _PFB_WIN_POS 0x68870
> > > +#define PF_WIN_XPOS_MASK REG_GENMASK(28, 16)
> > > +#define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x))
> > > +#define PF_WIN_YPOS_MASK REG_GENMASK(11, 0)
> > > +#define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y))
> > > #define _PFA_VSCALE 0x68084
> > > #define _PFB_VSCALE 0x68884
> > > #define _PFA_HSCALE 0x68090
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
>
> --
> Ville Syrjälä
> Intel
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH 10/15] drm/i915: Remove dead scaler register defines
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
` (8 preceding siblings ...)
2023-04-18 17:55 ` [Intel-gfx] [PATCH 09/15] drm/i915: Define bitmasks for ilk pfit window pos/size Ville Syrjala
@ 2023-04-18 17:55 ` Ville Syrjala
2023-04-19 15:35 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 11/15] drm/i915: Rename skl+ scaler binding bits Ville Syrjala
` (9 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2023-04-18 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We have some duplicated scaler register defines that are
never used. Remove them.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 75e1f30adda1..919d999a2345 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4041,18 +4041,6 @@
#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
-#define _PSA_CTL 0x68180
-#define _PSB_CTL 0x68980
-#define PS_ENABLE (1 << 31)
-#define _PSA_WIN_SZ 0x68174
-#define _PSB_WIN_SZ 0x68974
-#define _PSA_WIN_POS 0x68170
-#define _PSB_WIN_POS 0x68970
-
-#define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
-#define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
-#define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
-
/*
* Skylake scalers
*/
--
2.39.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH 10/15] drm/i915: Remove dead scaler register defines
2023-04-18 17:55 ` [Intel-gfx] [PATCH 10/15] drm/i915: Remove dead scaler register defines Ville Syrjala
@ 2023-04-19 15:35 ` Jani Nikula
0 siblings, 0 replies; 40+ messages in thread
From: Jani Nikula @ 2023-04-19 15:35 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We have some duplicated scaler register defines that are
> never used. Remove them.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 12 ------------
> 1 file changed, 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 75e1f30adda1..919d999a2345 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4041,18 +4041,6 @@
> #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
> #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
>
> -#define _PSA_CTL 0x68180
> -#define _PSB_CTL 0x68980
> -#define PS_ENABLE (1 << 31)
> -#define _PSA_WIN_SZ 0x68174
> -#define _PSB_WIN_SZ 0x68974
> -#define _PSA_WIN_POS 0x68170
> -#define _PSB_WIN_POS 0x68970
> -
> -#define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
> -#define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
> -#define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
> -
> /*
> * Skylake scalers
> */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH 11/15] drm/i915: Rename skl+ scaler binding bits
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
` (9 preceding siblings ...)
2023-04-18 17:55 ` [Intel-gfx] [PATCH 10/15] drm/i915: Remove dead scaler register defines Ville Syrjala
@ 2023-04-18 17:55 ` Ville Syrjala
2023-04-18 19:36 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
` (2 more replies)
2023-04-18 17:55 ` [Intel-gfx] [PATCH 12/15] drm/i915: s/PS_COEE_INDEX_AUTO_INC/PS_COEF_INDEX_AUTO_INC/ Ville Syrjala
` (8 subsequent siblings)
19 siblings, 3 replies; 40+ messages in thread
From: Ville Syrjala @ 2023-04-18 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename the scaler binding bits to match the spec more closely.
Also call the parameters 'plane_id' to make it a bit more clear
what to pass in.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/skl_scaler.c | 12 ++++++------
drivers/gpu/drm/i915/i915_reg.h | 9 +++++----
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index ec930aec21c4..a96f8ecbeec1 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -396,7 +396,7 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat
mode = PS_SCALER_MODE_PLANAR;
if (linked)
- mode |= PS_PLANE_Y_SEL(linked->id);
+ mode |= PS_BINDING_Y_PLANE(linked->id);
}
} else if (DISPLAY_VER(dev_priv) >= 10) {
mode = PS_SCALER_MODE_NORMAL;
@@ -741,8 +741,8 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
id = scaler_state->scaler_id;
- ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
- ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode;
+ ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode |
+ skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
skl_scaler_setup_filter(dev_priv, pipe, id, 0,
crtc_state->hw.scaling_filter);
@@ -804,8 +804,8 @@ skl_program_plane_scaler(struct intel_plane *plane,
uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
}
- ps_ctrl = skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
- ps_ctrl |= PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode;
+ ps_ctrl = PS_SCALER_EN | PS_BINDING_PLANE(plane->id) | scaler->mode |
+ skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0,
plane_state->hw.scaling_filter);
@@ -870,7 +870,7 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
u32 ctl, pos, size;
ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
- if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
+ if ((ctl & (PS_SCALER_EN | PS_BINDING_MASK)) != (PS_SCALER_EN | PS_BINDING_PIPE))
continue;
id = i;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 919d999a2345..f8e6b86facc3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4056,8 +4056,9 @@
#define SKL_PS_SCALER_MODE_NV12 (2 << 28)
#define PS_SCALER_MODE_PLANAR (1 << 29)
#define PS_SCALER_MODE_NORMAL (0 << 29)
-#define PS_PLANE_SEL_MASK (7 << 25)
-#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
+#define PS_BINDING_MASK (7 << 25)
+#define PS_BINDING_PIPE (0 << 25)
+#define PS_BINDING_PLANE(plane_id) (((plane_id) + 1) << 25)
#define PS_FILTER_MASK (3 << 23)
#define PS_FILTER_MEDIUM (0 << 23)
#define PS_FILTER_PROGRAMMED (1 << 23)
@@ -4073,8 +4074,8 @@
#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
-#define PS_PLANE_Y_SEL_MASK (7 << 5)
-#define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
+#define PS_BINDING_Y_MASK (7 << 5)
+#define PS_BINDING_Y_PLANE(plane_id) (((plane_id) + 1) << 5)
#define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4)
#define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3)
#define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2)
--
2.39.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v2 11/15] drm/i915: Rename skl+ scaler binding bits
2023-04-18 17:55 ` [Intel-gfx] [PATCH 11/15] drm/i915: Rename skl+ scaler binding bits Ville Syrjala
@ 2023-04-18 19:36 ` Ville Syrjala
2023-04-19 15:38 ` Jani Nikula
2023-04-18 22:06 ` [Intel-gfx] [PATCH " kernel test robot
2023-04-19 15:38 ` Jani Nikula
2 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2023-04-18 19:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename the scaler binding bits to match the spec more closely.
Also call the parameters 'plane_id' to make it a bit more clear
what to pass in.
v2: Don't break gvt
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/skl_scaler.c | 12 ++++++------
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 9 +++++----
3 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index ec930aec21c4..a96f8ecbeec1 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -396,7 +396,7 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat
mode = PS_SCALER_MODE_PLANAR;
if (linked)
- mode |= PS_PLANE_Y_SEL(linked->id);
+ mode |= PS_BINDING_Y_PLANE(linked->id);
}
} else if (DISPLAY_VER(dev_priv) >= 10) {
mode = PS_SCALER_MODE_NORMAL;
@@ -741,8 +741,8 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
id = scaler_state->scaler_id;
- ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
- ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode;
+ ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode |
+ skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
skl_scaler_setup_filter(dev_priv, pipe, id, 0,
crtc_state->hw.scaling_filter);
@@ -804,8 +804,8 @@ skl_program_plane_scaler(struct intel_plane *plane,
uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
}
- ps_ctrl = skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
- ps_ctrl |= PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode;
+ ps_ctrl = PS_SCALER_EN | PS_BINDING_PLANE(plane->id) | scaler->mode |
+ skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0,
plane_state->hw.scaling_filter);
@@ -870,7 +870,7 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
u32 ctl, pos, size;
ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
- if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
+ if ((ctl & (PS_SCALER_EN | PS_BINDING_MASK)) != (PS_SCALER_EN | PS_BINDING_PIPE))
continue;
id = i;
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 4b45a041ac5c..a9f7fa9b90bd 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1562,7 +1562,7 @@ static int pf_write(struct intel_vgpu *vgpu,
if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
- offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
+ offset == _PS_1C_CTRL) && (val & PS_BINDING_MASK) != PS_BINDING_PIPE) {
drm_WARN_ONCE(&i915->drm, true,
"VM(%d): guest is trying to scaling a plane\n",
vgpu->id);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 919d999a2345..f8e6b86facc3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4056,8 +4056,9 @@
#define SKL_PS_SCALER_MODE_NV12 (2 << 28)
#define PS_SCALER_MODE_PLANAR (1 << 29)
#define PS_SCALER_MODE_NORMAL (0 << 29)
-#define PS_PLANE_SEL_MASK (7 << 25)
-#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
+#define PS_BINDING_MASK (7 << 25)
+#define PS_BINDING_PIPE (0 << 25)
+#define PS_BINDING_PLANE(plane_id) (((plane_id) + 1) << 25)
#define PS_FILTER_MASK (3 << 23)
#define PS_FILTER_MEDIUM (0 << 23)
#define PS_FILTER_PROGRAMMED (1 << 23)
@@ -4073,8 +4074,8 @@
#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
-#define PS_PLANE_Y_SEL_MASK (7 << 5)
-#define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
+#define PS_BINDING_Y_MASK (7 << 5)
+#define PS_BINDING_Y_PLANE(plane_id) (((plane_id) + 1) << 5)
#define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4)
#define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3)
#define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2)
--
2.39.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH v2 11/15] drm/i915: Rename skl+ scaler binding bits
2023-04-18 19:36 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
@ 2023-04-19 15:38 ` Jani Nikula
0 siblings, 0 replies; 40+ messages in thread
From: Jani Nikula @ 2023-04-19 15:38 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename the scaler binding bits to match the spec more closely.
> Also call the parameters 'plane_id' to make it a bit more clear
> what to pass in.
>
> v2: Don't break gvt
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_scaler.c | 12 ++++++------
> drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 9 +++++----
> 3 files changed, 12 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index ec930aec21c4..a96f8ecbeec1 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -396,7 +396,7 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat
> mode = PS_SCALER_MODE_PLANAR;
>
> if (linked)
> - mode |= PS_PLANE_Y_SEL(linked->id);
> + mode |= PS_BINDING_Y_PLANE(linked->id);
> }
> } else if (DISPLAY_VER(dev_priv) >= 10) {
> mode = PS_SCALER_MODE_NORMAL;
> @@ -741,8 +741,8 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
>
> id = scaler_state->scaler_id;
>
> - ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
> - ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode;
> + ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode |
> + skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
>
> skl_scaler_setup_filter(dev_priv, pipe, id, 0,
> crtc_state->hw.scaling_filter);
> @@ -804,8 +804,8 @@ skl_program_plane_scaler(struct intel_plane *plane,
> uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
> }
>
> - ps_ctrl = skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
> - ps_ctrl |= PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode;
> + ps_ctrl = PS_SCALER_EN | PS_BINDING_PLANE(plane->id) | scaler->mode |
> + skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
>
> skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0,
> plane_state->hw.scaling_filter);
> @@ -870,7 +870,7 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
> u32 ctl, pos, size;
>
> ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
> - if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
> + if ((ctl & (PS_SCALER_EN | PS_BINDING_MASK)) != (PS_SCALER_EN | PS_BINDING_PIPE))
> continue;
>
> id = i;
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 4b45a041ac5c..a9f7fa9b90bd 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -1562,7 +1562,7 @@ static int pf_write(struct intel_vgpu *vgpu,
>
> if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
> offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
> - offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
> + offset == _PS_1C_CTRL) && (val & PS_BINDING_MASK) != PS_BINDING_PIPE) {
> drm_WARN_ONCE(&i915->drm, true,
> "VM(%d): guest is trying to scaling a plane\n",
> vgpu->id);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 919d999a2345..f8e6b86facc3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4056,8 +4056,9 @@
> #define SKL_PS_SCALER_MODE_NV12 (2 << 28)
> #define PS_SCALER_MODE_PLANAR (1 << 29)
> #define PS_SCALER_MODE_NORMAL (0 << 29)
> -#define PS_PLANE_SEL_MASK (7 << 25)
> -#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
> +#define PS_BINDING_MASK (7 << 25)
> +#define PS_BINDING_PIPE (0 << 25)
> +#define PS_BINDING_PLANE(plane_id) (((plane_id) + 1) << 25)
> #define PS_FILTER_MASK (3 << 23)
> #define PS_FILTER_MEDIUM (0 << 23)
> #define PS_FILTER_PROGRAMMED (1 << 23)
> @@ -4073,8 +4074,8 @@
> #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
> #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
> #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
> -#define PS_PLANE_Y_SEL_MASK (7 << 5)
> -#define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
> +#define PS_BINDING_Y_MASK (7 << 5)
> +#define PS_BINDING_Y_PLANE(plane_id) (((plane_id) + 1) << 5)
> #define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4)
> #define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3)
> #define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [Intel-gfx] [PATCH 11/15] drm/i915: Rename skl+ scaler binding bits
2023-04-18 17:55 ` [Intel-gfx] [PATCH 11/15] drm/i915: Rename skl+ scaler binding bits Ville Syrjala
2023-04-18 19:36 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
@ 2023-04-18 22:06 ` kernel test robot
2023-04-19 15:38 ` Jani Nikula
2 siblings, 0 replies; 40+ messages in thread
From: kernel test robot @ 2023-04-18 22:06 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: oe-kbuild-all
Hi Ville,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-tip/drm-tip]
url: https://github.com/intel-lab-lkp/linux/commits/Ville-Syrjala/drm-i915-Check-pipe-source-size-when-using-skl-scalers/20230419-015829
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link: https://lore.kernel.org/r/20230418175528.13117-12-ville.syrjala%40linux.intel.com
patch subject: [Intel-gfx] [PATCH 11/15] drm/i915: Rename skl+ scaler binding bits
config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20230419/202304190547.OlyNaAi3-lkp@intel.com/config)
compiler: gcc-11 (Debian 11.3.0-8) 11.3.0
reproduce (this is a W=1 build):
# https://github.com/intel-lab-lkp/linux/commit/19871303e2971d47d4ac0557533295744c04cfd4
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Check-pipe-source-size-when-using-skl-scalers/20230419-015829
git checkout 19871303e2971d47d4ac0557533295744c04cfd4
# save the config file
mkdir build_dir && cp config build_dir/.config
make W=1 O=build_dir ARCH=x86_64 olddefconfig
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202304190547.OlyNaAi3-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/gvt/handlers.c: In function 'pf_write':
>> drivers/gpu/drm/i915/gvt/handlers.c:1565:45: error: 'PS_PLANE_SEL_MASK' undeclared (first use in this function); did you mean 'PS_PHASE_MASK'?
1565 | offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
| ^~~~~~~~~~~~~~~~~
| PS_PHASE_MASK
drivers/gpu/drm/i915/gvt/handlers.c:1565:45: note: each undeclared identifier is reported only once for each function it appears in
vim +1565 drivers/gpu/drm/i915/gvt/handlers.c
e39c5add322184 Zhi Wang 2016-09-02 1556
04d348ae3f0aea Zhi Wang 2016-04-25 1557 static int pf_write(struct intel_vgpu *vgpu,
04d348ae3f0aea Zhi Wang 2016-04-25 1558 unsigned int offset, void *p_data, unsigned int bytes)
04d348ae3f0aea Zhi Wang 2016-04-25 1559 {
a61ac1e75105a0 Chris Wilson 2020-03-06 1560 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
04d348ae3f0aea Zhi Wang 2016-04-25 1561 u32 val = *(u32 *)p_data;
04d348ae3f0aea Zhi Wang 2016-04-25 1562
04d348ae3f0aea Zhi Wang 2016-04-25 1563 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
04d348ae3f0aea Zhi Wang 2016-04-25 1564 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
04d348ae3f0aea Zhi Wang 2016-04-25 @1565 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
12d5861973c70f Pankaj Bharadiya 2020-02-20 1566 drm_WARN_ONCE(&i915->drm, true,
12d5861973c70f Pankaj Bharadiya 2020-02-20 1567 "VM(%d): guest is trying to scaling a plane\n",
04d348ae3f0aea Zhi Wang 2016-04-25 1568 vgpu->id);
04d348ae3f0aea Zhi Wang 2016-04-25 1569 return 0;
04d348ae3f0aea Zhi Wang 2016-04-25 1570 }
04d348ae3f0aea Zhi Wang 2016-04-25 1571
04d348ae3f0aea Zhi Wang 2016-04-25 1572 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
04d348ae3f0aea Zhi Wang 2016-04-25 1573 }
04d348ae3f0aea Zhi Wang 2016-04-25 1574
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH 11/15] drm/i915: Rename skl+ scaler binding bits
2023-04-18 17:55 ` [Intel-gfx] [PATCH 11/15] drm/i915: Rename skl+ scaler binding bits Ville Syrjala
2023-04-18 19:36 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2023-04-18 22:06 ` [Intel-gfx] [PATCH " kernel test robot
@ 2023-04-19 15:38 ` Jani Nikula
2 siblings, 0 replies; 40+ messages in thread
From: Jani Nikula @ 2023-04-19 15:38 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename the scaler binding bits to match the spec more closely.
> Also call the parameters 'plane_id' to make it a bit more clear
> what to pass in.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_scaler.c | 12 ++++++------
> drivers/gpu/drm/i915/i915_reg.h | 9 +++++----
> 2 files changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index ec930aec21c4..a96f8ecbeec1 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -396,7 +396,7 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat
> mode = PS_SCALER_MODE_PLANAR;
>
> if (linked)
> - mode |= PS_PLANE_Y_SEL(linked->id);
> + mode |= PS_BINDING_Y_PLANE(linked->id);
> }
> } else if (DISPLAY_VER(dev_priv) >= 10) {
> mode = PS_SCALER_MODE_NORMAL;
> @@ -741,8 +741,8 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
>
> id = scaler_state->scaler_id;
>
> - ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
> - ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode;
> + ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode |
> + skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
>
> skl_scaler_setup_filter(dev_priv, pipe, id, 0,
> crtc_state->hw.scaling_filter);
> @@ -804,8 +804,8 @@ skl_program_plane_scaler(struct intel_plane *plane,
> uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
> }
>
> - ps_ctrl = skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
> - ps_ctrl |= PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode;
> + ps_ctrl = PS_SCALER_EN | PS_BINDING_PLANE(plane->id) | scaler->mode |
> + skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
>
> skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0,
> plane_state->hw.scaling_filter);
> @@ -870,7 +870,7 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
> u32 ctl, pos, size;
>
> ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
> - if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
> + if ((ctl & (PS_SCALER_EN | PS_BINDING_MASK)) != (PS_SCALER_EN | PS_BINDING_PIPE))
> continue;
>
> id = i;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 919d999a2345..f8e6b86facc3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4056,8 +4056,9 @@
> #define SKL_PS_SCALER_MODE_NV12 (2 << 28)
> #define PS_SCALER_MODE_PLANAR (1 << 29)
> #define PS_SCALER_MODE_NORMAL (0 << 29)
> -#define PS_PLANE_SEL_MASK (7 << 25)
> -#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
> +#define PS_BINDING_MASK (7 << 25)
> +#define PS_BINDING_PIPE (0 << 25)
> +#define PS_BINDING_PLANE(plane_id) (((plane_id) + 1) << 25)
> #define PS_FILTER_MASK (3 << 23)
> #define PS_FILTER_MEDIUM (0 << 23)
> #define PS_FILTER_PROGRAMMED (1 << 23)
> @@ -4073,8 +4074,8 @@
> #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
> #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
> #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
> -#define PS_PLANE_Y_SEL_MASK (7 << 5)
> -#define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
> +#define PS_BINDING_Y_MASK (7 << 5)
> +#define PS_BINDING_Y_PLANE(plane_id) (((plane_id) + 1) << 5)
> #define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4)
> #define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3)
> #define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH 12/15] drm/i915: s/PS_COEE_INDEX_AUTO_INC/PS_COEF_INDEX_AUTO_INC/
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
` (10 preceding siblings ...)
2023-04-18 17:55 ` [Intel-gfx] [PATCH 11/15] drm/i915: Rename skl+ scaler binding bits Ville Syrjala
@ 2023-04-18 17:55 ` Ville Syrjala
2023-04-19 15:38 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 13/15] drm/i915: Define bitmasks for sik+ scaler window pos/size Ville Syrjala
` (7 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2023-04-18 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fix a typo in the PS_COEF_INDEX_AUTO_INC define.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/skl_scaler.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index a96f8ecbeec1..4437d130293a 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -658,7 +658,7 @@ static void glk_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
int i;
intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set),
- PS_COEE_INDEX_AUTO_INC);
+ PS_COEF_INDEX_AUTO_INC);
for (i = 0; i < 17 * 7; i += 2) {
u32 tmp;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f8e6b86facc3..a5ae291de55b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4146,7 +4146,7 @@
#define _PS_COEF_SET0_INDEX_2A 0x68298
#define _PS_COEF_SET0_INDEX_1B 0x68998
#define _PS_COEF_SET0_INDEX_2B 0x68A98
-#define PS_COEE_INDEX_AUTO_INC (1 << 10)
+#define PS_COEF_INDEX_AUTO_INC (1 << 10)
#define _PS_COEF_SET0_DATA_1A 0x6819C
#define _PS_COEF_SET0_DATA_2A 0x6829C
--
2.39.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH 12/15] drm/i915: s/PS_COEE_INDEX_AUTO_INC/PS_COEF_INDEX_AUTO_INC/
2023-04-18 17:55 ` [Intel-gfx] [PATCH 12/15] drm/i915: s/PS_COEE_INDEX_AUTO_INC/PS_COEF_INDEX_AUTO_INC/ Ville Syrjala
@ 2023-04-19 15:38 ` Jani Nikula
0 siblings, 0 replies; 40+ messages in thread
From: Jani Nikula @ 2023-04-19 15:38 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Fix a typo in the PS_COEF_INDEX_AUTO_INC define.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_scaler.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index a96f8ecbeec1..4437d130293a 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -658,7 +658,7 @@ static void glk_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
> int i;
>
> intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set),
> - PS_COEE_INDEX_AUTO_INC);
> + PS_COEF_INDEX_AUTO_INC);
>
> for (i = 0; i < 17 * 7; i += 2) {
> u32 tmp;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f8e6b86facc3..a5ae291de55b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4146,7 +4146,7 @@
> #define _PS_COEF_SET0_INDEX_2A 0x68298
> #define _PS_COEF_SET0_INDEX_1B 0x68998
> #define _PS_COEF_SET0_INDEX_2B 0x68A98
> -#define PS_COEE_INDEX_AUTO_INC (1 << 10)
> +#define PS_COEF_INDEX_AUTO_INC (1 << 10)
>
> #define _PS_COEF_SET0_DATA_1A 0x6819C
> #define _PS_COEF_SET0_DATA_2A 0x6829C
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH 13/15] drm/i915: Define bitmasks for sik+ scaler window pos/size
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
` (11 preceding siblings ...)
2023-04-18 17:55 ` [Intel-gfx] [PATCH 12/15] drm/i915: s/PS_COEE_INDEX_AUTO_INC/PS_COEF_INDEX_AUTO_INC/ Ville Syrjala
@ 2023-04-18 17:55 ` Ville Syrjala
2023-04-19 15:41 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 14/15] drm/i915: Use REG_BIT() & co. for pipe scaler registers Ville Syrjala
` (6 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2023-04-18 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Define and use the bitmasks for the x/y components
of the skl+ scaler window pos/size registers.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/skl_scaler.c | 14 ++++++++------
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index 4437d130293a..1e7c97243fcf 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -754,9 +754,9 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
- x << 16 | y);
+ PS_WIN_XPOS(x) | PS_WIN_YPOS(y));
intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
- width << 16 | height);
+ PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height));
}
void
@@ -816,9 +816,9 @@ skl_program_plane_scaler(struct intel_plane *plane,
intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id),
PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id),
- (crtc_x << 16) | crtc_y);
+ PS_WIN_XPOS(crtc_x) | PS_WIN_YPOS(crtc_y));
intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id),
- (crtc_w << 16) | crtc_h);
+ PS_WIN_XSIZE(crtc_w) | PS_WIN_YSIZE(crtc_h));
}
static void skl_detach_scaler(struct intel_crtc *crtc, int id)
@@ -880,8 +880,10 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
drm_rect_init(&crtc_state->pch_pfit.dst,
- pos >> 16, pos & 0xffff,
- size >> 16, size & 0xffff);
+ REG_FIELD_GET(PS_WIN_XPOS_MASK, pos),
+ REG_FIELD_GET(PS_WIN_YPOS_MASK, pos),
+ REG_FIELD_GET(PS_WIN_XSIZE_MASK, size),
+ REG_FIELD_GET(PS_WIN_YSIZE_MASK, size));
scaler_state->scalers[i].in_use = true;
break;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a5ae291de55b..68581864fb44 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4101,12 +4101,20 @@
#define _PS_WIN_POS_1B 0x68970
#define _PS_WIN_POS_2B 0x68A70
#define _PS_WIN_POS_1C 0x69170
+#define PS_WIN_XPOS_MASK REG_GENMASK(28, 16)
+#define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x))
+#define PS_WIN_YPOS_MASK REG_GENMASK(12, 0)
+#define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y))
#define _PS_WIN_SZ_1A 0x68174
#define _PS_WIN_SZ_2A 0x68274
#define _PS_WIN_SZ_1B 0x68974
#define _PS_WIN_SZ_2B 0x68A74
#define _PS_WIN_SZ_1C 0x69174
+#define PS_WIN_XSIZE_MASK REG_GENMASK(29, 16)
+#define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w))
+#define PS_WIN_YSIZE_MASK REG_GENMASK(12, 0)
+#define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h))
#define _PS_VSCALE_1A 0x68184
#define _PS_VSCALE_2A 0x68284
--
2.39.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH 13/15] drm/i915: Define bitmasks for sik+ scaler window pos/size
2023-04-18 17:55 ` [Intel-gfx] [PATCH 13/15] drm/i915: Define bitmasks for sik+ scaler window pos/size Ville Syrjala
@ 2023-04-19 15:41 ` Jani Nikula
0 siblings, 0 replies; 40+ messages in thread
From: Jani Nikula @ 2023-04-19 15:41 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Define and use the bitmasks for the x/y components
> of the skl+ scaler window pos/size registers.
This too should mention the change of mask size.
Typo in subject, *skl+
BR,
Jani.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_scaler.c | 14 ++++++++------
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> 2 files changed, 16 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index 4437d130293a..1e7c97243fcf 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -754,9 +754,9 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
> intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
> PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
> intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
> - x << 16 | y);
> + PS_WIN_XPOS(x) | PS_WIN_YPOS(y));
> intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
> - width << 16 | height);
> + PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height));
> }
>
> void
> @@ -816,9 +816,9 @@ skl_program_plane_scaler(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id),
> PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
> intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id),
> - (crtc_x << 16) | crtc_y);
> + PS_WIN_XPOS(crtc_x) | PS_WIN_YPOS(crtc_y));
> intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id),
> - (crtc_w << 16) | crtc_h);
> + PS_WIN_XSIZE(crtc_w) | PS_WIN_YSIZE(crtc_h));
> }
>
> static void skl_detach_scaler(struct intel_crtc *crtc, int id)
> @@ -880,8 +880,10 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
> size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
>
> drm_rect_init(&crtc_state->pch_pfit.dst,
> - pos >> 16, pos & 0xffff,
> - size >> 16, size & 0xffff);
> + REG_FIELD_GET(PS_WIN_XPOS_MASK, pos),
> + REG_FIELD_GET(PS_WIN_YPOS_MASK, pos),
> + REG_FIELD_GET(PS_WIN_XSIZE_MASK, size),
> + REG_FIELD_GET(PS_WIN_YSIZE_MASK, size));
>
> scaler_state->scalers[i].in_use = true;
> break;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a5ae291de55b..68581864fb44 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4101,12 +4101,20 @@
> #define _PS_WIN_POS_1B 0x68970
> #define _PS_WIN_POS_2B 0x68A70
> #define _PS_WIN_POS_1C 0x69170
> +#define PS_WIN_XPOS_MASK REG_GENMASK(28, 16)
> +#define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x))
> +#define PS_WIN_YPOS_MASK REG_GENMASK(12, 0)
> +#define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y))
>
> #define _PS_WIN_SZ_1A 0x68174
> #define _PS_WIN_SZ_2A 0x68274
> #define _PS_WIN_SZ_1B 0x68974
> #define _PS_WIN_SZ_2B 0x68A74
> #define _PS_WIN_SZ_1C 0x69174
> +#define PS_WIN_XSIZE_MASK REG_GENMASK(29, 16)
> +#define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w))
> +#define PS_WIN_YSIZE_MASK REG_GENMASK(12, 0)
> +#define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h))
>
> #define _PS_VSCALE_1A 0x68184
> #define _PS_VSCALE_2A 0x68284
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH 14/15] drm/i915: Use REG_BIT() & co. for pipe scaler registers
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
` (12 preceding siblings ...)
2023-04-18 17:55 ` [Intel-gfx] [PATCH 13/15] drm/i915: Define bitmasks for sik+ scaler window pos/size Ville Syrjala
@ 2023-04-18 17:55 ` Ville Syrjala
2023-04-19 15:48 ` Jani Nikula
2023-04-18 17:55 ` [Intel-gfx] [PATCH 15/15] drm/i915: Define more PS_CTRL bits Ville Syrjala
` (5 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Ville Syrjala @ 2023-04-18 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pimp the skl+ scaler register bits with REG_BIT()/etc.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 98 ++++++++++++++++++---------------
1 file changed, 53 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 68581864fb44..9a6343d2e0fa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4049,52 +4049,58 @@
#define _PS_1B_CTRL 0x68980
#define _PS_2B_CTRL 0x68A80
#define _PS_1C_CTRL 0x69180
-#define PS_SCALER_EN (1 << 31)
-#define SKL_PS_SCALER_MODE_MASK (3 << 28)
-#define SKL_PS_SCALER_MODE_DYN (0 << 28)
-#define SKL_PS_SCALER_MODE_HQ (1 << 28)
-#define SKL_PS_SCALER_MODE_NV12 (2 << 28)
-#define PS_SCALER_MODE_PLANAR (1 << 29)
-#define PS_SCALER_MODE_NORMAL (0 << 29)
-#define PS_BINDING_MASK (7 << 25)
-#define PS_BINDING_PIPE (0 << 25)
-#define PS_BINDING_PLANE(plane_id) (((plane_id) + 1) << 25)
-#define PS_FILTER_MASK (3 << 23)
-#define PS_FILTER_MEDIUM (0 << 23)
-#define PS_FILTER_PROGRAMMED (1 << 23)
-#define PS_FILTER_EDGE_ENHANCE (2 << 23)
-#define PS_FILTER_BILINEAR (3 << 23)
-#define PS_VERT3TAP (1 << 21)
-#define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
-#define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
-#define PS_PWRUP_PROGRESS (1 << 17)
-#define PS_V_FILTER_BYPASS (1 << 8)
-#define PS_VADAPT_EN (1 << 7)
-#define PS_VADAPT_MODE_MASK (3 << 5)
-#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
-#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
-#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
-#define PS_BINDING_Y_MASK (7 << 5)
-#define PS_BINDING_Y_PLANE(plane_id) (((plane_id) + 1) << 5)
-#define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4)
-#define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3)
-#define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2)
-#define PS_UV_HORZ_FILTER_SELECT(set) ((set) << 1)
+#define PS_SCALER_EN REG_BIT(31)
+#define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */
+#define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
+#define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)
+#define SKL_PS_SCALER_MODE_NV12 REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2)
+#define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
+#define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
+#define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)
+#define PS_BINDING_MASK REG_GENMASK(27, 25)
+#define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0)
+#define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)
+#define PS_FILTER_MASK REG_GENMASK(24, 23)
+#define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0)
+#define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1)
+#define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2)
+#define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3)
+#define PS_VERT3TAP REG_BIT(21) /* skl/bxt */
+#define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
+#define PS_PWRUP_PROGRESS REG_BIT(17)
+#define PS_V_FILTER_BYPASS REG_BIT(8)
+#define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */
+#define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */
+#define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0)
+#define PS_VADAPT_MODE_MOD_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1)
+#define PS_VADAPT_MODE_MOST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3)
+#define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */
+#define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1)
+#define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */
+#define PS_Y_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set))
+#define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */
+#define PS_Y_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set))
+#define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */
+#define PS_UV_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set))
+#define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */
+#define PS_UV_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set))
#define _PS_PWR_GATE_1A 0x68160
#define _PS_PWR_GATE_2A 0x68260
#define _PS_PWR_GATE_1B 0x68960
#define _PS_PWR_GATE_2B 0x68A60
#define _PS_PWR_GATE_1C 0x69160
-#define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
-#define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
-#define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
-#define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
-#define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
-#define PS_PWR_GATE_SLPEN_8 0
-#define PS_PWR_GATE_SLPEN_16 1
-#define PS_PWR_GATE_SLPEN_24 2
-#define PS_PWR_GATE_SLPEN_32 3
+#define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31)
+#define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3)
+#define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0)
+#define PS_PWR_GATE_SETTLING_TIME_64 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1)
+#define PS_PWR_GATE_SETTLING_TIME_96 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2)
+#define PS_PWR_GATE_SETTLING_TIME_128 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3)
+#define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0)
+#define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0)
+#define PS_PWR_GATE_SLPEN_16 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1)
+#define PS_PWR_GATE_SLPEN_24 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2)
+#define PS_PWR_GATE_SLPEN_32 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3)
#define _PS_WIN_POS_1A 0x68170
#define _PS_WIN_POS_2A 0x68270
@@ -4133,10 +4139,12 @@
#define _PS_VPHASE_1B 0x68988
#define _PS_VPHASE_2B 0x68A88
#define _PS_VPHASE_1C 0x69188
-#define PS_Y_PHASE(x) ((x) << 16)
-#define PS_UV_RGB_PHASE(x) ((x) << 0)
-#define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
-#define PS_PHASE_TRIP (1 << 0)
+#define PS_Y_PHASE_MASK REG_GENMASK(31, 16)
+#define PS_Y_PHASE(x) REG_FIELD_PREP(PS_Y_PHASE_MASK, (x))
+#define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0)
+#define PS_UV_RGB_PHASE(x) REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x))
+#define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
+#define PS_PHASE_TRIP (1 << 0)
#define _PS_HPHASE_1A 0x68194
#define _PS_HPHASE_2A 0x68294
@@ -4154,7 +4162,7 @@
#define _PS_COEF_SET0_INDEX_2A 0x68298
#define _PS_COEF_SET0_INDEX_1B 0x68998
#define _PS_COEF_SET0_INDEX_2B 0x68A98
-#define PS_COEF_INDEX_AUTO_INC (1 << 10)
+#define PS_COEF_INDEX_AUTO_INC REG_BIT(10)
#define _PS_COEF_SET0_DATA_1A 0x6819C
#define _PS_COEF_SET0_DATA_2A 0x6829C
--
2.39.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH 14/15] drm/i915: Use REG_BIT() & co. for pipe scaler registers
2023-04-18 17:55 ` [Intel-gfx] [PATCH 14/15] drm/i915: Use REG_BIT() & co. for pipe scaler registers Ville Syrjala
@ 2023-04-19 15:48 ` Jani Nikula
0 siblings, 0 replies; 40+ messages in thread
From: Jani Nikula @ 2023-04-19 15:48 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 18 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pimp the skl+ scaler register bits with REG_BIT()/etc.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 98 ++++++++++++++++++---------------
> 1 file changed, 53 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 68581864fb44..9a6343d2e0fa 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4049,52 +4049,58 @@
> #define _PS_1B_CTRL 0x68980
> #define _PS_2B_CTRL 0x68A80
> #define _PS_1C_CTRL 0x69180
> -#define PS_SCALER_EN (1 << 31)
> -#define SKL_PS_SCALER_MODE_MASK (3 << 28)
> -#define SKL_PS_SCALER_MODE_DYN (0 << 28)
> -#define SKL_PS_SCALER_MODE_HQ (1 << 28)
> -#define SKL_PS_SCALER_MODE_NV12 (2 << 28)
> -#define PS_SCALER_MODE_PLANAR (1 << 29)
> -#define PS_SCALER_MODE_NORMAL (0 << 29)
> -#define PS_BINDING_MASK (7 << 25)
> -#define PS_BINDING_PIPE (0 << 25)
> -#define PS_BINDING_PLANE(plane_id) (((plane_id) + 1) << 25)
> -#define PS_FILTER_MASK (3 << 23)
> -#define PS_FILTER_MEDIUM (0 << 23)
> -#define PS_FILTER_PROGRAMMED (1 << 23)
> -#define PS_FILTER_EDGE_ENHANCE (2 << 23)
> -#define PS_FILTER_BILINEAR (3 << 23)
> -#define PS_VERT3TAP (1 << 21)
> -#define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
> -#define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
> -#define PS_PWRUP_PROGRESS (1 << 17)
> -#define PS_V_FILTER_BYPASS (1 << 8)
> -#define PS_VADAPT_EN (1 << 7)
> -#define PS_VADAPT_MODE_MASK (3 << 5)
> -#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
> -#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
> -#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
> -#define PS_BINDING_Y_MASK (7 << 5)
> -#define PS_BINDING_Y_PLANE(plane_id) (((plane_id) + 1) << 5)
> -#define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4)
> -#define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3)
> -#define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2)
> -#define PS_UV_HORZ_FILTER_SELECT(set) ((set) << 1)
> +#define PS_SCALER_EN REG_BIT(31)
> +#define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */
> +#define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
> +#define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)
> +#define SKL_PS_SCALER_MODE_NV12 REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2)
> +#define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
> +#define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
> +#define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)
> +#define PS_BINDING_MASK REG_GENMASK(27, 25)
> +#define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0)
> +#define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)
> +#define PS_FILTER_MASK REG_GENMASK(24, 23)
> +#define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0)
> +#define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1)
> +#define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2)
> +#define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3)
> +#define PS_VERT3TAP REG_BIT(21) /* skl/bxt */
> +#define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
> +#define PS_PWRUP_PROGRESS REG_BIT(17)
> +#define PS_V_FILTER_BYPASS REG_BIT(8)
> +#define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */
> +#define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */
> +#define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0)
> +#define PS_VADAPT_MODE_MOD_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1)
> +#define PS_VADAPT_MODE_MOST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3)
> +#define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */
> +#define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1)
> +#define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */
> +#define PS_Y_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set))
> +#define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */
> +#define PS_Y_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set))
> +#define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */
> +#define PS_UV_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set))
> +#define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */
> +#define PS_UV_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set))
>
> #define _PS_PWR_GATE_1A 0x68160
> #define _PS_PWR_GATE_2A 0x68260
> #define _PS_PWR_GATE_1B 0x68960
> #define _PS_PWR_GATE_2B 0x68A60
> #define _PS_PWR_GATE_1C 0x69160
> -#define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
> -#define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
> -#define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
> -#define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
> -#define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
> -#define PS_PWR_GATE_SLPEN_8 0
> -#define PS_PWR_GATE_SLPEN_16 1
> -#define PS_PWR_GATE_SLPEN_24 2
> -#define PS_PWR_GATE_SLPEN_32 3
> +#define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31)
> +#define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3)
> +#define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0)
> +#define PS_PWR_GATE_SETTLING_TIME_64 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1)
> +#define PS_PWR_GATE_SETTLING_TIME_96 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2)
> +#define PS_PWR_GATE_SETTLING_TIME_128 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3)
> +#define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0)
> +#define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0)
> +#define PS_PWR_GATE_SLPEN_16 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1)
> +#define PS_PWR_GATE_SLPEN_24 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2)
> +#define PS_PWR_GATE_SLPEN_32 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3)
>
> #define _PS_WIN_POS_1A 0x68170
> #define _PS_WIN_POS_2A 0x68270
> @@ -4133,10 +4139,12 @@
> #define _PS_VPHASE_1B 0x68988
> #define _PS_VPHASE_2B 0x68A88
> #define _PS_VPHASE_1C 0x69188
> -#define PS_Y_PHASE(x) ((x) << 16)
> -#define PS_UV_RGB_PHASE(x) ((x) << 0)
> -#define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
> -#define PS_PHASE_TRIP (1 << 0)
> +#define PS_Y_PHASE_MASK REG_GENMASK(31, 16)
> +#define PS_Y_PHASE(x) REG_FIELD_PREP(PS_Y_PHASE_MASK, (x))
> +#define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0)
> +#define PS_UV_RGB_PHASE(x) REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x))
> +#define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
> +#define PS_PHASE_TRIP (1 << 0)
>
> #define _PS_HPHASE_1A 0x68194
> #define _PS_HPHASE_2A 0x68294
> @@ -4154,7 +4162,7 @@
> #define _PS_COEF_SET0_INDEX_2A 0x68298
> #define _PS_COEF_SET0_INDEX_1B 0x68998
> #define _PS_COEF_SET0_INDEX_2B 0x68A98
> -#define PS_COEF_INDEX_AUTO_INC (1 << 10)
> +#define PS_COEF_INDEX_AUTO_INC REG_BIT(10)
>
> #define _PS_COEF_SET0_DATA_1A 0x6819C
> #define _PS_COEF_SET0_DATA_2A 0x6829C
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH 15/15] drm/i915: Define more PS_CTRL bits
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
` (13 preceding siblings ...)
2023-04-18 17:55 ` [Intel-gfx] [PATCH 14/15] drm/i915: Use REG_BIT() & co. for pipe scaler registers Ville Syrjala
@ 2023-04-18 17:55 ` Ville Syrjala
2023-04-18 18:31 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Scaler/pfit stuff Patchwork
` (4 subsequent siblings)
19 siblings, 0 replies; 40+ messages in thread
From: Ville Syrjala @ 2023-04-18 17:55 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
To avoid annoying spec lookups let's define more PS_CTRL
bits in the header.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9a6343d2e0fa..5baaf6df6951 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4050,6 +4050,9 @@
#define _PS_2B_CTRL 0x68A80
#define _PS_1C_CTRL 0x69180
#define PS_SCALER_EN REG_BIT(31)
+#define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */
+#define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
+#define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1)
#define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */
#define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
#define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)
@@ -4057,6 +4060,7 @@
#define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
#define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
#define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)
+#define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */
#define PS_BINDING_MASK REG_GENMASK(27, 25)
#define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0)
#define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)
@@ -4065,8 +4069,15 @@
#define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1)
#define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2)
#define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3)
+#define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */
+#define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)
+#define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1)
+#define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */
+#define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */
+#define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */
#define PS_VERT3TAP REG_BIT(21) /* skl/bxt */
#define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
+#define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
#define PS_PWRUP_PROGRESS REG_BIT(17)
#define PS_V_FILTER_BYPASS REG_BIT(8)
#define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */
--
2.39.2
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Scaler/pfit stuff
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
` (14 preceding siblings ...)
2023-04-18 17:55 ` [Intel-gfx] [PATCH 15/15] drm/i915: Define more PS_CTRL bits Ville Syrjala
@ 2023-04-18 18:31 ` Patchwork
2023-04-18 22:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Scaler/pfit stuff (rev2) Patchwork
` (3 subsequent siblings)
19 siblings, 0 replies; 40+ messages in thread
From: Patchwork @ 2023-04-18 18:31 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Scaler/pfit stuff
URL : https://patchwork.freedesktop.org/series/116661/
State : failure
== Summary ==
Error: make failed
CALL scripts/checksyscalls.sh
DESCEND objtool
INSTALL libsubcmd_headers
LD [M] drivers/gpu/drm/i915/i915.o
CC [M] drivers/gpu/drm/i915/gvt/handlers.o
drivers/gpu/drm/i915/gvt/handlers.c: In function ‘pf_write’:
drivers/gpu/drm/i915/gvt/handlers.c:1565:38: error: ‘PS_PLANE_SEL_MASK’ undeclared (first use in this function); did you mean ‘PS_PHASE_MASK’?
1565 | offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
| ^~~~~~~~~~~~~~~~~
| PS_PHASE_MASK
drivers/gpu/drm/i915/gvt/handlers.c:1565:38: note: each undeclared identifier is reported only once for each function it appears in
make[5]: *** [scripts/Makefile.build:252: drivers/gpu/drm/i915/gvt/handlers.o] Error 1
make[4]: *** [scripts/Makefile.build:494: drivers/gpu/drm/i915] Error 2
make[3]: *** [scripts/Makefile.build:494: drivers/gpu/drm] Error 2
make[2]: *** [scripts/Makefile.build:494: drivers/gpu] Error 2
make[1]: *** [scripts/Makefile.build:494: drivers] Error 2
make: *** [Makefile:2025: .] Error 2
Build failed, no error log produced
^ permalink raw reply [flat|nested] 40+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Scaler/pfit stuff (rev2)
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
` (15 preceding siblings ...)
2023-04-18 18:31 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Scaler/pfit stuff Patchwork
@ 2023-04-18 22:20 ` Patchwork
2023-04-18 22:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
19 siblings, 0 replies; 40+ messages in thread
From: Patchwork @ 2023-04-18 22:20 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Scaler/pfit stuff (rev2)
URL : https://patchwork.freedesktop.org/series/116661/
State : warning
== Summary ==
Error: dim checkpatch failed
96742f02457a drm/i915: Check pipe source size when using skl+ scalers
-:19: WARNING:COMMIT_LOG_USE_LINK: Unknown link reference 'Closes:', use 'Link:' instead
#19:
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8357
total: 0 errors, 1 warnings, 0 checks, 29 lines checked
020b73ecaea1 drm/i915: Relocate VBLANK_EVASION_TIME_US
985d1c61ab4b drm/i915: Relocate intel_atomic_setup_scalers()
d8119d553652 drm/i915: Relocate skl_get_pfit_config()
abb5209c730e drm/i915: Use REG_BIT() & co for the pre-ilk pfit registers
e661ff574bbc drm/i915: Namespace pfit registers properly
5f7ed896b1db drm/i915: Use REG_BIT() & co. for ilk+ pfit registers
8337eb734cde drm/i915: Drop a useless forward declararion
152fabebf7a4 drm/i915: Define bitmasks for ilk pfit window pos/size
afe2b9bb87f3 drm/i915: Remove dead scaler register defines
500da878f1fb drm/i915: Rename skl+ scaler binding bits
c4690f428705 drm/i915: s/PS_COEE_INDEX_AUTO_INC/PS_COEF_INDEX_AUTO_INC/
73ea67a05509 drm/i915: Define bitmasks for sik+ scaler window pos/size
dcfed7ebc951 drm/i915: Use REG_BIT() & co. for pipe scaler registers
f9431f7d6815 drm/i915: Define more PS_CTRL bits
-:44: WARNING:LONG_LINE_COMMENT: line length of 107 exceeds 100 columns
#44: FILE: drivers/gpu/drm/i915/i915_reg.h:4076:
+#define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */
-:45: WARNING:LONG_LINE_COMMENT: line length of 103 exceeds 100 columns
#45: FILE: drivers/gpu/drm/i915/i915_reg.h:4077:
+#define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */
total: 0 errors, 2 warnings, 0 checks, 31 lines checked
^ permalink raw reply [flat|nested] 40+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Scaler/pfit stuff (rev2)
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
` (16 preceding siblings ...)
2023-04-18 22:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Scaler/pfit stuff (rev2) Patchwork
@ 2023-04-18 22:20 ` Patchwork
2023-04-18 22:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-04-19 4:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
19 siblings, 0 replies; 40+ messages in thread
From: Patchwork @ 2023-04-18 22:20 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Scaler/pfit stuff (rev2)
URL : https://patchwork.freedesktop.org/series/116661/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return'
^ permalink raw reply [flat|nested] 40+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Scaler/pfit stuff (rev2)
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
` (17 preceding siblings ...)
2023-04-18 22:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-04-18 22:30 ` Patchwork
2023-04-19 4:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
19 siblings, 0 replies; 40+ messages in thread
From: Patchwork @ 2023-04-18 22:30 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4799 bytes --]
== Series Details ==
Series: drm/i915: Scaler/pfit stuff (rev2)
URL : https://patchwork.freedesktop.org/series/116661/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13027 -> Patchwork_116661v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/index.html
Participating hosts (37 -> 36)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_116661v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [PASS][1] -> [DMESG-WARN][2] ([i915#7699])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/bat-dg2-11/igt@i915_selftest@live@migrate.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/bat-dg2-11/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: NOTRUN -> [ABORT][3] ([i915#4983])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/bat-rpls-1/igt@i915_selftest@live@reset.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- fi-glk-j4005: NOTRUN -> [SKIP][4] ([fdo#109271])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/fi-glk-j4005/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
#### Possible fixes ####
* igt@dmabuf@all-tests@dma_fence:
- fi-glk-j4005: [ABORT][5] -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/fi-glk-j4005/igt@dmabuf@all-tests@dma_fence.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/fi-glk-j4005/igt@dmabuf@all-tests@dma_fence.html
* igt@dmabuf@all-tests@dma_fence_chain:
- fi-glk-j4005: [DMESG-FAIL][7] -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/fi-glk-j4005/igt@dmabuf@all-tests@dma_fence_chain.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/fi-glk-j4005/igt@dmabuf@all-tests@dma_fence_chain.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [ABORT][9] ([i915#7911] / [i915#7982]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/bat-rpls-1/igt@i915_selftest@live@requests.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/bat-rpls-1/igt@i915_selftest@live@requests.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [FAIL][11] ([i915#7932]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982
Build changes
-------------
* Linux: CI_DRM_13027 -> Patchwork_116661v2
CI-20190529: 20190529
CI_DRM_13027: 9e1eb302fc69b5d8dc662f1ce7ed8684e87c5751 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7259: 3d3a7f1c041d3f8d84d7457abf96adef0ea071cb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116661v2: 9e1eb302fc69b5d8dc662f1ce7ed8684e87c5751 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
9947c69ee924 drm/i915: Define more PS_CTRL bits
0ac6b744524a drm/i915: Use REG_BIT() & co. for pipe scaler registers
6b67a6cd9f21 drm/i915: Define bitmasks for sik+ scaler window pos/size
687ad0dac35d drm/i915: s/PS_COEE_INDEX_AUTO_INC/PS_COEF_INDEX_AUTO_INC/
89444185a560 drm/i915: Rename skl+ scaler binding bits
b3faccaba258 drm/i915: Remove dead scaler register defines
c373ba56babd drm/i915: Define bitmasks for ilk pfit window pos/size
3e421cff5a5c drm/i915: Drop a useless forward declararion
5852fb441ef9 drm/i915: Use REG_BIT() & co. for ilk+ pfit registers
4d524b27d865 drm/i915: Namespace pfit registers properly
58c021cd2807 drm/i915: Use REG_BIT() & co for the pre-ilk pfit registers
507b0444a95c drm/i915: Relocate skl_get_pfit_config()
08731b676724 drm/i915: Relocate intel_atomic_setup_scalers()
1a7334d25793 drm/i915: Relocate VBLANK_EVASION_TIME_US
f77bf272f7b9 drm/i915: Check pipe source size when using skl+ scalers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/index.html
[-- Attachment #2: Type: text/html, Size: 5673 bytes --]
^ permalink raw reply [flat|nested] 40+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Scaler/pfit stuff (rev2)
2023-04-18 17:55 [Intel-gfx] [PATCH 00/15] drm/i915: Scaler/pfit stuff Ville Syrjala
` (18 preceding siblings ...)
2023-04-18 22:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-04-19 4:12 ` Patchwork
19 siblings, 0 replies; 40+ messages in thread
From: Patchwork @ 2023-04-19 4:12 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 17287 bytes --]
== Series Details ==
Series: drm/i915: Scaler/pfit stuff (rev2)
URL : https://patchwork.freedesktop.org/series/116661/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13027_full -> Patchwork_116661v2_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (8 -> 8)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_116661v2_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_ccs@pipe-h-bad-aux-stride-yf_tiled_ccs:
- {shard-dg1}: NOTRUN -> [SKIP][1] +25 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-dg1-18/igt@kms_ccs@pipe-h-bad-aux-stride-yf_tiled_ccs.html
Known issues
------------
Here are the changes found in Patchwork_116661v2_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-snb: ([PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) -> ([PASS][27], [PASS][28], [PASS][29], [FAIL][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51]) ([i915#4338])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb1/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb1/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb1/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb1/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb2/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb2/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb7/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb6/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb6/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb7/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb7/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb2/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb2/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb2/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb4/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb4/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb4/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb4/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb5/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb5/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb5/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb5/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb6/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb6/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-snb6/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb7/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb7/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb7/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb6/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb6/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb6/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb6/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb5/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb5/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb5/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb5/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb5/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb4/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb4/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb4/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb4/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb2/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb2/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb2/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb2/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb2/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb1/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb1/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb1/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb1/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_barrier_race@remote-request@rcs0:
- shard-glk: [PASS][52] -> [ABORT][53] ([i915#8211])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-glk1/igt@gem_barrier_race@remote-request@rcs0.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-glk2/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [PASS][54] -> [FAIL][55] ([i915#2842])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-glk5/igt@gem_exec_fair@basic-none-share@rcs0.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-glk9/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][56] -> [FAIL][57] ([i915#2842])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [PASS][58] -> [DMESG-FAIL][59] ([i915#5334])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-apl4/igt@i915_selftest@live@gt_heartbeat.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-apl1/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-apl: NOTRUN -> [SKIP][60] ([fdo#109271]) +6 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-apl6/igt@kms_flip@2x-plain-flip-fb-recreate.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][61] ([fdo#109271]) +46 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-snb6/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-vga-1.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [FAIL][62] ([i915#2842]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-glk6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-glk7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- {shard-rkl}: [FAIL][64] ([i915#2842]) -> [PASS][65] +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-rkl-7/igt@gem_exec_fair@basic-pace@rcs0.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-rkl-3/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@i915_pm_rc6_residency@rc6-idle@vecs0:
- {shard-dg1}: [FAIL][66] ([i915#3591]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- {shard-dg1}: [SKIP][68] ([i915#1397]) -> [PASS][69] +3 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-dg1-18/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-dg1-14/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- {shard-rkl}: [SKIP][70] ([i915#1397]) -> [PASS][71] +2 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-rkl-7/igt@i915_pm_rpm@dpms-non-lpsp.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-rkl-3/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@i915_suspend@forcewake:
- shard-apl: [ABORT][72] ([i915#180]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-apl6/igt@i915_suspend@forcewake.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-apl6/igt@i915_suspend@forcewake.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [FAIL][74] ([i915#2346]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@forked-bo@pipe-b:
- {shard-dg1}: [INCOMPLETE][76] ([i915#8011] / [i915#8347]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-dg1-14/igt@kms_cursor_legacy@forked-bo@pipe-b.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-dg1-17/igt@kms_cursor_legacy@forked-bo@pipe-b.html
* igt@kms_cursor_legacy@single-bo@pipe-b:
- {shard-rkl}: [INCOMPLETE][78] ([i915#8011]) -> [PASS][79] +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13027/shard-rkl-7/igt@kms_cursor_legacy@single-bo@pipe-b.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/shard-rkl-1/igt@kms_cursor_legacy@single-bo@pipe-b.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4338]: https://gitlab.freedesktop.org/drm/intel/issues/4338
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
Build changes
-------------
* Linux: CI_DRM_13027 -> Patchwork_116661v2
CI-20190529: 20190529
CI_DRM_13027: 9e1eb302fc69b5d8dc662f1ce7ed8684e87c5751 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7259: 3d3a7f1c041d3f8d84d7457abf96adef0ea071cb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116661v2: 9e1eb302fc69b5d8dc662f1ce7ed8684e87c5751 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v2/index.html
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