[PATCH v2 00/22] drm/xe: Add Xe3p support

[PATCH v2 00/22] drm/xe: Add Xe3p support

[Lucas De Marchi]

This begins the support for the Xe3p arch - it contains generic support
for graphics version 35 and the Xe3p_xpc IP, the Xe3p_LPM IP for media
and support for Nova Lake S (NVL-S), that uses a mix of IPs - the
display side for NVL-S will be submitted separately.

Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
Changes in v2:
- Rebase on latest drm-tip as some interfaces changed like the device
  flags location and RTP helper signature
- Drop patches to handle app transient and additional flushes as they
  are not currently used
- Drop patches to handle main gam control - they are actually correct,
  but having a spec reference to embed in the commit message is
  preferred
- Add 2 patches to refactor irq enabling on hw engines so we don blindly
  set bits intended for one engine class in another.
- Some other changes, mentioned in the individual commits
- Link to v1: https://lore.kernel.org/r/20251013-xe3p-v1-0-bfb74f038215@intel.com
---
Balasubramani Vivekanandan (3):
      drm/xe: Drop CTC_MODE register read
      drm/xe/xe3p_lpm: Skip disabling NOA on unsupported IPs
      drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition

Dnyaneshwar Bhadane (1):
      drm/xe/nvls: Attach MOCS table for NVL-S

Fei Yang (1):
      drm/xe/xe3p_xpc: Add L3 bank mask

Harish Chegondi (1):
      drm/xe/xe3p: Add xe3p EU stall data format

Lucas De Marchi (4):
      drm/xe: Add GT_VER() to check version specific to gt type
      drm/xe/irq: Rename fuse mask variables
      drm/xe/irq: Split irq mask per engine class
      drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx

Matt Roper (8):
      drm/xe/xe3p_lpm: Handle MCR steering
      drm/xe/xe3p: Stop programming RCU_MODE's fixed slice mode setting
      drm/xe/xe3p: Determine service copy availability from fuse
      drm/xe/nvl: Define NVL-S platform
      drm/xe/nvls: Define GuC firmware for NVL-S
      drm/xe/xe3p_xpc: Add MCR steering
      drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs
      drm/xe/xe3p_xpc: Setup PAT table

Shekhar Chauhan (2):
      drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05
      drm/xe/xe3p_lpm: Add support for media IP versions 35.00 & 35.03

Wang Xin (2):
      drm/xe: Dump CURRENT_LRCA register
      drm/xe/xe3p: Dump CSMQDEBUG register

 drivers/gpu/drm/xe/regs/xe_engine_regs.h |   5 ++
 drivers/gpu/drm/xe/regs/xe_gt_regs.h     |   7 +-
 drivers/gpu/drm/xe/regs/xe_irq_regs.h    |   1 +
 drivers/gpu/drm/xe/xe_eu_stall.c         |  28 +++++++-
 drivers/gpu/drm/xe/xe_gt.h               |   6 ++
 drivers/gpu/drm/xe/xe_gt_clock.c         |  19 ------
 drivers/gpu/drm/xe/xe_gt_mcr.c           |  61 +++++++++++++++--
 drivers/gpu/drm/xe/xe_gt_topology.c      |   6 +-
 drivers/gpu/drm/xe/xe_gt_types.h         |  15 +++++
 drivers/gpu/drm/xe/xe_guc_capture.c      |  49 +++++++++++++-
 drivers/gpu/drm/xe/xe_hw_engine.c        |  50 +++++++++++---
 drivers/gpu/drm/xe/xe_irq.c              | 109 ++++++++++++++++++++-----------
 drivers/gpu/drm/xe/xe_mocs.c             |   1 +
 drivers/gpu/drm/xe/xe_oa.c               |   3 +-
 drivers/gpu/drm/xe/xe_pat.c              |  96 ++++++++++++++++++++++++++-
 drivers/gpu/drm/xe/xe_pci.c              |  21 ++++++
 drivers/gpu/drm/xe/xe_platform_types.h   |   1 +
 drivers/gpu/drm/xe/xe_rtp.c              |   7 ++
 drivers/gpu/drm/xe/xe_rtp.h              |  12 ++++
 drivers/gpu/drm/xe/xe_tuning.c           |   9 ++-
 drivers/gpu/drm/xe/xe_uc_fw.c            |   1 +
 drivers/gpu/drm/xe/xe_wa.c               |   6 +-
 drivers/gpu/drm/xe/xe_wa_oob.rules       |   9 +--
 include/drm/intel/pciids.h               |   9 +++
 24 files changed, 441 insertions(+), 90 deletions(-)

base-commit: f019aaad58112f89234f7b68557c831846437008
change-id: 20251013-xe3p-81bb749e9de0

Lucas De Marchi

[PATCH v2 01/22] drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05

[Lucas De Marchi]

From: Shekhar Chauhan <shekhar.chauhan@intel.com>

Add graphics IP versions 30.04 & 30.05 and initial workarounds for these
IP versions.

BSpec: 74201
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2: Merge graphics range together (Shekhar, Matt Roper)
---
 drivers/gpu/drm/xe/xe_pci.c        | 2 ++
 drivers/gpu/drm/xe/xe_wa.c         | 6 +++---
 drivers/gpu/drm/xe/xe_wa_oob.rules | 9 +++++----
 3 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 24a38904bb508..3ea8ccfcbca55 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -136,6 +136,8 @@ static const struct xe_ip graphics_ips[] = {
 	{ 3000, "Xe3_LPG", &graphics_xe2 },
 	{ 3001, "Xe3_LPG", &graphics_xe2 },
 	{ 3003, "Xe3_LPG", &graphics_xe2 },
+	{ 3004, "Xe3_LPG", &graphics_xe2 },
+	{ 3005, "Xe3_LPG", &graphics_xe2 },
 };
 
 /* Pre-GMDID Media IPs */
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index aa1b69f48f6f9..b6dcd9827354d 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -684,7 +684,7 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 	},
 	{ XE_RTP_NAME("13012615864"),
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), OR,
-		       GRAPHICS_VERSION(3003),
+		       GRAPHICS_VERSION_RANGE(3003, 3005),
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
 	},
@@ -695,7 +695,7 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
 	},
 	{ XE_RTP_NAME("14021402888"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(3003), FUNC(xe_rtp_match_first_render_or_compute)),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3003, 3005), FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
 	},
 	{ XE_RTP_NAME("18041344222"),
@@ -913,7 +913,7 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 			     DIS_AUTOSTRIP))
 	},
 	{ XE_RTP_NAME("22021007897"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3003), ENGINE_CLASS(RENDER)),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
 	},
 };
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 4bb94e5799ed6..fb38eb3d6e9a3 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -33,14 +33,15 @@
 13011645652	GRAPHICS_VERSION(2004)
 		GRAPHICS_VERSION_RANGE(3000, 3001)
 		GRAPHICS_VERSION(3003)
+		GRAPHICS_VERSION_RANGE(3004, 3005)
 14022293748	GRAPHICS_VERSION_RANGE(2001, 2002)
 		GRAPHICS_VERSION(2004)
-		GRAPHICS_VERSION_RANGE(3000, 3001)
-		GRAPHICS_VERSION(3003)
+		GRAPHICS_VERSION_RANGE(3000, 3005)
 22019794406	GRAPHICS_VERSION_RANGE(2001, 2002)
 		GRAPHICS_VERSION(2004)
 		GRAPHICS_VERSION_RANGE(3000, 3001)
 		GRAPHICS_VERSION(3003)
+		GRAPHICS_VERSION_RANGE(3004, 3005)
 22019338487	MEDIA_VERSION(2000)
 		GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_not_sriov_vf)
 		MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), FUNC(xe_rtp_match_not_sriov_vf)
@@ -61,11 +62,11 @@
 16023105232	GRAPHICS_VERSION_RANGE(2001, 3001)
 		MEDIA_VERSION_RANGE(1301, 3000)
 		MEDIA_VERSION(3002)
-		GRAPHICS_VERSION(3003)
+		GRAPHICS_VERSION_RANGE(3003, 3005)
 16026508708	GRAPHICS_VERSION_RANGE(1200, 3001)
 		MEDIA_VERSION_RANGE(1300, 3000)
 		MEDIA_VERSION(3002)
-		GRAPHICS_VERSION(3003)
+		GRAPHICS_VERSION_RANGE(3003, 3005)
 14020001231	GRAPHICS_VERSION_RANGE(2001,2004), FUNC(xe_rtp_match_psmi_enabled)
 		MEDIA_VERSION(2000), FUNC(xe_rtp_match_psmi_enabled)
 		MEDIA_VERSION(3000), FUNC(xe_rtp_match_psmi_enabled)

-- 
2.51.0

[PATCH v2 02/22] drm/xe/xe3p_lpm: Add support for media IP versions 35.00 & 35.03

[Lucas De Marchi]

From: Shekhar Chauhan <shekhar.chauhan@intel.com>

Xe3p_LPM is very similar to Xe3_LPM on the kmd interface, so it can use
the same descriptor structure. Add both 35.00 and 35.03 IP versions.

BSpec: 74201, 74202, 77977, 77979
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 3ea8ccfcbca55..b72f71b0f52c9 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -151,6 +151,8 @@ static const struct xe_ip media_ips[] = {
 	{ 2000, "Xe2_LPM", &media_xelpmp },
 	{ 3000, "Xe3_LPM", &media_xelpmp },
 	{ 3002, "Xe3_LPM", &media_xelpmp },
+	{ 3500, "Xe3p_LPM", &media_xelpmp },
+	{ 3503, "Xe3p_LPM", &media_xelpmp },
 };
 
 static const struct xe_device_desc tgl_desc = {

-- 
2.51.0

[PATCH v2 03/22] drm/xe: Drop CTC_MODE register read

[Lucas De Marchi]

From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

The warning was added for a condition that never triggered even for
platforms prior to Xe2. It's not supported in Xe2 and in Xe3p the
register is removed from the main GT. Just drop the entire function as
it doesn't bring any benefit.

Bspec: 62395
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
[ Drop the entire check for CTC_MODE ]
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_regs.h |  4 ----
 drivers/gpu/drm/xe/xe_gt_clock.c     | 19 -------------------
 2 files changed, 23 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 51f2a03847f9d..21c15441c4537 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -346,10 +346,6 @@
 #define   VDN_HCP_POWERGATE_ENABLE(n)		REG_BIT(3 + 2 * (n))
 #define   VDN_MFXVDENC_POWERGATE_ENABLE(n)	REG_BIT(4 + 2 * (n))
 
-#define CTC_MODE				XE_REG(0xa26c)
-#define   CTC_SHIFT_PARAMETER_MASK		REG_GENMASK(2, 1)
-#define   CTC_SOURCE_DIVIDE_LOGIC		REG_BIT(0)
-
 #define FORCEWAKE_RENDER			XE_REG(0xa278)
 
 #define POWERGATE_DOMAIN_STATUS			XE_REG(0xa2a0)
diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
index 4f011d1573c65..00f5972c14dc5 100644
--- a/drivers/gpu/drm/xe/xe_gt_clock.c
+++ b/drivers/gpu/drm/xe/xe_gt_clock.c
@@ -55,30 +55,11 @@ static void read_crystal_clock(struct xe_gt *gt, u32 rpm_config_reg, u32 *freq,
 	}
 }
 
-static void check_ctc_mode(struct xe_gt *gt)
-{
-	/*
-	 * CTC_MODE[0] = 1 is definitely not supported for Xe2 and later
-	 * platforms.  In theory it could be a valid setting for pre-Xe2
-	 * platforms, but there's no documentation on how to properly handle
-	 * this case.  Reading TIMESTAMP_OVERRIDE, as the driver attempted in
-	 * the past has been confirmed as incorrect by the hardware architects.
-	 *
-	 * For now just warn if we ever encounter hardware in the wild that
-	 * has this setting and move on as if it hadn't been set.
-	 */
-	if (xe_mmio_read32(&gt->mmio, CTC_MODE) & CTC_SOURCE_DIVIDE_LOGIC)
-		xe_gt_warn(gt, "CTC_MODE[0] is set; this is unexpected and undocumented\n");
-}
-
 int xe_gt_clock_init(struct xe_gt *gt)
 {
 	u32 freq;
 	u32 c0;
 
-	if (!IS_SRIOV_VF(gt_to_xe(gt)))
-		check_ctc_mode(gt);
-
 	c0 = xe_mmio_read32(&gt->mmio, RPM_CONFIG0);
 	read_crystal_clock(gt, c0, &freq, &gt->info.timestamp_base);
 

-- 
2.51.0

[PATCH v2 04/22] drm/xe: Add GT_VER() to check version specific to gt type

[Lucas De Marchi]

In some situations we will need to check the version of the specific gt
being passed as argument, not if the device has a certain graphics/media
version.

This is extracted from a patch by Balasubramani Vivekanandan that
may need some rework, but this helper is still useful for other enabling
parts of Xe3p.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_gt.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h
index 5df2ffe3ff838..9d710049da455 100644
--- a/drivers/gpu/drm/xe/xe_gt.h
+++ b/drivers/gpu/drm/xe/xe_gt.h
@@ -22,6 +22,12 @@
 
 #define CCS_MASK(gt) (((gt)->info.engine_mask & XE_HW_ENGINE_CCS_MASK) >> XE_HW_ENGINE_CCS0)
 
+#define GT_VER(gt) ({ \
+	typeof(gt) gt_ = (gt); \
+	struct xe_device *xe = gt_to_xe(gt_); \
+	xe_gt_is_media_type(gt_) ? MEDIA_VER(xe) : GRAPHICS_VER(xe); \
+})
+
 extern struct fault_attr gt_reset_failure;
 static inline bool xe_fault_inject_gt_reset(void)
 {

-- 
2.51.0

[PATCH v2 05/22] drm/xe/xe3p_lpm: Skip disabling NOA on unsupported IPs

[Lucas De Marchi]

From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

IP version 35 has removed "NOA Enable Signal" bit from RPM_CONFIG1
register. Skip clearing that bit on unsupported IPs.

Bspec: 62391
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_oa.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index a4894eb0d7f3f..f901ba52b4032 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -837,7 +837,8 @@ static void xe_oa_disable_metric_set(struct xe_oa_stream *stream)
 		xe_oa_configure_oa_context(stream, false);
 
 	/* Make sure we disable noa to save power. */
-	xe_mmio_rmw32(mmio, RPM_CONFIG1, GT_NOA_ENABLE, 0);
+	if (GT_VER(stream->gt) < 35)
+		xe_mmio_rmw32(mmio, RPM_CONFIG1, GT_NOA_ENABLE, 0);
 
 	sqcnt1 = SQCNT1_PMON_ENABLE |
 		 (HAS_OA_BPC_REPORTING(stream->oa->xe) ? SQCNT1_OABPC : 0);

-- 
2.51.0

[PATCH v2 06/22] drm/xe/xe3p_lpm: Handle MCR steering

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Xe3p_LPM's MCR steering has the same ranges and behavior as Xe3_LPM.
However one register range that was reserved on Xe3_LPM has now become a
unicast range (0x384200-0x38427F), so we need to stop consolidating the
adjacent MCR ranges into a single table entry in the table.  With this
change to the Xe3_LPM table, we can continue to use the same table for
both IP families.

While we're touching this table, take the opportunity to fix a
whitespace mistake and clarify that one of the other consolidated range
entries includes a reserved range.

Bspec: 76445
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_gt_mcr.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index 8fb1cae917244..e1a2b38fc2a86 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -236,12 +236,13 @@ static const struct xe_mmio_range xe2lpm_instance0_steering_table[] = {
 };
 
 static const struct xe_mmio_range xe3lpm_instance0_steering_table[] = {
-	{ 0x384000, 0x3847DF },         /* GAM, rsvd, GAM */
+	{ 0x384000, 0x3841FF },         /* GAM */
+	{ 0x384400, 0x3847DF },         /* GAM */
 	{ 0x384900, 0x384AFF },         /* GAM */
 	{ 0x389560, 0x3895FF },         /* MEDIAINF */
 	{ 0x38B600, 0x38B8FF },         /* L3BANK */
 	{ 0x38C800, 0x38D07F },         /* GAM, MEDIAINF */
-	{ 0x38D0D0, 0x38F0FF },		/* MEDIAINF, GAM */
+	{ 0x38D0D0, 0x38F0FF },         /* MEDIAINF, rsvd, GAM */
 	{ 0x393C00, 0x393C7F },         /* MEDIAINF */
 	{},
 };

-- 
2.51.0

[PATCH v2 07/22] drm/xe/xe3p: Stop programming RCU_MODE's fixed slice mode setting

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Since the hardware load balancing is no longer supported, the
programming in RCU_MODE is no longer necessary.

Bspec: 60382
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index cba4375525c7e..b08a6d42c8ffc 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -350,6 +350,13 @@ static bool xe_hw_engine_match_fixed_cslice_mode(const struct xe_device *xe,
 						 const struct xe_gt *gt,
 						 const struct xe_hw_engine *hwe)
 {
+	/*
+	 * Xe3p no longer supports load balance mode, so "fixed cslice" mode
+	 * is automatic and no RCU_MODE programming is required.
+	 */
+	if (GRAPHICS_VER(gt_to_xe(gt)) >= 35)
+		return false;
+
 	return xe_gt_ccs_mode_enabled(gt) &&
 	       xe_rtp_match_first_render_or_compute(xe, gt, hwe);
 }

-- 
2.51.0

[PATCH v2 08/22] drm/xe/xe3p: Determine service copy availability from fuse

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Xe3p introduces a dedicated SERVICE_COPY_ENABLE fuse register to reflect
the availability of the service copy engines (BCS1-BCS8).

Bspec: 74624
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_regs.h |  3 +++
 drivers/gpu/drm/xe/xe_hw_engine.c    | 43 ++++++++++++++++++++++++++++--------
 2 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 21c15441c4537..228de47c0f3f5 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -239,6 +239,9 @@
 #define XE2_GT_GEOMETRY_DSS_1			XE_REG(0x9150)
 #define XE2_GT_GEOMETRY_DSS_2			XE_REG(0x9154)
 
+#define SERVICE_COPY_ENABLE			XE_REG(0x9170)
+#define   FUSE_SERVICE_COPY_ENABLE_MASK		REG_GENMASK(7, 0)
+
 #define GDRST					XE_REG(0x941c)
 #define   GRDOM_GUC				REG_BIT(3)
 #define   GRDOM_FULL				REG_BIT(0)
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index b08a6d42c8ffc..073ecd263e543 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -718,27 +718,52 @@ static void read_media_fuses(struct xe_gt *gt)
 	}
 }
 
+static u32 infer_svccopy_from_meml3(struct xe_gt *gt)
+{
+	u32 meml3 = REG_FIELD_GET(MEML3_EN_MASK,
+				  xe_mmio_read32(&gt->mmio, MIRROR_FUSE3));
+	u32 svccopy_mask = 0;
+
+	/*
+	 * Each of the four meml3 bits determines the fusing of two service
+	 * copy engines.
+	 */
+	for (int i = 0; i < 4; i++)
+		svccopy_mask |= (meml3 & BIT(i)) ? 0b11 << 2 * i : 0;
+
+	return svccopy_mask;
+}
+
+static u32 read_svccopy_fuses(struct xe_gt *gt)
+{
+	return REG_FIELD_GET(FUSE_SERVICE_COPY_ENABLE_MASK,
+			     xe_mmio_read32(&gt->mmio, SERVICE_COPY_ENABLE));
+}
+
 static void read_copy_fuses(struct xe_gt *gt)
 {
 	struct xe_device *xe = gt_to_xe(gt);
 	u32 bcs_mask;
 
-	if (GRAPHICS_VERx100(xe) < 1260 || GRAPHICS_VERx100(xe) >= 1270)
-		return;
-
 	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
 
-	bcs_mask = xe_mmio_read32(&gt->mmio, MIRROR_FUSE3);
-	bcs_mask = REG_FIELD_GET(MEML3_EN_MASK, bcs_mask);
+	if (GRAPHICS_VER(xe) >= 35)
+		bcs_mask = read_svccopy_fuses(gt);
+	else if (GRAPHICS_VERx100(xe) == 1260)
+		bcs_mask = infer_svccopy_from_meml3(gt);
+	else
+		return;
 
-	/* BCS0 is always present; only BCS1-BCS8 may be fused off */
-	for (int i = XE_HW_ENGINE_BCS1, j = 0; i <= XE_HW_ENGINE_BCS8; ++i, ++j) {
+	/* Only BCS1-BCS8 may be fused off */
+	bcs_mask <<= XE_HW_ENGINE_BCS1;
+	for (int i = XE_HW_ENGINE_BCS1; i <= XE_HW_ENGINE_BCS8; ++i) {
 		if (!(gt->info.engine_mask & BIT(i)))
 			continue;
 
-		if (!(BIT(j / 2) & bcs_mask)) {
+		if (!(bcs_mask & BIT(i))) {
 			gt->info.engine_mask &= ~BIT(i);
-			xe_gt_info(gt, "bcs%u fused off\n", j);
+			xe_gt_info(gt, "bcs%u fused off\n",
+				   i - XE_HW_ENGINE_BCS0);
 		}
 	}
 }

-- 
2.51.0

[PATCH v2 09/22] drm/xe: Dump CURRENT_LRCA register

[Lucas De Marchi]

From: Wang Xin <x.wang@intel.com>

Add CURRENT_LRCA to register dump to help debugging.

Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Wang Xin <x.wang@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2: Extract CURRENT_LRCA from other patch dumping xe3p-specific register
    (Matt Roper)
---
 drivers/gpu/drm/xe/regs/xe_engine_regs.h | 3 +++
 drivers/gpu/drm/xe/xe_guc_capture.c      | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index f4c3e1187a00a..3c05d85902c69 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -141,6 +141,9 @@
 #define   INHIBIT_SWITCH_UNTIL_PREEMPTED	REG_BIT(31)
 #define   IDLE_DELAY				REG_GENMASK(20, 0)
 
+#define RING_CURRENT_LRCA(base)			XE_REG((base) + 0x240)
+#define   CURRENT_LRCA_VALID			REG_BIT(0)
+
 #define RING_CONTEXT_CONTROL(base)		XE_REG((base) + 0x244, XE_REG_OPTION_MASKED)
 #define	  CTX_CTRL_PXP_ENABLE			REG_BIT(10)
 #define	  CTX_CTRL_OAC_CONTEXT_ENABLE		REG_BIT(8)
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
index 243dad3e24185..8d1bfa2cdb151 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.c
+++ b/drivers/gpu/drm/xe/xe_guc_capture.c
@@ -122,6 +122,7 @@ struct __guc_capture_parsed_output {
 	{ RING_IPEHR(0),		REG_32BIT,	0,	0,	0,	"IPEHR"}, \
 	{ RING_INSTDONE(0),		REG_32BIT,	0,	0,	0,	"RING_INSTDONE"}, \
 	{ INDIRECT_RING_STATE(0),	REG_32BIT,	0,	0,	0,	"INDIRECT_RING_STATE"}, \
+	{ RING_CURRENT_LRCA(0),		REG_32BIT,	0,	0,	0,	"CURRENT_LRCA"}, \
 	{ RING_ACTHD(0),		REG_64BIT_LOW_DW, 0,	0,	0,	NULL}, \
 	{ RING_ACTHD_UDW(0),		REG_64BIT_HI_DW, 0,	0,	0,	"ACTHD"}, \
 	{ RING_BBADDR(0),		REG_64BIT_LOW_DW, 0,	0,	0,	NULL}, \

-- 
2.51.0

[PATCH v2 10/22] drm/xe/xe3p: Dump CSMQDEBUG register

[Lucas De Marchi]

From: Wang Xin <x.wang@intel.com>

The CSMQDEBUG is useful for the development of MQ feature. Start dumping
the debug register.

Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Wang Xin <x.wang@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2:
 - Extract CSMQDEBUG from other patch dumping multiple register (Matt
   Roper)
 - Simplify version check (Matt Roper)
 - Do not dump CSMQDEBUG for engines that do not support MQ (Matt Roper)
---
 drivers/gpu/drm/xe/regs/xe_engine_regs.h |  2 ++
 drivers/gpu/drm/xe/xe_guc_capture.c      | 48 +++++++++++++++++++++++++++++++-
 2 files changed, 49 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index 3c05d85902c69..7b6ec0cf78c85 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -156,6 +156,8 @@
 #define   GFX_DISABLE_LEGACY_MODE		REG_BIT(3)
 #define   GFX_MSIX_INTERRUPT_ENABLE		REG_BIT(13)
 
+#define RING_CSMQDEBUG(base)			XE_REG((base) + 0x2b0)
+
 #define RING_TIMESTAMP(base)			XE_REG((base) + 0x358)
 
 #define RING_TIMESTAMP_UDW(base)		XE_REG((base) + 0x358 + 4)
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
index 8d1bfa2cdb151..035b9b6c0df58 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.c
+++ b/drivers/gpu/drm/xe/xe_guc_capture.c
@@ -150,6 +150,9 @@ struct __guc_capture_parsed_output {
 	{ SFC_DONE(2),			0,	0,	0,	0,	"SFC_DONE[2]"}, \
 	{ SFC_DONE(3),			0,	0,	0,	0,	"SFC_DONE[3]"}
 
+#define XE3P_BASE_ENGINE_INSTANCE \
+	{ RING_CSMQDEBUG(0),		REG_32BIT,	0,	0,	0,	"CSMQDEBUG"}
+
 /* XE_LP Global */
 static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = {
 	COMMON_XELP_BASE_GLOBAL,
@@ -196,6 +199,32 @@ static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = {
 	COMMON_BASE_ENGINE_INSTANCE,
 };
 
+/* Render / Compute Per-Engine-Instance */
+static const struct __guc_mmio_reg_descr xe3p_rc_inst_regs[] = {
+	COMMON_BASE_ENGINE_INSTANCE,
+	XE3P_BASE_ENGINE_INSTANCE,
+};
+
+/* Media Decode/Encode Per-Engine-Instance */
+static const struct __guc_mmio_reg_descr xe3p_vd_inst_regs[] = {
+	COMMON_BASE_ENGINE_INSTANCE,
+};
+
+/* Video Enhancement Per-Engine-Instance */
+static const struct __guc_mmio_reg_descr xe3p_vec_inst_regs[] = {
+	COMMON_BASE_ENGINE_INSTANCE,
+};
+
+/* Blitter Per-Engine-Instance */
+static const struct __guc_mmio_reg_descr xe3p_blt_inst_regs[] = {
+	COMMON_BASE_ENGINE_INSTANCE,
+};
+
+/* XE3P - GSC Per-Engine-Instance */
+static const struct __guc_mmio_reg_descr xe3p_gsc_inst_regs[] = {
+	COMMON_BASE_ENGINE_INSTANCE,
+};
+
 /*
  * Empty list to prevent warnings about unknown class/instance types
  * as not all class/instance types have entries on all platforms.
@@ -246,6 +275,21 @@ static const struct __guc_mmio_reg_descr_group xe_hpg_lists[] = {
 	{}
 };
 
+ /* List of lists for Xe3p and beyond */
+static const struct __guc_mmio_reg_descr_group xe3p_lists[] = {
+	MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0),
+	MAKE_REGLIST(xe_hpg_rc_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
+	MAKE_REGLIST(xe3p_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
+	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO),
+	MAKE_REGLIST(xe3p_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO),
+	MAKE_REGLIST(xe_vec_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
+	MAKE_REGLIST(xe3p_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
+	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER),
+	MAKE_REGLIST(xe3p_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
+	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
+	MAKE_REGLIST(xe3p_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
+	{}
+};
 static const char * const capture_list_type_names[] = {
 	"Global",
 	"Class",
@@ -293,7 +337,9 @@ guc_capture_remove_stale_matches_from_list(struct xe_guc_state_capture *gc,
 static const struct __guc_mmio_reg_descr_group *
 guc_capture_get_device_reglist(struct xe_device *xe)
 {
-	if (GRAPHICS_VERx100(xe) >= 1255)
+	if (GRAPHICS_VER(xe) >= 35)
+		return xe3p_lists;
+	else if (GRAPHICS_VERx100(xe) >= 1255)
 		return xe_hpg_lists;
 	else
 		return xe_lp_lists;

-- 
2.51.0

[PATCH v2 11/22] drm/xe/nvl: Define NVL-S platform

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Provide the basic platform definitions and PCI IDs for NVL-S.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c            | 9 +++++++++
 drivers/gpu/drm/xe/xe_platform_types.h | 1 +
 include/drm/intel/pciids.h             | 9 +++++++++
 3 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index b72f71b0f52c9..d836fd8e187a6 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -377,6 +377,14 @@ static const struct xe_device_desc ptl_desc = {
 	.vm_max_level = 4,
 };
 
+static const struct xe_device_desc nvls_desc = {
+	PLATFORM(NOVALAKE_S),
+	.dma_mask_size = 46,
+	.has_display = true,
+	.max_gt_per_tile = 2,
+	.require_force_probe = true,
+};
+
 #undef PLATFORM
 __diag_pop();
 
@@ -405,6 +413,7 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
 	INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
 	INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
+	INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
 	{ }
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
index 3e332214c7bb4..78286285c2495 100644
--- a/drivers/gpu/drm/xe/xe_platform_types.h
+++ b/drivers/gpu/drm/xe/xe_platform_types.h
@@ -24,6 +24,7 @@ enum xe_platform {
 	XE_LUNARLAKE,
 	XE_BATTLEMAGE,
 	XE_PANTHERLAKE,
+	XE_NOVALAKE_S,
 };
 
 enum xe_subplatform {
diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
index 452c1de606ff2..13c592e1a28c7 100644
--- a/include/drm/intel/pciids.h
+++ b/include/drm/intel/pciids.h
@@ -887,4 +887,13 @@
 	MACRO__(0xFD80, ## __VA_ARGS__), \
 	MACRO__(0xFD81, ## __VA_ARGS__)
 
+/* NVL-S */
+#define INTEL_NVLS_IDS(MACRO__, ...) \
+	MACRO__(0xD740, ## __VA_ARGS__), \
+	MACRO__(0xD741, ## __VA_ARGS__), \
+	MACRO__(0xD742, ## __VA_ARGS__), \
+	MACRO__(0xD743, ## __VA_ARGS__), \
+	MACRO__(0xD744, ## __VA_ARGS__), \
+	MACRO__(0xD745, ## __VA_ARGS__)
+
 #endif /* __PCIIDS_H__ */

-- 
2.51.0

[PATCH v2 12/22] drm/xe/nvls: Define GuC firmware for NVL-S

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Although NVL-S has a similar Xe3 to PTL/WCL, it requires a unique GuC
firmware.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_uc_fw.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index 6056ecd0b92f5..e589c7e38f125 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -115,6 +115,7 @@ struct fw_blobs_by_type {
 #define XE_GT_TYPE_ANY XE_GT_TYPE_UNINITIALIZED
 
 #define XE_GUC_FIRMWARE_DEFS(fw_def, mmp_ver, major_ver)					\
+	fw_def(NOVALAKE_S,	GT_TYPE_ANY,	mmp_ver(xe,	guc,	nvl,	70, 49, 4))	\
 	fw_def(PANTHERLAKE,	GT_TYPE_ANY,	major_ver(xe,	guc,	ptl,	70, 49, 4))	\
 	fw_def(BATTLEMAGE,	GT_TYPE_ANY,	major_ver(xe,	guc,	bmg,	70, 49, 4))	\
 	fw_def(LUNARLAKE,	GT_TYPE_ANY,	major_ver(xe,	guc,	lnl,	70, 45, 2))	\

-- 
2.51.0

[PATCH v2 13/22] drm/xe/nvls: Attach MOCS table for NVL-S

[Lucas De Marchi]

From: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>

The MOCS table for NVL-S is the same as that of
Xe2.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_mocs.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
index 7b68c22ff7bbc..e8ec4114302e5 100644
--- a/drivers/gpu/drm/xe/xe_mocs.c
+++ b/drivers/gpu/drm/xe/xe_mocs.c
@@ -576,6 +576,7 @@ static unsigned int get_mocs_settings(struct xe_device *xe,
 	memset(info, 0, sizeof(struct xe_mocs_info));
 
 	switch (xe->info.platform) {
+	case XE_NOVALAKE_S:
 	case XE_PANTHERLAKE:
 	case XE_LUNARLAKE:
 	case XE_BATTLEMAGE:

-- 
2.51.0

[PATCH v2 14/22] drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition

[Lucas De Marchi]

From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Add support for graphics IP Xe3p_XPC having IP version 35.11.

Bspec: 77979, 77975
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index d836fd8e187a6..b4e0e16ad558d 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -106,6 +106,13 @@ static const struct xe_graphics_desc graphics_xe2 = {
 	XE2_GFX_FEATURES,
 };
 
+static const struct xe_graphics_desc graphics_xe3p_xpc = {
+	XE2_GFX_FEATURES,
+	.hw_engine_mask =
+		GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) |
+		GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0),
+};
+
 static const struct xe_media_desc media_xem = {
 	.hw_engine_mask =
 		GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
@@ -138,6 +145,7 @@ static const struct xe_ip graphics_ips[] = {
 	{ 3003, "Xe3_LPG", &graphics_xe2 },
 	{ 3004, "Xe3_LPG", &graphics_xe2 },
 	{ 3005, "Xe3_LPG", &graphics_xe2 },
+	{ 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
 };
 
 /* Pre-GMDID Media IPs */

-- 
2.51.0

[PATCH v2 15/22] drm/xe/xe3p_xpc: Add L3 bank mask

[Lucas De Marchi]

From: Fei Yang <fei.yang@intel.com>

Expose L3 bank mask through topology query interface.

In Xe3p_XPC, MIRROR_L3BANK_ENABLE represents the full L3 bank mask (not
just a per-node mask), and each bit represents a single bank. With that
there's no extra complexity to calculate the L3 bank mask like there was
in previous platforms.

Bspec: 73439
Signed-off-by: Fei Yang <fei.yang@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2: Better commit message (Matt Roper)
---
 drivers/gpu/drm/xe/xe_gt_topology.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
index 80ef3a6e0a3b5..14af073783ad3 100644
--- a/drivers/gpu/drm/xe/xe_gt_topology.c
+++ b/drivers/gpu/drm/xe/xe_gt_topology.c
@@ -148,7 +148,11 @@ load_l3_bank_mask(struct xe_gt *gt, xe_l3_bank_mask_t l3_bank_mask)
 	if (!xe_gt_topology_report_l3(gt))
 		return;
 
-	if (GRAPHICS_VER(xe) >= 30) {
+	if (GRAPHICS_VERx100(xe) == 3511) {
+		u32 fuse_val = xe_mmio_read32(mmio, MIRROR_L3BANK_ENABLE);
+
+		bitmap_from_arr32(l3_bank_mask, &fuse_val, 32);
+	} else if (GRAPHICS_VER(xe) >= 30) {
 		xe_l3_bank_mask_t per_node = {};
 		u32 meml3_en = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, fuse3);
 		u32 mirror_l3bank_enable = xe_mmio_read32(mmio, MIRROR_L3BANK_ENABLE);

-- 
2.51.0

[PATCH v2 16/22] drm/xe/xe3p_xpc: Add MCR steering

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Xe3p_XPC's steering has a few changes from Xe3.  Aside from
minor changes to the XeCore (the new name for what used to be "DSS") and
INSTANCE0 tables, different rules apply to different subranges of type
"GAM."  Certain GAM subranges require steering to grp/instance (0,0)
(and thus use the INSTANCE0 table), while others require special
steering to (1,0) instead.  Similarly, there are multiple classes of
"PSMI" steering, with some requiring steering to (0,0) while others
require (19,0).

FIXME: There's an "L3BANK" range listed in the bspec that needs
clarification.

Bspec: 74418
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_gt_mcr.c   | 56 ++++++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/xe/xe_gt_types.h | 15 +++++++++++
 2 files changed, 69 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index e1a2b38fc2a86..e5506ec28e147 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -169,6 +169,15 @@ static const struct xe_mmio_range xelpg_dss_steering_table[] = {
 	{},
 };
 
+static const struct xe_mmio_range xe3p_xpc_xecore_steering_table[] = {
+	{ 0x008140, 0x00817F },         /* SLICE, XeCore, SLICE */
+	{ 0x009480, 0x00955F },         /* SLICE, XeCore */
+	{ 0x00D800, 0x00D87F },		/* SLICE */
+	{ 0x00DC00, 0x00E9FF },         /* SLICE, rsvd, XeCore, rsvd, XeCore, rsvd, XeCore */
+	{ 0x013000, 0x0135FF },         /* XeCore, SLICE */
+	{},
+};
+
 static const struct xe_mmio_range xelpmp_oaddrm_steering_table[] = {
 	{ 0x393200, 0x39323F },
 	{ 0x393400, 0x3934FF },
@@ -247,6 +256,30 @@ static const struct xe_mmio_range xe3lpm_instance0_steering_table[] = {
 	{},
 };
 
+/*
+ * Different "GAM" ranges have different rules; GAMWKRS, STLB, and GAMREQSTRM
+ * range subtypes need to be steered to (1,0), while all other GAM subtypes
+ * are steered to (0,0) and are included in the "INSTANCE0" table farther
+ * down.
+ */
+static const struct xe_mmio_range xe3p_xpc_gam_grp1_steering_table[] = {
+	{ 0x004000, 0x004AFF },		/* GAMREQSTRM, rsvd, STLB, GAMWKRS, GAMREQSTRM */
+	{ 0x00F100, 0x00FFFF },		/* GAMWKRS */
+	{},
+};
+
+static const struct xe_mmio_range xe3p_xpc_psmi_grp19_steering_table[] = {
+	{ 0x00B500, 0x00B5FF },
+	{},
+};
+
+static const struct xe_mmio_range xe3p_xpc_instance0_steering_table[] = {
+	{ 0x00B600, 0x00B6FF },		/* PSMI0 */
+	{ 0x00C800, 0x00CFFF },		/* GAMCTRL */
+	{ 0x00F000, 0x00F0FF },		/* GAMCTRL */
+	{},
+};
+
 static void init_steering_l3bank(struct xe_gt *gt)
 {
 	struct xe_mmio *mmio = &gt->mmio;
@@ -419,6 +452,18 @@ static void init_steering_sqidi_psmi(struct xe_gt *gt)
 	gt->steering[SQIDI_PSMI].instance_target = select & 0x1;
 }
 
+static void init_steering_psmi(struct xe_gt *gt)
+{
+	gt->steering[PSMI19].group_target = 19;
+	gt->steering[PSMI19].instance_target = 0;
+}
+
+static void init_steering_gam1(struct xe_gt *gt)
+{
+	gt->steering[GAM1].group_target = 1;
+	gt->steering[GAM1].instance_target = 0;
+}
+
 static const struct {
 	const char *name;
 	void (*init)(struct xe_gt *gt);
@@ -426,9 +471,11 @@ static const struct {
 	[L3BANK] =	{ "L3BANK",	init_steering_l3bank },
 	[MSLICE] =	{ "MSLICE",	init_steering_mslice },
 	[LNCF] =	{ "LNCF",	NULL }, /* initialized by mslice init */
-	[DSS] =		{ "DSS",	init_steering_dss },
+	[DSS] =		{ "DSS / XeCore", init_steering_dss },
 	[OADDRM] =	{ "OADDRM / GPMXMT", init_steering_oaddrm },
 	[SQIDI_PSMI] =  { "SQIDI_PSMI", init_steering_sqidi_psmi },
+	[PSMI19] =	{ "PSMI[19]",	init_steering_psmi },
+	[GAM1] =	{ "GAMWKRS / STLB / GAMREQSTRM", init_steering_gam1 },
 	[INSTANCE0] =	{ "INSTANCE 0",	NULL },
 	[IMPLICIT_STEERING] = { "IMPLICIT", NULL },
 };
@@ -467,7 +514,12 @@ void xe_gt_mcr_init_early(struct xe_gt *gt)
 			gt->steering[OADDRM].ranges = xelpmp_oaddrm_steering_table;
 		}
 	} else {
-		if (GRAPHICS_VER(xe) >= 20) {
+		if (GRAPHICS_VERx100(xe) == 3511) {
+			gt->steering[DSS].ranges = xe3p_xpc_xecore_steering_table;
+			gt->steering[GAM1].ranges = xe3p_xpc_gam_grp1_steering_table;
+			gt->steering[INSTANCE0].ranges = xe3p_xpc_instance0_steering_table;
+			gt->steering[PSMI19].ranges = xe3p_xpc_psmi_grp19_steering_table;
+		} else if (GRAPHICS_VER(xe) >= 20) {
 			gt->steering[DSS].ranges = xe2lpg_dss_steering_table;
 			gt->steering[SQIDI_PSMI].ranges = xe2lpg_sqidi_psmi_steering_table;
 			gt->steering[INSTANCE0].ranges = xe2lpg_instance0_steering_table;
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index 8b5f604d7883a..d93faa1eedef8 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -72,6 +72,21 @@ enum xe_steering_type {
 	OADDRM,
 	SQIDI_PSMI,
 
+	/*
+	 * The bspec lists multiple ranges as "PSMI," but the different
+	 * ranges with that label have different grpid steering values so we
+	 * treat them independently in code.  Note that the ranges with grpid=0
+	 * are included in the INSTANCE0 group above.
+	 */
+	PSMI19,
+
+	/*
+	 * Although most GAM ranges must be steered to (0,0) and thus use the
+	 * INSTANCE0 type farther down, some platforms have special rules
+	 * for specific subtypes that require steering to (1,0) instead.
+	 */
+	GAM1,
+
 	/*
 	 * On some platforms there are multiple types of MCR registers that
 	 * will always return a non-terminated value at instance (0, 0).  We'll

-- 
2.51.0

[PATCH v2 17/22] drm/xe/irq: Rename fuse mask variables

[Lucas De Marchi]

It's confusing to refer to some masks as the interrupt masks and others
as the fuse masks. Rename the fuse one to make it clearer.

Note that the most important role they play here is that the call
to xe_hw_engine_mask_per_class() will not only limit the engines
according to the fuses, but also by what is available in the specific
architecture - the latter is more important information to know what
interrupts should be enabled. Add a comment about that.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_irq.c | 30 ++++++++++++++++++------------
 1 file changed, 18 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 838fb512b7779..9c3a85c4585ed 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -139,7 +139,6 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
 {
 	struct xe_device *xe = gt_to_xe(gt);
 	struct xe_mmio *mmio = &gt->mmio;
-	u32 ccs_mask, bcs_mask;
 	u32 irqs, dmask, smask;
 	u32 gsc_mask = 0;
 	u32 heci_mask = 0;
@@ -157,36 +156,43 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
 		       GT_WAIT_SEMAPHORE_INTERRUPT;
 	}
 
-	ccs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
-	bcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
-
 	dmask = irqs << 16 | irqs;
 	smask = irqs << 16;
 
 	if (xe_gt_is_main_type(gt)) {
+		/*
+		 * For enabling the interrupts, the information about fused off
+		 * engines doesn't matter much, but this also allows to check if
+		 * the engine is available architecturally in the platform
+		 */
+		u32 ccs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
+		u32 bcs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
+
 		/* Enable interrupts for each engine class */
 		xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, dmask);
-		if (ccs_mask)
+		if (ccs_fuse_mask)
 			xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, smask);
 
 		/* Unmask interrupts for each engine instance */
 		xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~smask);
 		xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~smask);
-		if (bcs_mask & (BIT(1)|BIT(2)))
+		if (bcs_fuse_mask & (BIT(1)|BIT(2)))
 			xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
-		if (bcs_mask & (BIT(3)|BIT(4)))
+		if (bcs_fuse_mask & (BIT(3)|BIT(4)))
 			xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
-		if (bcs_mask & (BIT(5)|BIT(6)))
+		if (bcs_fuse_mask & (BIT(5)|BIT(6)))
 			xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
-		if (bcs_mask & (BIT(7)|BIT(8)))
+		if (bcs_fuse_mask & (BIT(7)|BIT(8)))
 			xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
-		if (ccs_mask & (BIT(0)|BIT(1)))
+		if (ccs_fuse_mask & (BIT(0)|BIT(1)))
 			xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~dmask);
-		if (ccs_mask & (BIT(2)|BIT(3)))
+		if (ccs_fuse_mask & (BIT(2)|BIT(3)))
 			xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~dmask);
 	}
 
 	if (xe_gt_is_media_type(gt) || MEDIA_VER(xe) < 13) {
+		u32 other_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER);
+
 		/* Enable interrupts for each engine class */
 		xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, dmask);
 
@@ -199,7 +205,7 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
 		 * the heci2 interrupt is enabled via the same register as the
 		 * GSCCS interrupts, but it has its own mask register.
 		 */
-		if (xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER)) {
+		if (other_fuse_mask) {
 			gsc_mask = irqs | GSC_ER_COMPLETE;
 			heci_mask = GSC_IRQ_INTF(1);
 		} else if (xe->info.has_heci_gscfi) {

-- 
2.51.0

[PATCH v2 18/22] drm/xe/irq: Split irq mask per engine class

[Lucas De Marchi]

Each engine class has a different bitfield structure in the hw. We've
been just using a common mask for all of them, but this means that we
could inadvertently set a wrong bit in one class while enabling
something in another. Split them to make it more future proof.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_irq.c | 73 +++++++++++++++++++++++++++++----------------
 1 file changed, 47 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 9c3a85c4585ed..103804546b280 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -139,25 +139,28 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
 {
 	struct xe_device *xe = gt_to_xe(gt);
 	struct xe_mmio *mmio = &gt->mmio;
-	u32 irqs, dmask, smask;
-	u32 gsc_mask = 0;
-	u32 heci_mask = 0;
+	u32 common_mask, val, gsc_mask = 0, heci_mask = 0,
+	    rcs_mask = 0, bcs_mask = 0, vcs_mask = 0, vecs_mask = 0,
+	    ccs_mask = 0;
 
 	if (xe_device_uses_memirq(xe))
 		return;
 
 	if (xe_device_uc_enabled(xe)) {
-		irqs = GT_RENDER_USER_INTERRUPT |
-			GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
+		common_mask = GT_RENDER_USER_INTERRUPT |
+			      GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
 	} else {
-		irqs = GT_RENDER_USER_INTERRUPT |
-		       GT_CS_MASTER_ERROR_INTERRUPT |
-		       GT_CONTEXT_SWITCH_INTERRUPT |
-		       GT_WAIT_SEMAPHORE_INTERRUPT;
+		common_mask = GT_RENDER_USER_INTERRUPT |
+			      GT_CS_MASTER_ERROR_INTERRUPT |
+			      GT_CONTEXT_SWITCH_INTERRUPT |
+			      GT_WAIT_SEMAPHORE_INTERRUPT;
 	}
 
-	dmask = irqs << 16 | irqs;
-	smask = irqs << 16;
+	rcs_mask |= common_mask;
+	bcs_mask |= common_mask;
+	vcs_mask |= common_mask;
+	vecs_mask |= common_mask;
+	ccs_mask |= common_mask;
 
 	if (xe_gt_is_main_type(gt)) {
 		/*
@@ -169,44 +172,62 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
 		u32 bcs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
 
 		/* Enable interrupts for each engine class */
-		xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, dmask);
+		xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE,
+				REG_FIELD_PREP(ENGINE1_MASK, rcs_mask) |
+				REG_FIELD_PREP(ENGINE0_MASK, bcs_mask));
 		if (ccs_fuse_mask)
-			xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, smask);
+			xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE,
+					REG_FIELD_PREP(ENGINE1_MASK, ccs_mask));
 
 		/* Unmask interrupts for each engine instance */
-		xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~smask);
-		xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~smask);
+		val = ~REG_FIELD_PREP(ENGINE1_MASK, rcs_mask);
+		xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, val);
+		val = ~REG_FIELD_PREP(ENGINE1_MASK, bcs_mask);
+		xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, val);
+
+		val = ~(REG_FIELD_PREP(ENGINE1_MASK, bcs_mask) |
+			REG_FIELD_PREP(ENGINE0_MASK, bcs_mask));
 		if (bcs_fuse_mask & (BIT(1)|BIT(2)))
-			xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
+			xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, val);
 		if (bcs_fuse_mask & (BIT(3)|BIT(4)))
-			xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
+			xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, val);
 		if (bcs_fuse_mask & (BIT(5)|BIT(6)))
-			xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
+			xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, val);
 		if (bcs_fuse_mask & (BIT(7)|BIT(8)))
-			xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
+			xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, val);
+
+		val = ~(REG_FIELD_PREP(ENGINE1_MASK, ccs_mask) |
+			REG_FIELD_PREP(ENGINE0_MASK, ccs_mask));
 		if (ccs_fuse_mask & (BIT(0)|BIT(1)))
-			xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~dmask);
+			xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, val);
 		if (ccs_fuse_mask & (BIT(2)|BIT(3)))
-			xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~dmask);
+			xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, val);
 	}
 
 	if (xe_gt_is_media_type(gt) || MEDIA_VER(xe) < 13) {
 		u32 other_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER);
 
 		/* Enable interrupts for each engine class */
-		xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, dmask);
+		xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE,
+				REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
+				REG_FIELD_PREP(ENGINE1_MASK, vecs_mask));
 
 		/* Unmask interrupts for each engine instance */
-		xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~dmask);
-		xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~dmask);
-		xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~dmask);
+		val = ~(REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
+			REG_FIELD_PREP(ENGINE0_MASK, vcs_mask));
+		xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, val);
+		xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, val);
+
+		val = ~(REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
+			REG_FIELD_PREP(ENGINE0_MASK, vcs_mask));
+		xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, val);
 
 		/*
 		 * the heci2 interrupt is enabled via the same register as the
 		 * GSCCS interrupts, but it has its own mask register.
 		 */
 		if (other_fuse_mask) {
-			gsc_mask = irqs | GSC_ER_COMPLETE;
+			gsc_mask = common_mask | GSC_ER_COMPLETE;
 			heci_mask = GSC_IRQ_INTF(1);
 		} else if (xe->info.has_heci_gscfi) {
 			gsc_mask = GSC_IRQ_INTF(1);

-- 
2.51.0

[PATCH v2 19/22] drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx

[Lucas De Marchi]

Current implementation of compute walker has dependency on GPU/SW Stack
which requires SW/UMD to wait for event from KMD to indicate
PIPE_CONTROL interrupt was done. This created latency on SW stack.

This feature adds support to generate completion interrupt from GPGPU
walker which does not support MSIx and avoid software using Pipe control
drain/idle latency.

Suggested-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: S A Muqthyar Ahmed <syed.abdul.muqthyar.ahmed@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2: Rebase on split mask per engine class
---
 drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
 drivers/gpu/drm/xe/xe_irq.c           | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
index 7c2a3a1401424..9c46b5fb81412 100644
--- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
@@ -82,6 +82,7 @@
 #define   GSC_ER_COMPLETE			REG_BIT(5)
 #define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)
 #define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
+#define   GT_COMPUTE_WALKER_INTERRUPT		REG_BIT(2)
 #define   GT_RENDER_USER_INTERRUPT		REG_BIT(0)
 
 /* irqs for OTHER_KCR_INSTANCE */
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 103804546b280..ac5524cbe4b9a 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -149,6 +149,12 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
 	if (xe_device_uc_enabled(xe)) {
 		common_mask = GT_RENDER_USER_INTERRUPT |
 			      GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
+
+		/* Enable Compute Walker Interrupt for non-MSIX platforms */
+		if (GRAPHICS_VERx100(xe) >= 3511 && !xe_device_has_msix(xe)) {
+			rcs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
+			ccs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
+		}
 	} else {
 		common_mask = GT_RENDER_USER_INTERRUPT |
 			      GT_CS_MASTER_ERROR_INTERRUPT |

-- 
2.51.0

[PATCH v2 20/22] drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

The compression overfetch tuning settings only apply to platforms that
support FlatCCS.  In Xe3p_XPC (and any future IPs that also lack
compression) some of the registers being adjusted by this tuning will
not exist or may have been repurposed for something else, so we should
take care not to try to program them.

Note that our xe_rtp_match_has_flatccs() function will also return false
on platforms that do have FlatCCS in the hardware design, but have
compression manually disabled in the BIOS.  On such platforms the
registers still exist (and it would be fine to continue programming
them), but they would have no effect, so skipping that tuning is also
safe.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_rtp.c    |  7 +++++++
 drivers/gpu/drm/xe/xe_rtp.h    | 12 ++++++++++++
 drivers/gpu/drm/xe/xe_tuning.c |  9 ++++++---
 3 files changed, 25 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
index 66707cc89ec97..ed509b1c8cfcd 100644
--- a/drivers/gpu/drm/xe/xe_rtp.c
+++ b/drivers/gpu/drm/xe/xe_rtp.c
@@ -378,3 +378,10 @@ bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_device *xe,
 {
 	return xe_gt_has_discontiguous_dss_groups(gt);
 }
+
+bool xe_rtp_match_has_flat_ccs(const struct xe_device *xe,
+			       const struct xe_gt *gt,
+			       const struct xe_hw_engine *hwe)
+{
+	return xe->info.has_flat_ccs;
+}
diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
index e5b8a9452e29e..ba5f940c0a961 100644
--- a/drivers/gpu/drm/xe/xe_rtp.h
+++ b/drivers/gpu/drm/xe/xe_rtp.h
@@ -491,4 +491,16 @@ bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_device *xe,
 						  const struct xe_gt *gt,
 						  const struct xe_hw_engine *hwe);
 
+/**
+ * xe_rtp_match_has_flat_ccs - Match when platform has FlatCCS compression
+ * @xe: Device structure
+ * @gt: GT structure
+ * @hwe: Engine instance
+ *
+ * Returns: true if platform has FlatCCS compression, false otherwise
+ */
+bool xe_rtp_match_has_flat_ccs(const struct xe_device *xe,
+			       const struct xe_gt *gt,
+			       const struct xe_hw_engine *hwe);
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index fd58ea5e78bf6..7c140d8cb1e07 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -40,7 +40,8 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
 				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
 	},
 	{ XE_RTP_NAME("Tuning: Compression Overfetch"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
+		       FUNC(xe_rtp_match_has_flat_ccs)),
 	  XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
 			 SET(CCCHKNREG1, L3CMPCTRL))
 	},
@@ -58,12 +59,14 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
 	  XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3, COMPPWOVERFETCHEN))
 	},
 	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
+		       FUNC(xe_rtp_match_has_flat_ccs)),
 	  XE_RTP_ACTIONS(SET(L3SQCREG2,
 			     COMPMEMRD256BOVRFETCHEN))
 	},
 	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only - media"),
-	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
+	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED),
+		       FUNC(xe_rtp_match_has_flat_ccs)),
 	  XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
 			     COMPMEMRD256BOVRFETCHEN))
 	},

-- 
2.51.0

[PATCH v2 21/22] drm/xe/xe3p_xpc: Setup PAT table

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Xe3p_XPC IP requires a new PAT table; note that this table has one fewer
column than the Xe2/Xe3 tables since compression is not supported.
There's also no "WT" entry (which we wouldn't have used on a platform
without display anyway).

Bspec: 71582
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_pat.c | 96 ++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 95 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index 6e48ff84ad0a0..7649b554942aa 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -154,6 +154,41 @@ static const struct xe_pat_table_entry xe2_pat_table[] = {
 static const struct xe_pat_table_entry xe2_pat_ats = XE2_PAT( 0, 0, 0, 0, 3, 3 );
 static const struct xe_pat_table_entry xe2_pat_pta = XE2_PAT( 0, 0, 0, 0, 3, 0 );
 
+/*
+ * Xe3p_XPC PAT table uses the same layout as Xe2/Xe3, except that there's no
+ * option for compression.  Also note that the "L3" and "L4" register fields
+ * actually control L2 and L3 cache respectively on this platform.
+ */
+#define XE3P_XPC_PAT(no_promote, l3clos, l3_policy, l4_policy, __coh_mode) \
+	XE2_PAT(no_promote, 0, l3clos, l3_policy, l4_policy, __coh_mode)
+
+static const struct xe_pat_table_entry xe3p_xpc_pat_ats = XE3P_XPC_PAT( 0, 0, 0, 0, 3 );
+static const struct xe_pat_table_entry xe3p_xpc_pat_pta = XE3P_XPC_PAT( 0, 0, 0, 0, 0 );
+
+static const struct xe_pat_table_entry xe3p_xpc_pat_table[] = {
+	[ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ),
+	[ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ),
+	[ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ),
+	[ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ),
+	[ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ),
+	[ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ),
+	[ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ),
+	[ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ),
+	[ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ),
+	[ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ),
+	[10] = XE3P_XPC_PAT( 0, 0, 0, 3, 3 ),
+	/* 11..22 are reserved; leave set to all 0's */
+	[23] = XE3P_XPC_PAT( 0, 1, 0, 0, 0 ),
+	[24] = XE3P_XPC_PAT( 0, 1, 0, 0, 2 ),
+	[25] = XE3P_XPC_PAT( 0, 1, 0, 0, 3 ),
+	[26] = XE3P_XPC_PAT( 0, 2, 0, 0, 0 ),
+	[27] = XE3P_XPC_PAT( 0, 2, 0, 0, 2 ),
+	[28] = XE3P_XPC_PAT( 0, 2, 0, 0, 3 ),
+	[29] = XE3P_XPC_PAT( 0, 3, 0, 0, 0 ),
+	[30] = XE3P_XPC_PAT( 0, 3, 0, 0, 2 ),
+	[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),
+};
+
 u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index)
 {
 	WARN_ON(pat_index >= xe->pat.n_entries);
@@ -380,9 +415,68 @@ static const struct xe_pat_ops xe2_pat_ops = {
 	.dump = xe2_dump,
 };
 
+static int xe3p_xpc_dump(struct xe_gt *gt, struct drm_printer *p)
+{
+	struct xe_device *xe = gt_to_xe(gt);
+	unsigned int fw_ref;
+	u32 pat;
+	int i;
+
+	fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
+	if (!fw_ref)
+		return -ETIMEDOUT;
+
+	drm_printf(p, "PAT table:\n");
+
+	for (i = 0; i < xe->pat.n_entries; i++) {
+		pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));
+
+		drm_printf(p, "PAT[%2d] = [ %u, %u, %u, %u, %u ]  (%#8x)\n", i,
+			   !!(pat & XE2_NO_PROMOTE),
+			   REG_FIELD_GET(XE2_L3_CLOS, pat),
+			   REG_FIELD_GET(XE2_L3_POLICY, pat),
+			   REG_FIELD_GET(XE2_L4_POLICY, pat),
+			   REG_FIELD_GET(XE2_COH_MODE, pat),
+			   pat);
+	}
+
+	/*
+	 * Also print PTA_MODE, which describes how the hardware accesses
+	 * PPGTT entries.
+	 */
+	pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA));
+
+	drm_printf(p, "Page Table Access:\n");
+	drm_printf(p, "PTA_MODE= [ %u, %u, %u, %u, %u ]  (%#8x)\n",
+		   !!(pat & XE2_NO_PROMOTE),
+		   REG_FIELD_GET(XE2_L3_CLOS, pat),
+		   REG_FIELD_GET(XE2_L3_POLICY, pat),
+		   REG_FIELD_GET(XE2_L4_POLICY, pat),
+		   REG_FIELD_GET(XE2_COH_MODE, pat),
+		   pat);
+
+	xe_force_wake_put(gt_to_fw(gt), fw_ref);
+	return 0;
+}
+
+static const struct xe_pat_ops xe3p_xpc_pat_ops = {
+	.program_graphics = program_pat_mcr,
+	.program_media = program_pat,
+	.dump = xe3p_xpc_dump,
+};
+
 void xe_pat_init_early(struct xe_device *xe)
 {
-	if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
+	if (GRAPHICS_VERx100(xe) == 3511) {
+		xe->pat.ops = &xe3p_xpc_pat_ops;
+		xe->pat.table = xe3p_xpc_pat_table;
+		xe->pat.pat_ats = &xe3p_xpc_pat_ats;
+		xe->pat.pat_pta = &xe3p_xpc_pat_pta;
+		xe->pat.n_entries = ARRAY_SIZE(xe3p_xpc_pat_table);
+		xe->pat.idx[XE_CACHE_NONE] = 3;
+		xe->pat.idx[XE_CACHE_WT] = 3;	/* N/A (no display); use UC */
+		xe->pat.idx[XE_CACHE_WB] = 2;
+	} else if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
 		xe->pat.ops = &xe2_pat_ops;
 		xe->pat.table = xe2_pat_table;
 		xe->pat.pat_ats = &xe2_pat_ats;

-- 
2.51.0

[PATCH v2 22/22] drm/xe/xe3p: Add xe3p EU stall data format

[Lucas De Marchi]

From: Harish Chegondi <harish.chegondi@intel.com>

Starting with Xe3p, IP address in EU stall data increases to 61 bits.
While at it, re-order the if-else ladder so the officially supported
platforms come before PVC.

Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2: reorder the if-else ladder so PVC is the last (Lucas)

TODO: double check data format as it's missing from bspec
---
 drivers/gpu/drm/xe/xe_eu_stall.c | 28 ++++++++++++++++++++++++++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
index f5cfdf29fde34..650e45f6a7c7e 100644
--- a/drivers/gpu/drm/xe/xe_eu_stall.c
+++ b/drivers/gpu/drm/xe/xe_eu_stall.c
@@ -124,6 +124,27 @@ struct xe_eu_stall_data_xe2 {
 	__u64 unused[6];
 } __packed;
 
+/*
+ * EU stall data format for Xe3p arch GPUs.
+ */
+struct xe_eu_stall_data_xe3p {
+	__u64 ip_addr:61;	  /* Bits 0  to 60  */
+	__u64 tdr_count:8;	  /* Bits 61 to 68  */
+	__u64 other_count:8;	  /* Bits 69 to 76  */
+	__u64 control_count:8;	  /* Bits 77 to 84  */
+	__u64 pipestall_count:8;  /* Bits 85 to 92  */
+	__u64 send_count:8;	  /* Bits 93 to 100 */
+	__u64 dist_acc_count:8;   /* Bits 101 to 108 */
+	__u64 sbid_count:8;	  /* Bits 109 to 116 */
+	__u64 sync_count:8;	  /* Bits 117 to 124 */
+	__u64 inst_fetch_count:8; /* Bits 125 to 132 */
+	__u64 active_count:8;	  /* Bits 133 to 140 */
+	__u64 ex_id:3;		  /* Bits 141 to 143 */
+	__u64 end_flag:1;	  /* Bit  144 */
+	__u64 unused_bits:47;
+	__u64 unused[5];
+} __packed;
+
 const u64 eu_stall_sampling_rates[] = {251, 251 * 2, 251 * 3, 251 * 4, 251 * 5, 251 * 6, 251 * 7};
 
 /**
@@ -167,10 +188,13 @@ size_t xe_eu_stall_data_record_size(struct xe_device *xe)
 {
 	size_t record_size = 0;
 
-	if (xe->info.platform == XE_PVC)
-		record_size = sizeof(struct xe_eu_stall_data_pvc);
+	if (GRAPHICS_VER(xe) >= 35)
+		record_size = sizeof(struct xe_eu_stall_data_xe3p);
 	else if (GRAPHICS_VER(xe) >= 20)
 		record_size = sizeof(struct xe_eu_stall_data_xe2);
+	else if (xe->info.platform == XE_PVC)
+		record_size = sizeof(struct xe_eu_stall_data_pvc);
+
 
 	xe_assert(xe, is_power_of_2(record_size));
 

-- 
2.51.0

Re: [PATCH v2 03/22] drm/xe: Drop CTC_MODE register read

[Matt Roper]

On Wed, Oct 15, 2025 at 03:06:18PM -0700, Lucas De Marchi wrote:
> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> 
> The warning was added for a condition that never triggered even for
> platforms prior to Xe2. It's not supported in Xe2 and in Xe3p the
> register is removed from the main GT. Just drop the entire function as
> it doesn't bring any benefit.
> 
> Bspec: 62395
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> [ Drop the entire check for CTC_MODE ]
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

As far as we know, the warning has never been tripped, so (as we
suspected) it doesn't appear that this bit has ever been set on
production hardware.  Removing should be safe.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  4 ----
>  drivers/gpu/drm/xe/xe_gt_clock.c     | 19 -------------------
>  2 files changed, 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 51f2a03847f9d..21c15441c4537 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -346,10 +346,6 @@
>  #define   VDN_HCP_POWERGATE_ENABLE(n)		REG_BIT(3 + 2 * (n))
>  #define   VDN_MFXVDENC_POWERGATE_ENABLE(n)	REG_BIT(4 + 2 * (n))
>  
> -#define CTC_MODE				XE_REG(0xa26c)
> -#define   CTC_SHIFT_PARAMETER_MASK		REG_GENMASK(2, 1)
> -#define   CTC_SOURCE_DIVIDE_LOGIC		REG_BIT(0)
> -
>  #define FORCEWAKE_RENDER			XE_REG(0xa278)
>  
>  #define POWERGATE_DOMAIN_STATUS			XE_REG(0xa2a0)
> diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
> index 4f011d1573c65..00f5972c14dc5 100644
> --- a/drivers/gpu/drm/xe/xe_gt_clock.c
> +++ b/drivers/gpu/drm/xe/xe_gt_clock.c
> @@ -55,30 +55,11 @@ static void read_crystal_clock(struct xe_gt *gt, u32 rpm_config_reg, u32 *freq,
>  	}
>  }
>  
> -static void check_ctc_mode(struct xe_gt *gt)
> -{
> -	/*
> -	 * CTC_MODE[0] = 1 is definitely not supported for Xe2 and later
> -	 * platforms.  In theory it could be a valid setting for pre-Xe2
> -	 * platforms, but there's no documentation on how to properly handle
> -	 * this case.  Reading TIMESTAMP_OVERRIDE, as the driver attempted in
> -	 * the past has been confirmed as incorrect by the hardware architects.
> -	 *
> -	 * For now just warn if we ever encounter hardware in the wild that
> -	 * has this setting and move on as if it hadn't been set.
> -	 */
> -	if (xe_mmio_read32(&gt->mmio, CTC_MODE) & CTC_SOURCE_DIVIDE_LOGIC)
> -		xe_gt_warn(gt, "CTC_MODE[0] is set; this is unexpected and undocumented\n");
> -}
> -
>  int xe_gt_clock_init(struct xe_gt *gt)
>  {
>  	u32 freq;
>  	u32 c0;
>  
> -	if (!IS_SRIOV_VF(gt_to_xe(gt)))
> -		check_ctc_mode(gt);
> -
>  	c0 = xe_mmio_read32(&gt->mmio, RPM_CONFIG0);
>  	read_crystal_clock(gt, c0, &freq, &gt->info.timestamp_base);
>  
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v2 09/22] drm/xe: Dump CURRENT_LRCA register

[Matt Roper]

On Wed, Oct 15, 2025 at 03:06:24PM -0700, Lucas De Marchi wrote:
> From: Wang Xin <x.wang@intel.com>
> 
> Add CURRENT_LRCA to register dump to help debugging.
> 
> Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Wang Xin <x.wang@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> v2: Extract CURRENT_LRCA from other patch dumping xe3p-specific register
>     (Matt Roper)
> ---
>  drivers/gpu/drm/xe/regs/xe_engine_regs.h | 3 +++
>  drivers/gpu/drm/xe/xe_guc_capture.c      | 1 +
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index f4c3e1187a00a..3c05d85902c69 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -141,6 +141,9 @@
>  #define   INHIBIT_SWITCH_UNTIL_PREEMPTED	REG_BIT(31)
>  #define   IDLE_DELAY				REG_GENMASK(20, 0)
>  
> +#define RING_CURRENT_LRCA(base)			XE_REG((base) + 0x240)
> +#define   CURRENT_LRCA_VALID			REG_BIT(0)

We only need the register definition itself for now.  We can define bit0
down the road if/when some patch actually wants to start using it.

Aside from that,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> +
>  #define RING_CONTEXT_CONTROL(base)		XE_REG((base) + 0x244, XE_REG_OPTION_MASKED)
>  #define	  CTX_CTRL_PXP_ENABLE			REG_BIT(10)
>  #define	  CTX_CTRL_OAC_CONTEXT_ENABLE		REG_BIT(8)
> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
> index 243dad3e24185..8d1bfa2cdb151 100644
> --- a/drivers/gpu/drm/xe/xe_guc_capture.c
> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c
> @@ -122,6 +122,7 @@ struct __guc_capture_parsed_output {
>  	{ RING_IPEHR(0),		REG_32BIT,	0,	0,	0,	"IPEHR"}, \
>  	{ RING_INSTDONE(0),		REG_32BIT,	0,	0,	0,	"RING_INSTDONE"}, \
>  	{ INDIRECT_RING_STATE(0),	REG_32BIT,	0,	0,	0,	"INDIRECT_RING_STATE"}, \
> +	{ RING_CURRENT_LRCA(0),		REG_32BIT,	0,	0,	0,	"CURRENT_LRCA"}, \
>  	{ RING_ACTHD(0),		REG_64BIT_LOW_DW, 0,	0,	0,	NULL}, \
>  	{ RING_ACTHD_UDW(0),		REG_64BIT_HI_DW, 0,	0,	0,	"ACTHD"}, \
>  	{ RING_BBADDR(0),		REG_64BIT_LOW_DW, 0,	0,	0,	NULL}, \
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v2 15/22] drm/xe/xe3p_xpc: Add L3 bank mask

[Matt Roper]

On Wed, Oct 15, 2025 at 03:06:30PM -0700, Lucas De Marchi wrote:
> From: Fei Yang <fei.yang@intel.com>
> 
> Expose L3 bank mask through topology query interface.
> 
> In Xe3p_XPC, MIRROR_L3BANK_ENABLE represents the full L3 bank mask (not
> just a per-node mask), and each bit represents a single bank. With that
> there's no extra complexity to calculate the L3 bank mask like there was
> in previous platforms.
> 
> Bspec: 73439
> Signed-off-by: Fei Yang <fei.yang@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
> v2: Better commit message (Matt Roper)
> ---
>  drivers/gpu/drm/xe/xe_gt_topology.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
> index 80ef3a6e0a3b5..14af073783ad3 100644
> --- a/drivers/gpu/drm/xe/xe_gt_topology.c
> +++ b/drivers/gpu/drm/xe/xe_gt_topology.c
> @@ -148,7 +148,11 @@ load_l3_bank_mask(struct xe_gt *gt, xe_l3_bank_mask_t l3_bank_mask)
>  	if (!xe_gt_topology_report_l3(gt))
>  		return;
>  
> -	if (GRAPHICS_VER(xe) >= 30) {
> +	if (GRAPHICS_VERx100(xe) == 3511) {
> +		u32 fuse_val = xe_mmio_read32(mmio, MIRROR_L3BANK_ENABLE);
> +
> +		bitmap_from_arr32(l3_bank_mask, &fuse_val, 32);
> +	} else if (GRAPHICS_VER(xe) >= 30) {
>  		xe_l3_bank_mask_t per_node = {};
>  		u32 meml3_en = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, fuse3);
>  		u32 mirror_l3bank_enable = xe_mmio_read32(mmio, MIRROR_L3BANK_ENABLE);
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v2 10/22] drm/xe/xe3p: Dump CSMQDEBUG register

[Matt Roper]

On Wed, Oct 15, 2025 at 03:06:25PM -0700, Lucas De Marchi wrote:
> From: Wang Xin <x.wang@intel.com>
> 
> The CSMQDEBUG is useful for the development of MQ feature. Start dumping
> the debug register.
> 
> Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Wang Xin <x.wang@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> v2:
>  - Extract CSMQDEBUG from other patch dumping multiple register (Matt
>    Roper)
>  - Simplify version check (Matt Roper)
>  - Do not dump CSMQDEBUG for engines that do not support MQ (Matt Roper)
> ---
>  drivers/gpu/drm/xe/regs/xe_engine_regs.h |  2 ++
>  drivers/gpu/drm/xe/xe_guc_capture.c      | 48 +++++++++++++++++++++++++++++++-
>  2 files changed, 49 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index 3c05d85902c69..7b6ec0cf78c85 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -156,6 +156,8 @@
>  #define   GFX_DISABLE_LEGACY_MODE		REG_BIT(3)
>  #define   GFX_MSIX_INTERRUPT_ENABLE		REG_BIT(13)
>  
> +#define RING_CSMQDEBUG(base)			XE_REG((base) + 0x2b0)
> +
>  #define RING_TIMESTAMP(base)			XE_REG((base) + 0x358)
>  
>  #define RING_TIMESTAMP_UDW(base)		XE_REG((base) + 0x358 + 4)
> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
> index 8d1bfa2cdb151..035b9b6c0df58 100644
> --- a/drivers/gpu/drm/xe/xe_guc_capture.c
> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c
> @@ -150,6 +150,9 @@ struct __guc_capture_parsed_output {
>  	{ SFC_DONE(2),			0,	0,	0,	0,	"SFC_DONE[2]"}, \
>  	{ SFC_DONE(3),			0,	0,	0,	0,	"SFC_DONE[3]"}
>  
> +#define XE3P_BASE_ENGINE_INSTANCE \
> +	{ RING_CSMQDEBUG(0),		REG_32BIT,	0,	0,	0,	"CSMQDEBUG"}
> +
>  /* XE_LP Global */
>  static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = {
>  	COMMON_XELP_BASE_GLOBAL,
> @@ -196,6 +199,32 @@ static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = {
>  	COMMON_BASE_ENGINE_INSTANCE,
>  };
>  
> +/* Render / Compute Per-Engine-Instance */
> +static const struct __guc_mmio_reg_descr xe3p_rc_inst_regs[] = {
> +	COMMON_BASE_ENGINE_INSTANCE,
> +	XE3P_BASE_ENGINE_INSTANCE,
> +};
> +
> +/* Media Decode/Encode Per-Engine-Instance */
> +static const struct __guc_mmio_reg_descr xe3p_vd_inst_regs[] = {
> +	COMMON_BASE_ENGINE_INSTANCE,
> +};

We can skip xe3p definitions for vd / ve / blt / gsc and just re-use the
existing definitions like xe_vd_inst_regs[] as we have on past
platforms.  We only need new platform-specific tables when we're adding
something new that's different from the previous platforms.


Matt

> +
> +/* Video Enhancement Per-Engine-Instance */
> +static const struct __guc_mmio_reg_descr xe3p_vec_inst_regs[] = {
> +	COMMON_BASE_ENGINE_INSTANCE,
> +};
> +
> +/* Blitter Per-Engine-Instance */
> +static const struct __guc_mmio_reg_descr xe3p_blt_inst_regs[] = {
> +	COMMON_BASE_ENGINE_INSTANCE,
> +};
> +
> +/* XE3P - GSC Per-Engine-Instance */
> +static const struct __guc_mmio_reg_descr xe3p_gsc_inst_regs[] = {
> +	COMMON_BASE_ENGINE_INSTANCE,
> +};
> +
>  /*
>   * Empty list to prevent warnings about unknown class/instance types
>   * as not all class/instance types have entries on all platforms.
> @@ -246,6 +275,21 @@ static const struct __guc_mmio_reg_descr_group xe_hpg_lists[] = {
>  	{}
>  };
>  
> + /* List of lists for Xe3p and beyond */
> +static const struct __guc_mmio_reg_descr_group xe3p_lists[] = {
> +	MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0),
> +	MAKE_REGLIST(xe_hpg_rc_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
> +	MAKE_REGLIST(xe3p_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
> +	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO),
> +	MAKE_REGLIST(xe3p_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO),
> +	MAKE_REGLIST(xe_vec_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
> +	MAKE_REGLIST(xe3p_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
> +	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER),
> +	MAKE_REGLIST(xe3p_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
> +	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
> +	MAKE_REGLIST(xe3p_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
> +	{}
> +};
>  static const char * const capture_list_type_names[] = {
>  	"Global",
>  	"Class",
> @@ -293,7 +337,9 @@ guc_capture_remove_stale_matches_from_list(struct xe_guc_state_capture *gc,
>  static const struct __guc_mmio_reg_descr_group *
>  guc_capture_get_device_reglist(struct xe_device *xe)
>  {
> -	if (GRAPHICS_VERx100(xe) >= 1255)
> +	if (GRAPHICS_VER(xe) >= 35)
> +		return xe3p_lists;
> +	else if (GRAPHICS_VERx100(xe) >= 1255)
>  		return xe_hpg_lists;
>  	else
>  		return xe_lp_lists;
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v2 04/22] drm/xe: Add GT_VER() to check version specific to gt type

[Matt Roper]

On Wed, Oct 15, 2025 at 03:06:19PM -0700, Lucas De Marchi wrote:
> In some situations we will need to check the version of the specific gt
> being passed as argument, not if the device has a certain graphics/media
> version.
> 
> This is extracted from a patch by Balasubramani Vivekanandan that
> may need some rework, but this helper is still useful for other enabling
> parts of Xe3p.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_gt.h | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h
> index 5df2ffe3ff838..9d710049da455 100644
> --- a/drivers/gpu/drm/xe/xe_gt.h
> +++ b/drivers/gpu/drm/xe/xe_gt.h
> @@ -22,6 +22,12 @@
>  
>  #define CCS_MASK(gt) (((gt)->info.engine_mask & XE_HW_ENGINE_CCS_MASK) >> XE_HW_ENGINE_CCS0)
>  
> +#define GT_VER(gt) ({ \
> +	typeof(gt) gt_ = (gt); \
> +	struct xe_device *xe = gt_to_xe(gt_); \
> +	xe_gt_is_media_type(gt_) ? MEDIA_VER(xe) : GRAPHICS_VER(xe); \
> +})
> +
>  extern struct fault_attr gt_reset_failure;
>  static inline bool xe_fault_inject_gt_reset(void)
>  {
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v2 17/22] drm/xe/irq: Rename fuse mask variables

[Matt Roper]

On Wed, Oct 15, 2025 at 03:06:32PM -0700, Lucas De Marchi wrote:
> It's confusing to refer to some masks as the interrupt masks and others
> as the fuse masks. Rename the fuse one to make it clearer.
> 
> Note that the most important role they play here is that the call
> to xe_hw_engine_mask_per_class() will not only limit the engines
> according to the fuses, but also by what is available in the specific
> architecture - the latter is more important information to know what
> interrupts should be enabled. Add a comment about that.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_irq.c | 30 ++++++++++++++++++------------
>  1 file changed, 18 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 838fb512b7779..9c3a85c4585ed 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -139,7 +139,6 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>  {
>  	struct xe_device *xe = gt_to_xe(gt);
>  	struct xe_mmio *mmio = &gt->mmio;
> -	u32 ccs_mask, bcs_mask;
>  	u32 irqs, dmask, smask;
>  	u32 gsc_mask = 0;
>  	u32 heci_mask = 0;
> @@ -157,36 +156,43 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>  		       GT_WAIT_SEMAPHORE_INTERRUPT;
>  	}
>  
> -	ccs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
> -	bcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
> -
>  	dmask = irqs << 16 | irqs;
>  	smask = irqs << 16;
>  
>  	if (xe_gt_is_main_type(gt)) {
> +		/*
> +		 * For enabling the interrupts, the information about fused off
> +		 * engines doesn't matter much, but this also allows to check if
> +		 * the engine is available architecturally in the platform
> +		 */
> +		u32 ccs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
> +		u32 bcs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
> +
>  		/* Enable interrupts for each engine class */
>  		xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, dmask);
> -		if (ccs_mask)
> +		if (ccs_fuse_mask)
>  			xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, smask);
>  
>  		/* Unmask interrupts for each engine instance */
>  		xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~smask);
>  		xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~smask);
> -		if (bcs_mask & (BIT(1)|BIT(2)))
> +		if (bcs_fuse_mask & (BIT(1)|BIT(2)))
>  			xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
> -		if (bcs_mask & (BIT(3)|BIT(4)))
> +		if (bcs_fuse_mask & (BIT(3)|BIT(4)))
>  			xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
> -		if (bcs_mask & (BIT(5)|BIT(6)))
> +		if (bcs_fuse_mask & (BIT(5)|BIT(6)))
>  			xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
> -		if (bcs_mask & (BIT(7)|BIT(8)))
> +		if (bcs_fuse_mask & (BIT(7)|BIT(8)))
>  			xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
> -		if (ccs_mask & (BIT(0)|BIT(1)))
> +		if (ccs_fuse_mask & (BIT(0)|BIT(1)))
>  			xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~dmask);
> -		if (ccs_mask & (BIT(2)|BIT(3)))
> +		if (ccs_fuse_mask & (BIT(2)|BIT(3)))
>  			xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~dmask);
>  	}
>  
>  	if (xe_gt_is_media_type(gt) || MEDIA_VER(xe) < 13) {
> +		u32 other_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER);
> +
>  		/* Enable interrupts for each engine class */
>  		xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, dmask);
>  
> @@ -199,7 +205,7 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>  		 * the heci2 interrupt is enabled via the same register as the
>  		 * GSCCS interrupts, but it has its own mask register.
>  		 */
> -		if (xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER)) {
> +		if (other_fuse_mask) {
>  			gsc_mask = irqs | GSC_ER_COMPLETE;
>  			heci_mask = GSC_IRQ_INTF(1);
>  		} else if (xe->info.has_heci_gscfi) {
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v2 18/22] drm/xe/irq: Split irq mask per engine class

[Matt Roper]

On Wed, Oct 15, 2025 at 03:06:33PM -0700, Lucas De Marchi wrote:
> Each engine class has a different bitfield structure in the hw. We've
> been just using a common mask for all of them, but this means that we
> could inadvertently set a wrong bit in one class while enabling
> something in another. Split them to make it more future proof.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_irq.c | 73 +++++++++++++++++++++++++++++----------------
>  1 file changed, 47 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 9c3a85c4585ed..103804546b280 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -139,25 +139,28 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>  {
>  	struct xe_device *xe = gt_to_xe(gt);
>  	struct xe_mmio *mmio = &gt->mmio;
> -	u32 irqs, dmask, smask;
> -	u32 gsc_mask = 0;
> -	u32 heci_mask = 0;
> +	u32 common_mask, val, gsc_mask = 0, heci_mask = 0,
> +	    rcs_mask = 0, bcs_mask = 0, vcs_mask = 0, vecs_mask = 0,
> +	    ccs_mask = 0;
>  
>  	if (xe_device_uses_memirq(xe))
>  		return;
>  
>  	if (xe_device_uc_enabled(xe)) {
> -		irqs = GT_RENDER_USER_INTERRUPT |
> -			GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
> +		common_mask = GT_RENDER_USER_INTERRUPT |

As a follow-up patch, this should probably be renamed to
GT_MI_USER_INTERRUPT since it doesn't have anything to do with render
these days (I think once upon a time this interrupts was only supported
on the RCS, but it's supported everywhere on all the platforms Xe
supports).

> +			      GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;

This one will probably need a rename too.  The purpose is the same on
all engines (indicate that a flush command has finished), but the actual
flush command differs between engines...PIPECTL is only on rcs/ccs, and
MI_FLUSH_DW is used on the other engines.  So maybe
GT_FLUSH_COMPLETE_INTERRUPT or similar would be more accurate.

>  	} else {
> -		irqs = GT_RENDER_USER_INTERRUPT |
> -		       GT_CS_MASTER_ERROR_INTERRUPT |
> -		       GT_CONTEXT_SWITCH_INTERRUPT |
> -		       GT_WAIT_SEMAPHORE_INTERRUPT;
> +		common_mask = GT_RENDER_USER_INTERRUPT |
> +			      GT_CS_MASTER_ERROR_INTERRUPT |
> +			      GT_CONTEXT_SWITCH_INTERRUPT |
> +			      GT_WAIT_SEMAPHORE_INTERRUPT;
>  	}
>  
> -	dmask = irqs << 16 | irqs;
> -	smask = irqs << 16;
> +	rcs_mask |= common_mask;
> +	bcs_mask |= common_mask;
> +	vcs_mask |= common_mask;
> +	vecs_mask |= common_mask;
> +	ccs_mask |= common_mask;
>  
>  	if (xe_gt_is_main_type(gt)) {
>  		/*
> @@ -169,44 +172,62 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>  		u32 bcs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
>  
>  		/* Enable interrupts for each engine class */
> -		xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, dmask);
> +		xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE,
> +				REG_FIELD_PREP(ENGINE1_MASK, rcs_mask) |
> +				REG_FIELD_PREP(ENGINE0_MASK, bcs_mask));
>  		if (ccs_fuse_mask)
> -			xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, smask);
> +			xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE,
> +					REG_FIELD_PREP(ENGINE1_MASK, ccs_mask));
>  
>  		/* Unmask interrupts for each engine instance */
> -		xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~smask);
> -		xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~smask);
> +		val = ~REG_FIELD_PREP(ENGINE1_MASK, rcs_mask);
> +		xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, val);
> +		val = ~REG_FIELD_PREP(ENGINE1_MASK, bcs_mask);
> +		xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, val);
> +
> +		val = ~(REG_FIELD_PREP(ENGINE1_MASK, bcs_mask) |
> +			REG_FIELD_PREP(ENGINE0_MASK, bcs_mask));
>  		if (bcs_fuse_mask & (BIT(1)|BIT(2)))
> -			xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
> +			xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, val);
>  		if (bcs_fuse_mask & (BIT(3)|BIT(4)))
> -			xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
> +			xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, val);
>  		if (bcs_fuse_mask & (BIT(5)|BIT(6)))
> -			xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
> +			xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, val);
>  		if (bcs_fuse_mask & (BIT(7)|BIT(8)))
> -			xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
> +			xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, val);
> +
> +		val = ~(REG_FIELD_PREP(ENGINE1_MASK, ccs_mask) |
> +			REG_FIELD_PREP(ENGINE0_MASK, ccs_mask));
>  		if (ccs_fuse_mask & (BIT(0)|BIT(1)))
> -			xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~dmask);
> +			xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, val);
>  		if (ccs_fuse_mask & (BIT(2)|BIT(3)))
> -			xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~dmask);
> +			xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, val);
>  	}
>  
>  	if (xe_gt_is_media_type(gt) || MEDIA_VER(xe) < 13) {
>  		u32 other_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER);
>  
>  		/* Enable interrupts for each engine class */
> -		xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, dmask);
> +		xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE,
> +				REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
> +				REG_FIELD_PREP(ENGINE1_MASK, vecs_mask));
>  
>  		/* Unmask interrupts for each engine instance */

As a follow-up, we should probably add vcs_fuse_mask / vecs_fuse_mask
checks for these, and also handle the rest of the engines up to VCS7 and
VECS3 (since we have all of those in media_xelpmp's descriptor).

> -		xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~dmask);
> -		xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~dmask);
> -		xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~dmask);
> +		val = ~(REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
> +			REG_FIELD_PREP(ENGINE0_MASK, vcs_mask));
> +		xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, val);
> +		xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, val);
> +
> +		val = ~(REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
> +			REG_FIELD_PREP(ENGINE0_MASK, vcs_mask));

Was this one supposed to be using vecs_mask?


Matt

> +		xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, val);
>  
>  		/*
>  		 * the heci2 interrupt is enabled via the same register as the
>  		 * GSCCS interrupts, but it has its own mask register.
>  		 */
>  		if (other_fuse_mask) {
> -			gsc_mask = irqs | GSC_ER_COMPLETE;
> +			gsc_mask = common_mask | GSC_ER_COMPLETE;
>  			heci_mask = GSC_IRQ_INTF(1);
>  		} else if (xe->info.has_heci_gscfi) {
>  			gsc_mask = GSC_IRQ_INTF(1);
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v2 22/22] drm/xe/xe3p: Add xe3p EU stall data format

[Dixit, Ashutosh]

On Wed, 15 Oct 2025 15:06:37 -0700, Lucas De Marchi wrote:
>
> From: Harish Chegondi <harish.chegondi@intel.com>
>
> Starting with Xe3p, IP address in EU stall data increases to 61 bits.
> While at it, re-order the if-else ladder so the officially supported
> platforms come before PVC.
>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> v2: reorder the if-else ladder so PVC is the last (Lucas)

Don't we want to commit the version log as part of the patch?

In any case, this is:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>


>
> TODO: double check data format as it's missing from bspec
> ---
>  drivers/gpu/drm/xe/xe_eu_stall.c | 28 ++++++++++++++++++++++++++--
>  1 file changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
> index f5cfdf29fde34..650e45f6a7c7e 100644
> --- a/drivers/gpu/drm/xe/xe_eu_stall.c
> +++ b/drivers/gpu/drm/xe/xe_eu_stall.c
> @@ -124,6 +124,27 @@ struct xe_eu_stall_data_xe2 {
>	__u64 unused[6];
>  } __packed;
>
> +/*
> + * EU stall data format for Xe3p arch GPUs.
> + */
> +struct xe_eu_stall_data_xe3p {
> +	__u64 ip_addr:61;	  /* Bits 0  to 60  */
> +	__u64 tdr_count:8;	  /* Bits 61 to 68  */
> +	__u64 other_count:8;	  /* Bits 69 to 76  */
> +	__u64 control_count:8;	  /* Bits 77 to 84  */
> +	__u64 pipestall_count:8;  /* Bits 85 to 92  */
> +	__u64 send_count:8;	  /* Bits 93 to 100 */
> +	__u64 dist_acc_count:8;   /* Bits 101 to 108 */
> +	__u64 sbid_count:8;	  /* Bits 109 to 116 */
> +	__u64 sync_count:8;	  /* Bits 117 to 124 */
> +	__u64 inst_fetch_count:8; /* Bits 125 to 132 */
> +	__u64 active_count:8;	  /* Bits 133 to 140 */
> +	__u64 ex_id:3;		  /* Bits 141 to 143 */
> +	__u64 end_flag:1;	  /* Bit  144 */
> +	__u64 unused_bits:47;
> +	__u64 unused[5];
> +} __packed;
> +
>  const u64 eu_stall_sampling_rates[] = {251, 251 * 2, 251 * 3, 251 * 4, 251 * 5, 251 * 6, 251 * 7};
>
>  /**
> @@ -167,10 +188,13 @@ size_t xe_eu_stall_data_record_size(struct xe_device *xe)
>  {
>	size_t record_size = 0;
>
> -	if (xe->info.platform == XE_PVC)
> -		record_size = sizeof(struct xe_eu_stall_data_pvc);
> +	if (GRAPHICS_VER(xe) >= 35)
> +		record_size = sizeof(struct xe_eu_stall_data_xe3p);
>	else if (GRAPHICS_VER(xe) >= 20)
>		record_size = sizeof(struct xe_eu_stall_data_xe2);
> +	else if (xe->info.platform == XE_PVC)
> +		record_size = sizeof(struct xe_eu_stall_data_pvc);
> +
>
>	xe_assert(xe, is_power_of_2(record_size));
>
>
> --
> 2.51.0
>

Re: [PATCH v2 19/22] drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx

[Matt Roper]

On Wed, Oct 15, 2025 at 03:06:34PM -0700, Lucas De Marchi wrote:
> Current implementation of compute walker has dependency on GPU/SW Stack
> which requires SW/UMD to wait for event from KMD to indicate
> PIPE_CONTROL interrupt was done. This created latency on SW stack.
> 
> This feature adds support to generate completion interrupt from GPGPU
> walker which does not support MSIx and avoid software using Pipe control
> drain/idle latency.
> 
> Suggested-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> Signed-off-by: S A Muqthyar Ahmed <syed.abdul.muqthyar.ahmed@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> v2: Rebase on split mask per engine class
> ---
>  drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
>  drivers/gpu/drm/xe/xe_irq.c           | 6 ++++++
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> index 7c2a3a1401424..9c46b5fb81412 100644
> --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> @@ -82,6 +82,7 @@
>  #define   GSC_ER_COMPLETE			REG_BIT(5)
>  #define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)
>  #define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
> +#define   GT_COMPUTE_WALKER_INTERRUPT		REG_BIT(2)
>  #define   GT_RENDER_USER_INTERRUPT		REG_BIT(0)
>  
>  /* irqs for OTHER_KCR_INSTANCE */
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 103804546b280..ac5524cbe4b9a 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -149,6 +149,12 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>  	if (xe_device_uc_enabled(xe)) {
>  		common_mask = GT_RENDER_USER_INTERRUPT |
>  			      GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
> +
> +		/* Enable Compute Walker Interrupt for non-MSIX platforms */
> +		if (GRAPHICS_VERx100(xe) >= 3511 && !xe_device_has_msix(xe)) {
> +			rcs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
> +			ccs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
> +		}

It probably doesn't matter since our execlist support isn't functional
and we only really support GuC-based submission, but technically
shouldn't this be outside the 'uc_enabled' check so that we'd also get
these interrupts if we tried to use execlist submission?

BTW, is there more support for this coming in future patches?  Without
MSI-X, what's the mechanism by which userspace finds out this interrupt
has fired?  We're unmasking/enabling the interrupt here, but I don't see
how anything happens once the interrupts start showing up.


Matt

>  	} else {
>  		common_mask = GT_RENDER_USER_INTERRUPT |
>  			      GT_CS_MASTER_ERROR_INTERRUPT |
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v2 22/22] drm/xe/xe3p: Add xe3p EU stall data format

[Lucas De Marchi]

On Wed, Oct 15, 2025 at 04:58:52PM -0700, Ashutosh Dixit wrote:
>On Wed, 15 Oct 2025 15:06:37 -0700, Lucas De Marchi wrote:
>>
>> From: Harish Chegondi <harish.chegondi@intel.com>
>>
>> Starting with Xe3p, IP address in EU stall data increases to 61 bits.
>> While at it, re-order the if-else ladder so the officially supported
>> platforms come before PVC.
>>
>> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
>> Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> v2: reorder the if-else ladder so PVC is the last (Lucas)
>
>Don't we want to commit the version log as part of the patch?

I don't want, no. It's something we've did even if the general kernel
doc says we shouldn't be doing: https://docs.kernel.org/process/submitting-patches.html#commentary
I'd say it's good if people stop doing it in xe, particularly when they
start to contribute to other areas of the kernel, so they don't get
another barrier to get their contributions accepted.

>
>In any case, this is:
>
>Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

thanks
Lucas De Marchi

>
>
>>
>> TODO: double check data format as it's missing from bspec
>> ---
>>  drivers/gpu/drm/xe/xe_eu_stall.c | 28 ++++++++++++++++++++++++++--
>>  1 file changed, 26 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
>> index f5cfdf29fde34..650e45f6a7c7e 100644
>> --- a/drivers/gpu/drm/xe/xe_eu_stall.c
>> +++ b/drivers/gpu/drm/xe/xe_eu_stall.c
>> @@ -124,6 +124,27 @@ struct xe_eu_stall_data_xe2 {
>>	__u64 unused[6];
>>  } __packed;
>>
>> +/*
>> + * EU stall data format for Xe3p arch GPUs.
>> + */
>> +struct xe_eu_stall_data_xe3p {
>> +	__u64 ip_addr:61;	  /* Bits 0  to 60  */
>> +	__u64 tdr_count:8;	  /* Bits 61 to 68  */
>> +	__u64 other_count:8;	  /* Bits 69 to 76  */
>> +	__u64 control_count:8;	  /* Bits 77 to 84  */
>> +	__u64 pipestall_count:8;  /* Bits 85 to 92  */
>> +	__u64 send_count:8;	  /* Bits 93 to 100 */
>> +	__u64 dist_acc_count:8;   /* Bits 101 to 108 */
>> +	__u64 sbid_count:8;	  /* Bits 109 to 116 */
>> +	__u64 sync_count:8;	  /* Bits 117 to 124 */
>> +	__u64 inst_fetch_count:8; /* Bits 125 to 132 */
>> +	__u64 active_count:8;	  /* Bits 133 to 140 */
>> +	__u64 ex_id:3;		  /* Bits 141 to 143 */
>> +	__u64 end_flag:1;	  /* Bit  144 */
>> +	__u64 unused_bits:47;
>> +	__u64 unused[5];
>> +} __packed;
>> +
>>  const u64 eu_stall_sampling_rates[] = {251, 251 * 2, 251 * 3, 251 * 4, 251 * 5, 251 * 6, 251 * 7};
>>
>>  /**
>> @@ -167,10 +188,13 @@ size_t xe_eu_stall_data_record_size(struct xe_device *xe)
>>  {
>>	size_t record_size = 0;
>>
>> -	if (xe->info.platform == XE_PVC)
>> -		record_size = sizeof(struct xe_eu_stall_data_pvc);
>> +	if (GRAPHICS_VER(xe) >= 35)
>> +		record_size = sizeof(struct xe_eu_stall_data_xe3p);
>>	else if (GRAPHICS_VER(xe) >= 20)
>>		record_size = sizeof(struct xe_eu_stall_data_xe2);
>> +	else if (xe->info.platform == XE_PVC)
>> +		record_size = sizeof(struct xe_eu_stall_data_pvc);
>> +
>>
>>	xe_assert(xe, is_power_of_2(record_size));
>>
>>
>> --
>> 2.51.0
>>

Re: [PATCH v2 18/22] drm/xe/irq: Split irq mask per engine class

[Lucas De Marchi]

On Wed, Oct 15, 2025 at 04:52:00PM -0700, Matt Roper wrote:
>On Wed, Oct 15, 2025 at 03:06:33PM -0700, Lucas De Marchi wrote:
>> Each engine class has a different bitfield structure in the hw. We've
>> been just using a common mask for all of them, but this means that we
>> could inadvertently set a wrong bit in one class while enabling
>> something in another. Split them to make it more future proof.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/xe/xe_irq.c | 73 +++++++++++++++++++++++++++++----------------
>>  1 file changed, 47 insertions(+), 26 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>> index 9c3a85c4585ed..103804546b280 100644
>> --- a/drivers/gpu/drm/xe/xe_irq.c
>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>> @@ -139,25 +139,28 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>>  {
>>  	struct xe_device *xe = gt_to_xe(gt);
>>  	struct xe_mmio *mmio = &gt->mmio;
>> -	u32 irqs, dmask, smask;
>> -	u32 gsc_mask = 0;
>> -	u32 heci_mask = 0;
>> +	u32 common_mask, val, gsc_mask = 0, heci_mask = 0,
>> +	    rcs_mask = 0, bcs_mask = 0, vcs_mask = 0, vecs_mask = 0,
>> +	    ccs_mask = 0;
>>
>>  	if (xe_device_uses_memirq(xe))
>>  		return;
>>
>>  	if (xe_device_uc_enabled(xe)) {
>> -		irqs = GT_RENDER_USER_INTERRUPT |
>> -			GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
>> +		common_mask = GT_RENDER_USER_INTERRUPT |
>
>As a follow-up patch, this should probably be renamed to
>GT_MI_USER_INTERRUPT since it doesn't have anything to do with render
>these days (I think once upon a time this interrupts was only supported
>on the RCS, but it's supported everywhere on all the platforms Xe
>supports).

from bspec:

	- rcs: CS MI User Interrupt
	- vcs: MI User Interrupt
	- vecs: MI User Interrupt
	- blt: MI User Interrupt
	- gcs: MI User Interrupt

yeah so GT_MI_USER_INTERRUPT seems a good common name.

>
>> +			      GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
>
>This one will probably need a rename too.  The purpose is the same on
>all engines (indicate that a flush command has finished), but the actual
>flush command differs between engines...PIPECTL is only on rcs/ccs, and
>MI_FLUSH_DW is used on the other engines.  So maybe
>GT_FLUSH_COMPLETE_INTERRUPT or similar would be more accurate.

ack

Adding a commit with these renames on next version

>
>>  	} else {
>> -		irqs = GT_RENDER_USER_INTERRUPT |
>> -		       GT_CS_MASTER_ERROR_INTERRUPT |
>> -		       GT_CONTEXT_SWITCH_INTERRUPT |
>> -		       GT_WAIT_SEMAPHORE_INTERRUPT;
>> +		common_mask = GT_RENDER_USER_INTERRUPT |
>> +			      GT_CS_MASTER_ERROR_INTERRUPT |
>> +			      GT_CONTEXT_SWITCH_INTERRUPT |
>> +			      GT_WAIT_SEMAPHORE_INTERRUPT;
>>  	}
>>
>> -	dmask = irqs << 16 | irqs;
>> -	smask = irqs << 16;
>> +	rcs_mask |= common_mask;
>> +	bcs_mask |= common_mask;
>> +	vcs_mask |= common_mask;
>> +	vecs_mask |= common_mask;
>> +	ccs_mask |= common_mask;
>>
>>  	if (xe_gt_is_main_type(gt)) {
>>  		/*
>> @@ -169,44 +172,62 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>>  		u32 bcs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
>>
>>  		/* Enable interrupts for each engine class */
>> -		xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, dmask);
>> +		xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE,
>> +				REG_FIELD_PREP(ENGINE1_MASK, rcs_mask) |
>> +				REG_FIELD_PREP(ENGINE0_MASK, bcs_mask));
>>  		if (ccs_fuse_mask)
>> -			xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, smask);
>> +			xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE,
>> +					REG_FIELD_PREP(ENGINE1_MASK, ccs_mask));
>>
>>  		/* Unmask interrupts for each engine instance */
>> -		xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~smask);
>> -		xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~smask);
>> +		val = ~REG_FIELD_PREP(ENGINE1_MASK, rcs_mask);
>> +		xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, val);
>> +		val = ~REG_FIELD_PREP(ENGINE1_MASK, bcs_mask);
>> +		xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, val);
>> +
>> +		val = ~(REG_FIELD_PREP(ENGINE1_MASK, bcs_mask) |
>> +			REG_FIELD_PREP(ENGINE0_MASK, bcs_mask));
>>  		if (bcs_fuse_mask & (BIT(1)|BIT(2)))
>> -			xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
>> +			xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, val);
>>  		if (bcs_fuse_mask & (BIT(3)|BIT(4)))
>> -			xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
>> +			xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, val);
>>  		if (bcs_fuse_mask & (BIT(5)|BIT(6)))
>> -			xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
>> +			xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, val);
>>  		if (bcs_fuse_mask & (BIT(7)|BIT(8)))
>> -			xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
>> +			xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, val);
>> +
>> +		val = ~(REG_FIELD_PREP(ENGINE1_MASK, ccs_mask) |
>> +			REG_FIELD_PREP(ENGINE0_MASK, ccs_mask));
>>  		if (ccs_fuse_mask & (BIT(0)|BIT(1)))
>> -			xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~dmask);
>> +			xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, val);
>>  		if (ccs_fuse_mask & (BIT(2)|BIT(3)))
>> -			xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~dmask);
>> +			xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, val);
>>  	}
>>
>>  	if (xe_gt_is_media_type(gt) || MEDIA_VER(xe) < 13) {
>>  		u32 other_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER);
>>
>>  		/* Enable interrupts for each engine class */
>> -		xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, dmask);
>> +		xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE,
>> +				REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
>> +				REG_FIELD_PREP(ENGINE1_MASK, vecs_mask));
>>
>>  		/* Unmask interrupts for each engine instance */
>
>As a follow-up, we should probably add vcs_fuse_mask / vecs_fuse_mask
>checks for these, and also handle the rest of the engines up to VCS7 and
>VECS3 (since we have all of those in media_xelpmp's descriptor).

queued this change for the next version as well.

>
>> -		xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~dmask);
>> -		xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~dmask);
>> -		xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~dmask);
>> +		val = ~(REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
>> +			REG_FIELD_PREP(ENGINE0_MASK, vcs_mask));
>> +		xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, val);
>> +		xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, val);
>> +
>> +		val = ~(REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
>> +			REG_FIELD_PREP(ENGINE0_MASK, vcs_mask));
>
>Was this one supposed to be using vecs_mask?

yes, thanks. A few lines above there was also a ENGINE1_MASK when it
should be ENGINE0_MASK. I'm fixing those for next version.


thanks
Lucas De Marchi

>
>
>Matt
>
>> +		xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, val);
>>
>>  		/*
>>  		 * the heci2 interrupt is enabled via the same register as the
>>  		 * GSCCS interrupts, but it has its own mask register.
>>  		 */
>>  		if (other_fuse_mask) {
>> -			gsc_mask = irqs | GSC_ER_COMPLETE;
>> +			gsc_mask = common_mask | GSC_ER_COMPLETE;
>>  			heci_mask = GSC_IRQ_INTF(1);
>>  		} else if (xe->info.has_heci_gscfi) {
>>  			gsc_mask = GSC_IRQ_INTF(1);
>>
>> --
>> 2.51.0
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

✗ CI.checkpatch: warning for drm/xe: Add Xe3p support (rev2)

[Patchwork]

== Series Details ==

Series: drm/xe: Add Xe3p support (rev2)
URL   : https://patchwork.freedesktop.org/series/155866/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
fbd08a78c3a3bb17964db2a326514c69c1dca660
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit cc1e064d3414570352f3157cac1c812619efbddc
Author: Harish Chegondi <harish.chegondi@intel.com>
Date:   Wed Oct 15 15:06:37 2025 -0700

    drm/xe/xe3p: Add xe3p EU stall data format
    
    Starting with Xe3p, IP address in EU stall data increases to 61 bits.
    While at it, re-order the if-else ladder so the officially supported
    platforms come before PVC.
    
    Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
    Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
    Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
    Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
+ /mt/dim checkpatch 7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8 drm-intel
f6ac43df53a6 drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05
-:46: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#46: FILE: drivers/gpu/drm/xe/xe_wa.c:698:
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3003, 3005), FUNC(xe_rtp_match_first_render_or_compute)),

total: 0 errors, 1 warnings, 0 checks, 62 lines checked
eb23c0f2bda3 drm/xe/xe3p_lpm: Add support for media IP versions 35.00 & 35.03
4aeaa3a1549b drm/xe: Drop CTC_MODE register read
2a30fa629286 drm/xe: Add GT_VER() to check version specific to gt type
486401c310f8 drm/xe/xe3p_lpm: Skip disabling NOA on unsupported IPs
5b4a4e75ef4b drm/xe/xe3p_lpm: Handle MCR steering
75b519644def drm/xe/xe3p: Stop programming RCU_MODE's fixed slice mode setting
7083c4be2603 drm/xe/xe3p: Determine service copy availability from fuse
1d2b449b867f drm/xe: Dump CURRENT_LRCA register
72650a00582b drm/xe/xe3p: Dump CSMQDEBUG register
5d80a4c7c769 drm/xe/nvl: Define NVL-S platform
-:60: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#60: FILE: include/drm/intel/pciids.h:891:
+#define INTEL_NVLS_IDS(MACRO__, ...) \
+	MACRO__(0xD740, ## __VA_ARGS__), \
+	MACRO__(0xD741, ## __VA_ARGS__), \
+	MACRO__(0xD742, ## __VA_ARGS__), \
+	MACRO__(0xD743, ## __VA_ARGS__), \
+	MACRO__(0xD744, ## __VA_ARGS__), \
+	MACRO__(0xD745, ## __VA_ARGS__)

BUT SEE:

   do {} while (0) advice is over-stated in a few situations:

   The more obvious case is macros, like MODULE_PARM_DESC, invoked at
   file-scope, where C disallows code (it must be in functions).  See
   $exceptions if you have one to add by name.

   More troublesome is declarative macros used at top of new scope,
   like DECLARE_PER_CPU.  These might just compile with a do-while-0
   wrapper, but would be incorrect.  Most of these are handled by
   detecting struct,union,etc declaration primitives in $exceptions.

   Theres also macros called inside an if (block), which "return" an
   expression.  These cannot do-while, and need a ({}) wrapper.

   Enjoy this qualification while we work to improve our heuristics.

-:60: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#60: FILE: include/drm/intel/pciids.h:891:
+#define INTEL_NVLS_IDS(MACRO__, ...) \
+	MACRO__(0xD740, ## __VA_ARGS__), \
+	MACRO__(0xD741, ## __VA_ARGS__), \
+	MACRO__(0xD742, ## __VA_ARGS__), \
+	MACRO__(0xD743, ## __VA_ARGS__), \
+	MACRO__(0xD744, ## __VA_ARGS__), \
+	MACRO__(0xD745, ## __VA_ARGS__)

total: 1 errors, 0 warnings, 1 checks, 41 lines checked
bd5e8edb1858 drm/xe/nvls: Define GuC firmware for NVL-S
d970de823434 drm/xe/nvls: Attach MOCS table for NVL-S
dba780d0c456 drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition
a441ee392eba drm/xe/xe3p_xpc: Add L3 bank mask
d53e3b909759 drm/xe/xe3p_xpc: Add MCR steering
1047bcadca3b drm/xe/irq: Rename fuse mask variables
-:59: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#59: FILE: drivers/gpu/drm/xe/xe_irq.c:179:
+		if (bcs_fuse_mask & (BIT(1)|BIT(2)))
 		                           ^

-:62: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#62: FILE: drivers/gpu/drm/xe/xe_irq.c:181:
+		if (bcs_fuse_mask & (BIT(3)|BIT(4)))
 		                           ^

-:65: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#65: FILE: drivers/gpu/drm/xe/xe_irq.c:183:
+		if (bcs_fuse_mask & (BIT(5)|BIT(6)))
 		                           ^

-:68: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#68: FILE: drivers/gpu/drm/xe/xe_irq.c:185:
+		if (bcs_fuse_mask & (BIT(7)|BIT(8)))
 		                           ^

-:71: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#71: FILE: drivers/gpu/drm/xe/xe_irq.c:187:
+		if (ccs_fuse_mask & (BIT(0)|BIT(1)))
 		                           ^

-:74: CHECK:SPACING: spaces preferred around that '|' (ctx:VxV)
#74: FILE: drivers/gpu/drm/xe/xe_irq.c:189:
+		if (ccs_fuse_mask & (BIT(2)|BIT(3)))
 		                           ^

total: 0 errors, 0 warnings, 6 checks, 68 lines checked
83dd12b37877 drm/xe/irq: Split irq mask per engine class
072f2ffc2104 drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx
1b69abc2eaef drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs
9cd7d38b92e5 drm/xe/xe3p_xpc: Setup PAT table
-:31: ERROR:SPACING: space prohibited after that open parenthesis '('
#31: FILE: drivers/gpu/drm/xe/xe_pat.c:165:
+static const struct xe_pat_table_entry xe3p_xpc_pat_ats = XE3P_XPC_PAT( 0, 0, 0, 0, 3 );

-:31: ERROR:SPACING: space prohibited before that close parenthesis ')'
#31: FILE: drivers/gpu/drm/xe/xe_pat.c:165:
+static const struct xe_pat_table_entry xe3p_xpc_pat_ats = XE3P_XPC_PAT( 0, 0, 0, 0, 3 );

-:32: ERROR:SPACING: space prohibited after that open parenthesis '('
#32: FILE: drivers/gpu/drm/xe/xe_pat.c:166:
+static const struct xe_pat_table_entry xe3p_xpc_pat_pta = XE3P_XPC_PAT( 0, 0, 0, 0, 0 );

-:32: ERROR:SPACING: space prohibited before that close parenthesis ')'
#32: FILE: drivers/gpu/drm/xe/xe_pat.c:166:
+static const struct xe_pat_table_entry xe3p_xpc_pat_pta = XE3P_XPC_PAT( 0, 0, 0, 0, 0 );

-:35: ERROR:SPACING: space prohibited after that open square bracket '['
#35: FILE: drivers/gpu/drm/xe/xe_pat.c:169:
+	[ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ),

-:35: ERROR:SPACING: space prohibited after that open parenthesis '('
#35: FILE: drivers/gpu/drm/xe/xe_pat.c:169:
+	[ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ),

-:35: ERROR:SPACING: space prohibited before that close parenthesis ')'
#35: FILE: drivers/gpu/drm/xe/xe_pat.c:169:
+	[ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ),

-:36: ERROR:SPACING: space prohibited after that open square bracket '['
#36: FILE: drivers/gpu/drm/xe/xe_pat.c:170:
+	[ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ),

-:36: ERROR:SPACING: space prohibited after that open parenthesis '('
#36: FILE: drivers/gpu/drm/xe/xe_pat.c:170:
+	[ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ),

-:36: ERROR:SPACING: space prohibited before that close parenthesis ')'
#36: FILE: drivers/gpu/drm/xe/xe_pat.c:170:
+	[ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ),

-:37: ERROR:SPACING: space prohibited after that open square bracket '['
#37: FILE: drivers/gpu/drm/xe/xe_pat.c:171:
+	[ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ),

-:37: ERROR:SPACING: space prohibited after that open parenthesis '('
#37: FILE: drivers/gpu/drm/xe/xe_pat.c:171:
+	[ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ),

-:37: ERROR:SPACING: space prohibited before that close parenthesis ')'
#37: FILE: drivers/gpu/drm/xe/xe_pat.c:171:
+	[ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ),

-:38: ERROR:SPACING: space prohibited after that open square bracket '['
#38: FILE: drivers/gpu/drm/xe/xe_pat.c:172:
+	[ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ),

-:38: ERROR:SPACING: space prohibited after that open parenthesis '('
#38: FILE: drivers/gpu/drm/xe/xe_pat.c:172:
+	[ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ),

-:38: ERROR:SPACING: space prohibited before that close parenthesis ')'
#38: FILE: drivers/gpu/drm/xe/xe_pat.c:172:
+	[ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ),

-:39: ERROR:SPACING: space prohibited after that open square bracket '['
#39: FILE: drivers/gpu/drm/xe/xe_pat.c:173:
+	[ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ),

-:39: ERROR:SPACING: space prohibited after that open parenthesis '('
#39: FILE: drivers/gpu/drm/xe/xe_pat.c:173:
+	[ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ),

-:39: ERROR:SPACING: space prohibited before that close parenthesis ')'
#39: FILE: drivers/gpu/drm/xe/xe_pat.c:173:
+	[ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ),

-:40: ERROR:SPACING: space prohibited after that open square bracket '['
#40: FILE: drivers/gpu/drm/xe/xe_pat.c:174:
+	[ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ),

-:40: ERROR:SPACING: space prohibited after that open parenthesis '('
#40: FILE: drivers/gpu/drm/xe/xe_pat.c:174:
+	[ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ),

-:40: ERROR:SPACING: space prohibited before that close parenthesis ')'
#40: FILE: drivers/gpu/drm/xe/xe_pat.c:174:
+	[ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ),

-:41: ERROR:SPACING: space prohibited after that open square bracket '['
#41: FILE: drivers/gpu/drm/xe/xe_pat.c:175:
+	[ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ),

-:41: ERROR:SPACING: space prohibited after that open parenthesis '('
#41: FILE: drivers/gpu/drm/xe/xe_pat.c:175:
+	[ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ),

-:41: ERROR:SPACING: space prohibited before that close parenthesis ')'
#41: FILE: drivers/gpu/drm/xe/xe_pat.c:175:
+	[ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ),

-:42: ERROR:SPACING: space prohibited after that open square bracket '['
#42: FILE: drivers/gpu/drm/xe/xe_pat.c:176:
+	[ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ),

-:42: ERROR:SPACING: space prohibited after that open parenthesis '('
#42: FILE: drivers/gpu/drm/xe/xe_pat.c:176:
+	[ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ),

-:42: ERROR:SPACING: space prohibited before that close parenthesis ')'
#42: FILE: drivers/gpu/drm/xe/xe_pat.c:176:
+	[ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ),

-:43: ERROR:SPACING: space prohibited after that open square bracket '['
#43: FILE: drivers/gpu/drm/xe/xe_pat.c:177:
+	[ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ),

-:43: ERROR:SPACING: space prohibited after that open parenthesis '('
#43: FILE: drivers/gpu/drm/xe/xe_pat.c:177:
+	[ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ),

-:43: ERROR:SPACING: space prohibited before that close parenthesis ')'
#43: FILE: drivers/gpu/drm/xe/xe_pat.c:177:
+	[ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ),

-:44: ERROR:SPACING: space prohibited after that open square bracket '['
#44: FILE: drivers/gpu/drm/xe/xe_pat.c:178:
+	[ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ),

-:44: ERROR:SPACING: space prohibited after that open parenthesis '('
#44: FILE: drivers/gpu/drm/xe/xe_pat.c:178:
+	[ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ),

-:44: ERROR:SPACING: space prohibited before that close parenthesis ')'
#44: FILE: drivers/gpu/drm/xe/xe_pat.c:178:
+	[ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ),

-:45: ERROR:SPACING: space prohibited after that open parenthesis '('
#45: FILE: drivers/gpu/drm/xe/xe_pat.c:179:
+	[10] = XE3P_XPC_PAT( 0, 0, 0, 3, 3 ),

-:45: ERROR:SPACING: space prohibited before that close parenthesis ')'
#45: FILE: drivers/gpu/drm/xe/xe_pat.c:179:
+	[10] = XE3P_XPC_PAT( 0, 0, 0, 3, 3 ),

-:47: ERROR:SPACING: space prohibited after that open parenthesis '('
#47: FILE: drivers/gpu/drm/xe/xe_pat.c:181:
+	[23] = XE3P_XPC_PAT( 0, 1, 0, 0, 0 ),

-:47: ERROR:SPACING: space prohibited before that close parenthesis ')'
#47: FILE: drivers/gpu/drm/xe/xe_pat.c:181:
+	[23] = XE3P_XPC_PAT( 0, 1, 0, 0, 0 ),

-:48: ERROR:SPACING: space prohibited after that open parenthesis '('
#48: FILE: drivers/gpu/drm/xe/xe_pat.c:182:
+	[24] = XE3P_XPC_PAT( 0, 1, 0, 0, 2 ),

-:48: ERROR:SPACING: space prohibited before that close parenthesis ')'
#48: FILE: drivers/gpu/drm/xe/xe_pat.c:182:
+	[24] = XE3P_XPC_PAT( 0, 1, 0, 0, 2 ),

-:49: ERROR:SPACING: space prohibited after that open parenthesis '('
#49: FILE: drivers/gpu/drm/xe/xe_pat.c:183:
+	[25] = XE3P_XPC_PAT( 0, 1, 0, 0, 3 ),

-:49: ERROR:SPACING: space prohibited before that close parenthesis ')'
#49: FILE: drivers/gpu/drm/xe/xe_pat.c:183:
+	[25] = XE3P_XPC_PAT( 0, 1, 0, 0, 3 ),

-:50: ERROR:SPACING: space prohibited after that open parenthesis '('
#50: FILE: drivers/gpu/drm/xe/xe_pat.c:184:
+	[26] = XE3P_XPC_PAT( 0, 2, 0, 0, 0 ),

-:50: ERROR:SPACING: space prohibited before that close parenthesis ')'
#50: FILE: drivers/gpu/drm/xe/xe_pat.c:184:
+	[26] = XE3P_XPC_PAT( 0, 2, 0, 0, 0 ),

-:51: ERROR:SPACING: space prohibited after that open parenthesis '('
#51: FILE: drivers/gpu/drm/xe/xe_pat.c:185:
+	[27] = XE3P_XPC_PAT( 0, 2, 0, 0, 2 ),

-:51: ERROR:SPACING: space prohibited before that close parenthesis ')'
#51: FILE: drivers/gpu/drm/xe/xe_pat.c:185:
+	[27] = XE3P_XPC_PAT( 0, 2, 0, 0, 2 ),

-:52: ERROR:SPACING: space prohibited after that open parenthesis '('
#52: FILE: drivers/gpu/drm/xe/xe_pat.c:186:
+	[28] = XE3P_XPC_PAT( 0, 2, 0, 0, 3 ),

-:52: ERROR:SPACING: space prohibited before that close parenthesis ')'
#52: FILE: drivers/gpu/drm/xe/xe_pat.c:186:
+	[28] = XE3P_XPC_PAT( 0, 2, 0, 0, 3 ),

-:53: ERROR:SPACING: space prohibited after that open parenthesis '('
#53: FILE: drivers/gpu/drm/xe/xe_pat.c:187:
+	[29] = XE3P_XPC_PAT( 0, 3, 0, 0, 0 ),

-:53: ERROR:SPACING: space prohibited before that close parenthesis ')'
#53: FILE: drivers/gpu/drm/xe/xe_pat.c:187:
+	[29] = XE3P_XPC_PAT( 0, 3, 0, 0, 0 ),

-:54: ERROR:SPACING: space prohibited after that open parenthesis '('
#54: FILE: drivers/gpu/drm/xe/xe_pat.c:188:
+	[30] = XE3P_XPC_PAT( 0, 3, 0, 0, 2 ),

-:54: ERROR:SPACING: space prohibited before that close parenthesis ')'
#54: FILE: drivers/gpu/drm/xe/xe_pat.c:188:
+	[30] = XE3P_XPC_PAT( 0, 3, 0, 0, 2 ),

-:55: ERROR:SPACING: space prohibited after that open parenthesis '('
#55: FILE: drivers/gpu/drm/xe/xe_pat.c:189:
+	[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),

-:55: ERROR:SPACING: space prohibited before that close parenthesis ')'
#55: FILE: drivers/gpu/drm/xe/xe_pat.c:189:
+	[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),

total: 54 errors, 0 warnings, 0 checks, 110 lines checked
cc1e064d3414 drm/xe/xe3p: Add xe3p EU stall data format

✓ CI.KUnit: success for drm/xe: Add Xe3p support (rev2)

[Patchwork]

== Series Details ==

Series: drm/xe: Add Xe3p support (rev2)
URL   : https://patchwork.freedesktop.org/series/155866/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[05:11:46] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:11:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[05:12:27] Starting KUnit Kernel (1/1)...
[05:12:27] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:12:28] ================== guc_buf (11 subtests) ===================
[05:12:28] [PASSED] test_smallest
[05:12:28] [PASSED] test_largest
[05:12:28] [PASSED] test_granular
[05:12:28] [PASSED] test_unique
[05:12:28] [PASSED] test_overlap
[05:12:28] [PASSED] test_reusable
[05:12:28] [PASSED] test_too_big
[05:12:28] [PASSED] test_flush
[05:12:28] [PASSED] test_lookup
[05:12:28] [PASSED] test_data
[05:12:28] [PASSED] test_class
[05:12:28] ===================== [PASSED] guc_buf =====================
[05:12:28] =================== guc_dbm (7 subtests) ===================
[05:12:28] [PASSED] test_empty
[05:12:28] [PASSED] test_default
[05:12:28] ======================== test_size  ========================
[05:12:28] [PASSED] 4
[05:12:28] [PASSED] 8
[05:12:28] [PASSED] 32
[05:12:28] [PASSED] 256
[05:12:28] ==================== [PASSED] test_size ====================
[05:12:28] ======================= test_reuse  ========================
[05:12:28] [PASSED] 4
[05:12:28] [PASSED] 8
[05:12:28] [PASSED] 32
[05:12:28] [PASSED] 256
[05:12:28] =================== [PASSED] test_reuse ====================
[05:12:28] =================== test_range_overlap  ====================
[05:12:28] [PASSED] 4
[05:12:28] [PASSED] 8
[05:12:28] [PASSED] 32
[05:12:28] [PASSED] 256
[05:12:28] =============== [PASSED] test_range_overlap ================
[05:12:28] =================== test_range_compact  ====================
[05:12:28] [PASSED] 4
[05:12:28] [PASSED] 8
[05:12:28] [PASSED] 32
[05:12:28] [PASSED] 256
[05:12:28] =============== [PASSED] test_range_compact ================
[05:12:28] ==================== test_range_spare  =====================
[05:12:28] [PASSED] 4
[05:12:28] [PASSED] 8
[05:12:28] [PASSED] 32
[05:12:28] [PASSED] 256
[05:12:28] ================ [PASSED] test_range_spare =================
[05:12:28] ===================== [PASSED] guc_dbm =====================
[05:12:28] =================== guc_idm (6 subtests) ===================
[05:12:28] [PASSED] bad_init
[05:12:28] [PASSED] no_init
[05:12:28] [PASSED] init_fini
[05:12:28] [PASSED] check_used
[05:12:28] [PASSED] check_quota
[05:12:28] [PASSED] check_all
[05:12:28] ===================== [PASSED] guc_idm =====================
[05:12:28] ================== no_relay (3 subtests) ===================
[05:12:28] [PASSED] xe_drops_guc2pf_if_not_ready
[05:12:28] [PASSED] xe_drops_guc2vf_if_not_ready
[05:12:28] [PASSED] xe_rejects_send_if_not_ready
[05:12:28] ==================== [PASSED] no_relay =====================
[05:12:28] ================== pf_relay (14 subtests) ==================
[05:12:28] [PASSED] pf_rejects_guc2pf_too_short
[05:12:28] [PASSED] pf_rejects_guc2pf_too_long
[05:12:28] [PASSED] pf_rejects_guc2pf_no_payload
[05:12:28] [PASSED] pf_fails_no_payload
[05:12:28] [PASSED] pf_fails_bad_origin
[05:12:28] [PASSED] pf_fails_bad_type
[05:12:28] [PASSED] pf_txn_reports_error
[05:12:28] [PASSED] pf_txn_sends_pf2guc
[05:12:28] [PASSED] pf_sends_pf2guc
[05:12:28] [SKIPPED] pf_loopback_nop
[05:12:28] [SKIPPED] pf_loopback_echo
[05:12:28] [SKIPPED] pf_loopback_fail
[05:12:28] [SKIPPED] pf_loopback_busy
[05:12:28] [SKIPPED] pf_loopback_retry
[05:12:28] ==================== [PASSED] pf_relay =====================
[05:12:28] ================== vf_relay (3 subtests) ===================
[05:12:28] [PASSED] vf_rejects_guc2vf_too_short
[05:12:28] [PASSED] vf_rejects_guc2vf_too_long
[05:12:28] [PASSED] vf_rejects_guc2vf_no_payload
[05:12:28] ==================== [PASSED] vf_relay =====================
[05:12:28] ===================== lmtt (1 subtest) =====================
[05:12:28] ======================== test_ops  =========================
[05:12:28] [PASSED] 2-level
[05:12:28] [PASSED] multi-level
[05:12:28] ==================== [PASSED] test_ops =====================
[05:12:28] ====================== [PASSED] lmtt =======================
[05:12:28] ================= pf_service (11 subtests) =================
[05:12:28] [PASSED] pf_negotiate_any
[05:12:28] [PASSED] pf_negotiate_base_match
[05:12:28] [PASSED] pf_negotiate_base_newer
[05:12:28] [PASSED] pf_negotiate_base_next
[05:12:28] [SKIPPED] pf_negotiate_base_older
[05:12:28] [PASSED] pf_negotiate_base_prev
[05:12:28] [PASSED] pf_negotiate_latest_match
[05:12:28] [PASSED] pf_negotiate_latest_newer
[05:12:28] [PASSED] pf_negotiate_latest_next
[05:12:28] [SKIPPED] pf_negotiate_latest_older
[05:12:28] [SKIPPED] pf_negotiate_latest_prev
[05:12:28] =================== [PASSED] pf_service ====================
[05:12:28] ================= xe_guc_g2g (2 subtests) ==================
[05:12:28] ============== xe_live_guc_g2g_kunit_default  ==============
[05:12:28] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[05:12:28] ============== xe_live_guc_g2g_kunit_allmem  ===============
[05:12:28] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[05:12:28] =================== [SKIPPED] xe_guc_g2g ===================
[05:12:28] =================== xe_mocs (2 subtests) ===================
[05:12:28] ================ xe_live_mocs_kernel_kunit  ================
[05:12:28] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[05:12:28] ================ xe_live_mocs_reset_kunit  =================
[05:12:28] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[05:12:28] ==================== [SKIPPED] xe_mocs =====================
[05:12:28] ================= xe_migrate (2 subtests) ==================
[05:12:28] ================= xe_migrate_sanity_kunit  =================
[05:12:28] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[05:12:28] ================== xe_validate_ccs_kunit  ==================
[05:12:28] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[05:12:28] =================== [SKIPPED] xe_migrate ===================
[05:12:28] ================== xe_dma_buf (1 subtest) ==================
[05:12:28] ==================== xe_dma_buf_kunit  =====================
[05:12:28] ================ [SKIPPED] xe_dma_buf_kunit ================
[05:12:28] =================== [SKIPPED] xe_dma_buf ===================
[05:12:28] ================= xe_bo_shrink (1 subtest) =================
[05:12:28] =================== xe_bo_shrink_kunit  ====================
[05:12:28] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[05:12:28] ================== [SKIPPED] xe_bo_shrink ==================
[05:12:28] ==================== xe_bo (2 subtests) ====================
[05:12:28] ================== xe_ccs_migrate_kunit  ===================
[05:12:28] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[05:12:28] ==================== xe_bo_evict_kunit  ====================
[05:12:28] =============== [SKIPPED] xe_bo_evict_kunit ================
[05:12:28] ===================== [SKIPPED] xe_bo ======================
[05:12:28] ==================== args (11 subtests) ====================
[05:12:28] [PASSED] count_args_test
[05:12:28] [PASSED] call_args_example
[05:12:28] [PASSED] call_args_test
[05:12:28] [PASSED] drop_first_arg_example
[05:12:28] [PASSED] drop_first_arg_test
[05:12:28] [PASSED] first_arg_example
[05:12:28] [PASSED] first_arg_test
[05:12:28] [PASSED] last_arg_example
[05:12:28] [PASSED] last_arg_test
[05:12:28] [PASSED] pick_arg_example
[05:12:28] [PASSED] sep_comma_example
[05:12:28] ====================== [PASSED] args =======================
[05:12:28] =================== xe_pci (3 subtests) ====================
[05:12:28] ==================== check_graphics_ip  ====================
[05:12:28] [PASSED] 12.00 Xe_LP
[05:12:28] [PASSED] 12.10 Xe_LP+
[05:12:28] [PASSED] 12.55 Xe_HPG
[05:12:28] [PASSED] 12.60 Xe_HPC
[05:12:28] [PASSED] 12.70 Xe_LPG
[05:12:28] [PASSED] 12.71 Xe_LPG
[05:12:28] [PASSED] 12.74 Xe_LPG+
[05:12:28] [PASSED] 20.01 Xe2_HPG
[05:12:28] [PASSED] 20.02 Xe2_HPG
[05:12:28] [PASSED] 20.04 Xe2_LPG
[05:12:28] [PASSED] 30.00 Xe3_LPG
[05:12:28] [PASSED] 30.01 Xe3_LPG
[05:12:28] [PASSED] 30.03 Xe3_LPG
[05:12:28] [PASSED] 30.04 Xe3_LPG
[05:12:28] [PASSED] 30.05 Xe3_LPG
[05:12:28] [PASSED] 35.11 Xe3p_XPC
[05:12:28] ================ [PASSED] check_graphics_ip ================
[05:12:28] ===================== check_media_ip  ======================
[05:12:28] [PASSED] 12.00 Xe_M
[05:12:28] [PASSED] 12.55 Xe_HPM
[05:12:28] [PASSED] 13.00 Xe_LPM+
[05:12:28] [PASSED] 13.01 Xe2_HPM
[05:12:28] [PASSED] 20.00 Xe2_LPM
[05:12:28] [PASSED] 30.00 Xe3_LPM
[05:12:28] [PASSED] 30.02 Xe3_LPM
[05:12:28] [PASSED] 35.00 Xe3p_LPM
[05:12:28] [PASSED] 35.03 Xe3p_LPM
[05:12:28] ================= [PASSED] check_media_ip ==================
[05:12:28] ================= check_platform_gt_count  =================
[05:12:28] [PASSED] 0x9A60 (TIGERLAKE)
[05:12:28] [PASSED] 0x9A68 (TIGERLAKE)
[05:12:28] [PASSED] 0x9A70 (TIGERLAKE)
[05:12:28] [PASSED] 0x9A40 (TIGERLAKE)
[05:12:28] [PASSED] 0x9A49 (TIGERLAKE)
[05:12:28] [PASSED] 0x9A59 (TIGERLAKE)
[05:12:28] [PASSED] 0x9A78 (TIGERLAKE)
[05:12:28] [PASSED] 0x9AC0 (TIGERLAKE)
[05:12:28] [PASSED] 0x9AC9 (TIGERLAKE)
[05:12:28] [PASSED] 0x9AD9 (TIGERLAKE)
[05:12:28] [PASSED] 0x9AF8 (TIGERLAKE)
[05:12:28] [PASSED] 0x4C80 (ROCKETLAKE)
[05:12:28] [PASSED] 0x4C8A (ROCKETLAKE)
[05:12:28] [PASSED] 0x4C8B (ROCKETLAKE)
[05:12:28] [PASSED] 0x4C8C (ROCKETLAKE)
[05:12:28] [PASSED] 0x4C90 (ROCKETLAKE)
[05:12:28] [PASSED] 0x4C9A (ROCKETLAKE)
[05:12:28] [PASSED] 0x4680 (ALDERLAKE_S)
[05:12:28] [PASSED] 0x4682 (ALDERLAKE_S)
[05:12:28] [PASSED] 0x4688 (ALDERLAKE_S)
[05:12:28] [PASSED] 0x468A (ALDERLAKE_S)
[05:12:28] [PASSED] 0x468B (ALDERLAKE_S)
[05:12:28] [PASSED] 0x4690 (ALDERLAKE_S)
[05:12:28] [PASSED] 0x4692 (ALDERLAKE_S)
[05:12:28] [PASSED] 0x4693 (ALDERLAKE_S)
[05:12:28] [PASSED] 0x46A0 (ALDERLAKE_P)
[05:12:28] [PASSED] 0x46A1 (ALDERLAKE_P)
[05:12:28] [PASSED] 0x46A2 (ALDERLAKE_P)
[05:12:28] [PASSED] 0x46A3 (ALDERLAKE_P)
[05:12:28] [PASSED] 0x46A6 (ALDERLAKE_P)
[05:12:28] [PASSED] 0x46A8 (ALDERLAKE_P)
[05:12:28] [PASSED] 0x46AA (ALDERLAKE_P)
[05:12:28] [PASSED] 0x462A (ALDERLAKE_P)
[05:12:28] [PASSED] 0x4626 (ALDERLAKE_P)
[05:12:28] [PASSED] 0x4628 (ALDERLAKE_P)
[05:12:28] [PASSED] 0x46B0 (ALDERLAKE_P)
[05:12:28] [PASSED] 0x46B1 (ALDERLAKE_P)
[05:12:28] [PASSED] 0x46B2 (ALDERLAKE_P)
[05:12:28] [PASSED] 0x46B3 (ALDERLAKE_P)
[05:12:28] [PASSED] 0x46C0 (ALDERLAKE_P)
[05:12:28] [PASSED] 0x46C1 (ALDERLAKE_P)
[05:12:28] [PASSED] 0x46C2 (ALDERLAKE_P)
[05:12:28] [PASSED] 0x46C3 (ALDERLAKE_P)
[05:12:28] [PASSED] 0x46D0 (ALDERLAKE_N)
[05:12:28] [PASSED] 0x46D1 (ALDERLAKE_N)
[05:12:28] [PASSED] 0x46D2 (ALDERLAKE_N)
[05:12:28] [PASSED] 0x46D3 (ALDERLAKE_N)
[05:12:28] [PASSED] 0x46D4 (ALDERLAKE_N)
[05:12:28] [PASSED] 0xA721 (ALDERLAKE_P)
[05:12:28] [PASSED] 0xA7A1 (ALDERLAKE_P)
[05:12:28] [PASSED] 0xA7A9 (ALDERLAKE_P)
[05:12:28] [PASSED] 0xA7AC (ALDERLAKE_P)
[05:12:28] [PASSED] 0xA7AD (ALDERLAKE_P)
[05:12:28] [PASSED] 0xA720 (ALDERLAKE_P)
[05:12:28] [PASSED] 0xA7A0 (ALDERLAKE_P)
[05:12:28] [PASSED] 0xA7A8 (ALDERLAKE_P)
[05:12:28] [PASSED] 0xA7AA (ALDERLAKE_P)
[05:12:28] [PASSED] 0xA7AB (ALDERLAKE_P)
[05:12:28] [PASSED] 0xA780 (ALDERLAKE_S)
[05:12:28] [PASSED] 0xA781 (ALDERLAKE_S)
[05:12:28] [PASSED] 0xA782 (ALDERLAKE_S)
[05:12:28] [PASSED] 0xA783 (ALDERLAKE_S)
[05:12:28] [PASSED] 0xA788 (ALDERLAKE_S)
[05:12:28] [PASSED] 0xA789 (ALDERLAKE_S)
[05:12:28] [PASSED] 0xA78A (ALDERLAKE_S)
[05:12:28] [PASSED] 0xA78B (ALDERLAKE_S)
[05:12:28] [PASSED] 0x4905 (DG1)
[05:12:28] [PASSED] 0x4906 (DG1)
[05:12:28] [PASSED] 0x4907 (DG1)
[05:12:28] [PASSED] 0x4908 (DG1)
[05:12:28] [PASSED] 0x4909 (DG1)
[05:12:28] [PASSED] 0x56C0 (DG2)
[05:12:28] [PASSED] 0x56C2 (DG2)
[05:12:28] [PASSED] 0x56C1 (DG2)
[05:12:28] [PASSED] 0x7D51 (METEORLAKE)
[05:12:28] [PASSED] 0x7DD1 (METEORLAKE)
[05:12:28] [PASSED] 0x7D41 (METEORLAKE)
[05:12:28] [PASSED] 0x7D67 (METEORLAKE)
[05:12:28] [PASSED] 0xB640 (METEORLAKE)
[05:12:28] [PASSED] 0x56A0 (DG2)
[05:12:28] [PASSED] 0x56A1 (DG2)
[05:12:28] [PASSED] 0x56A2 (DG2)
[05:12:28] [PASSED] 0x56BE (DG2)
[05:12:28] [PASSED] 0x56BF (DG2)
[05:12:28] [PASSED] 0x5690 (DG2)
[05:12:28] [PASSED] 0x5691 (DG2)
[05:12:28] [PASSED] 0x5692 (DG2)
[05:12:28] [PASSED] 0x56A5 (DG2)
[05:12:28] [PASSED] 0x56A6 (DG2)
[05:12:28] [PASSED] 0x56B0 (DG2)
[05:12:28] [PASSED] 0x56B1 (DG2)
[05:12:28] [PASSED] 0x56BA (DG2)
[05:12:28] [PASSED] 0x56BB (DG2)
[05:12:28] [PASSED] 0x56BC (DG2)
[05:12:28] [PASSED] 0x56BD (DG2)
[05:12:28] [PASSED] 0x5693 (DG2)
[05:12:28] [PASSED] 0x5694 (DG2)
[05:12:28] [PASSED] 0x5695 (DG2)
[05:12:28] [PASSED] 0x56A3 (DG2)
[05:12:28] [PASSED] 0x56A4 (DG2)
[05:12:28] [PASSED] 0x56B2 (DG2)
[05:12:28] [PASSED] 0x56B3 (DG2)
[05:12:28] [PASSED] 0x5696 (DG2)
[05:12:28] [PASSED] 0x5697 (DG2)
[05:12:28] [PASSED] 0xB69 (PVC)
[05:12:28] [PASSED] 0xB6E (PVC)
[05:12:28] [PASSED] 0xBD4 (PVC)
[05:12:28] [PASSED] 0xBD5 (PVC)
[05:12:28] [PASSED] 0xBD6 (PVC)
[05:12:28] [PASSED] 0xBD7 (PVC)
[05:12:28] [PASSED] 0xBD8 (PVC)
[05:12:28] [PASSED] 0xBD9 (PVC)
[05:12:28] [PASSED] 0xBDA (PVC)
[05:12:28] [PASSED] 0xBDB (PVC)
[05:12:28] [PASSED] 0xBE0 (PVC)
[05:12:28] [PASSED] 0xBE1 (PVC)
[05:12:28] [PASSED] 0xBE5 (PVC)
[05:12:28] [PASSED] 0x7D40 (METEORLAKE)
[05:12:28] [PASSED] 0x7D45 (METEORLAKE)
[05:12:28] [PASSED] 0x7D55 (METEORLAKE)
[05:12:28] [PASSED] 0x7D60 (METEORLAKE)
[05:12:28] [PASSED] 0x7DD5 (METEORLAKE)
[05:12:28] [PASSED] 0x6420 (LUNARLAKE)
[05:12:28] [PASSED] 0x64A0 (LUNARLAKE)
[05:12:28] [PASSED] 0x64B0 (LUNARLAKE)
[05:12:28] [PASSED] 0xE202 (BATTLEMAGE)
[05:12:28] [PASSED] 0xE209 (BATTLEMAGE)
[05:12:28] [PASSED] 0xE20B (BATTLEMAGE)
[05:12:28] [PASSED] 0xE20C (BATTLEMAGE)
[05:12:28] [PASSED] 0xE20D (BATTLEMAGE)
[05:12:28] [PASSED] 0xE210 (BATTLEMAGE)
[05:12:28] [PASSED] 0xE211 (BATTLEMAGE)
[05:12:28] [PASSED] 0xE212 (BATTLEMAGE)
[05:12:28] [PASSED] 0xE216 (BATTLEMAGE)
[05:12:28] [PASSED] 0xE220 (BATTLEMAGE)
[05:12:28] [PASSED] 0xE221 (BATTLEMAGE)
[05:12:28] [PASSED] 0xE222 (BATTLEMAGE)
[05:12:28] [PASSED] 0xE223 (BATTLEMAGE)
[05:12:28] [PASSED] 0xB080 (PANTHERLAKE)
[05:12:28] [PASSED] 0xB081 (PANTHERLAKE)
[05:12:28] [PASSED] 0xB082 (PANTHERLAKE)
[05:12:28] [PASSED] 0xB083 (PANTHERLAKE)
[05:12:28] [PASSED] 0xB084 (PANTHERLAKE)
[05:12:28] [PASSED] 0xB085 (PANTHERLAKE)
[05:12:28] [PASSED] 0xB086 (PANTHERLAKE)
[05:12:28] [PASSED] 0xB087 (PANTHERLAKE)
[05:12:28] [PASSED] 0xB08F (PANTHERLAKE)
[05:12:28] [PASSED] 0xB090 (PANTHERLAKE)
[05:12:28] [PASSED] 0xB0A0 (PANTHERLAKE)
[05:12:28] [PASSED] 0xB0B0 (PANTHERLAKE)
[05:12:28] [PASSED] 0xFD80 (PANTHERLAKE)
[05:12:28] [PASSED] 0xFD81 (PANTHERLAKE)
[05:12:28] [PASSED] 0xD740 (NOVALAKE_S)
[05:12:28] [PASSED] 0xD741 (NOVALAKE_S)
[05:12:28] [PASSED] 0xD742 (NOVALAKE_S)
[05:12:28] [PASSED] 0xD743 (NOVALAKE_S)
[05:12:28] [PASSED] 0xD744 (NOVALAKE_S)
[05:12:28] [PASSED] 0xD745 (NOVALAKE_S)
[05:12:28] ============= [PASSED] check_platform_gt_count =============
[05:12:28] ===================== [PASSED] xe_pci ======================
[05:12:28] =================== xe_rtp (2 subtests) ====================
[05:12:28] =============== xe_rtp_process_to_sr_tests  ================
[05:12:28] [PASSED] coalesce-same-reg
[05:12:28] [PASSED] no-match-no-add
[05:12:28] [PASSED] match-or
[05:12:28] [PASSED] match-or-xfail
[05:12:28] [PASSED] no-match-no-add-multiple-rules
[05:12:28] [PASSED] two-regs-two-entries
[05:12:28] [PASSED] clr-one-set-other
[05:12:28] [PASSED] set-field
[05:12:28] [PASSED] conflict-duplicate
[05:12:28] [PASSED] conflict-not-disjoint
[05:12:28] [PASSED] conflict-reg-type
[05:12:28] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[05:12:28] ================== xe_rtp_process_tests  ===================
[05:12:28] [PASSED] active1
[05:12:28] [PASSED] active2
[05:12:28] [PASSED] active-inactive
[05:12:28] [PASSED] inactive-active
[05:12:28] [PASSED] inactive-1st_or_active-inactive
[05:12:28] [PASSED] inactive-2nd_or_active-inactive
[05:12:28] [PASSED] inactive-last_or_active-inactive
[05:12:28] [PASSED] inactive-no_or_active-inactive
stty: 'standard input': Inappropriate ioctl for device
[05:12:28] ============== [PASSED] xe_rtp_process_tests ===============
[05:12:28] ===================== [PASSED] xe_rtp ======================
[05:12:28] ==================== xe_wa (1 subtest) =====================
[05:12:28] ======================== xe_wa_gt  =========================
[05:12:28] [PASSED] TIGERLAKE B0
[05:12:28] [PASSED] DG1 A0
[05:12:28] [PASSED] DG1 B0
[05:12:28] [PASSED] ALDERLAKE_S A0
[05:12:28] [PASSED] ALDERLAKE_S B0
[05:12:28] [PASSED] ALDERLAKE_S C0
[05:12:28] [PASSED] ALDERLAKE_S D0
[05:12:28] [PASSED] ALDERLAKE_P A0
[05:12:28] [PASSED] ALDERLAKE_P B0
[05:12:28] [PASSED] ALDERLAKE_P C0
[05:12:28] [PASSED] ALDERLAKE_S RPLS D0
[05:12:28] [PASSED] ALDERLAKE_P RPLU E0
[05:12:28] [PASSED] DG2 G10 C0
[05:12:28] [PASSED] DG2 G11 B1
[05:12:28] [PASSED] DG2 G12 A1
[05:12:28] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[05:12:28] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[05:12:28] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[05:12:28] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[05:12:28] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[05:12:28] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[05:12:28] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[05:12:28] ==================== [PASSED] xe_wa_gt =====================
[05:12:28] ====================== [PASSED] xe_wa ======================
[05:12:28] ============================================================
[05:12:28] Testing complete. Ran 317 tests: passed: 299, skipped: 18
[05:12:28] Elapsed time: 41.898s total, 4.352s configuring, 37.179s building, 0.336s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[05:12:28] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:12:29] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[05:12:59] Starting KUnit Kernel (1/1)...
[05:12:59] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:12:59] ============ drm_test_pick_cmdline (2 subtests) ============
[05:12:59] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[05:12:59] =============== drm_test_pick_cmdline_named  ===============
[05:12:59] [PASSED] NTSC
[05:12:59] [PASSED] NTSC-J
[05:12:59] [PASSED] PAL
[05:12:59] [PASSED] PAL-M
[05:12:59] =========== [PASSED] drm_test_pick_cmdline_named ===========
[05:12:59] ============== [PASSED] drm_test_pick_cmdline ==============
[05:12:59] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[05:12:59] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[05:12:59] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[05:12:59] =========== drm_validate_clone_mode (2 subtests) ===========
[05:12:59] ============== drm_test_check_in_clone_mode  ===============
[05:12:59] [PASSED] in_clone_mode
[05:12:59] [PASSED] not_in_clone_mode
[05:12:59] ========== [PASSED] drm_test_check_in_clone_mode ===========
[05:12:59] =============== drm_test_check_valid_clones  ===============
[05:12:59] [PASSED] not_in_clone_mode
[05:12:59] [PASSED] valid_clone
[05:12:59] [PASSED] invalid_clone
[05:12:59] =========== [PASSED] drm_test_check_valid_clones ===========
[05:12:59] ============= [PASSED] drm_validate_clone_mode =============
[05:12:59] ============= drm_validate_modeset (1 subtest) =============
[05:12:59] [PASSED] drm_test_check_connector_changed_modeset
[05:12:59] ============== [PASSED] drm_validate_modeset ===============
[05:12:59] ====== drm_test_bridge_get_current_state (2 subtests) ======
[05:12:59] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[05:12:59] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[05:12:59] ======== [PASSED] drm_test_bridge_get_current_state ========
[05:12:59] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[05:12:59] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[05:12:59] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[05:12:59] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[05:12:59] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[05:12:59] ============== drm_bridge_alloc (2 subtests) ===============
[05:12:59] [PASSED] drm_test_drm_bridge_alloc_basic
[05:12:59] [PASSED] drm_test_drm_bridge_alloc_get_put
[05:12:59] ================ [PASSED] drm_bridge_alloc =================
[05:12:59] ================== drm_buddy (8 subtests) ==================
[05:12:59] [PASSED] drm_test_buddy_alloc_limit
[05:12:59] [PASSED] drm_test_buddy_alloc_optimistic
[05:12:59] [PASSED] drm_test_buddy_alloc_pessimistic
[05:12:59] [PASSED] drm_test_buddy_alloc_pathological
[05:12:59] [PASSED] drm_test_buddy_alloc_contiguous
[05:12:59] [PASSED] drm_test_buddy_alloc_clear
[05:12:59] [PASSED] drm_test_buddy_alloc_range_bias
[05:13:00] [PASSED] drm_test_buddy_fragmentation_performance
[05:13:00] ==================== [PASSED] drm_buddy ====================
[05:13:00] ============= drm_cmdline_parser (40 subtests) =============
[05:13:00] [PASSED] drm_test_cmdline_force_d_only
[05:13:00] [PASSED] drm_test_cmdline_force_D_only_dvi
[05:13:00] [PASSED] drm_test_cmdline_force_D_only_hdmi
[05:13:00] [PASSED] drm_test_cmdline_force_D_only_not_digital
[05:13:00] [PASSED] drm_test_cmdline_force_e_only
[05:13:00] [PASSED] drm_test_cmdline_res
[05:13:00] [PASSED] drm_test_cmdline_res_vesa
[05:13:00] [PASSED] drm_test_cmdline_res_vesa_rblank
[05:13:00] [PASSED] drm_test_cmdline_res_rblank
[05:13:00] [PASSED] drm_test_cmdline_res_bpp
[05:13:00] [PASSED] drm_test_cmdline_res_refresh
[05:13:00] [PASSED] drm_test_cmdline_res_bpp_refresh
[05:13:00] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[05:13:00] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[05:13:00] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[05:13:00] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[05:13:00] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[05:13:00] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[05:13:00] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[05:13:00] [PASSED] drm_test_cmdline_res_margins_force_on
[05:13:00] [PASSED] drm_test_cmdline_res_vesa_margins
[05:13:00] [PASSED] drm_test_cmdline_name
[05:13:00] [PASSED] drm_test_cmdline_name_bpp
[05:13:00] [PASSED] drm_test_cmdline_name_option
[05:13:00] [PASSED] drm_test_cmdline_name_bpp_option
[05:13:00] [PASSED] drm_test_cmdline_rotate_0
[05:13:00] [PASSED] drm_test_cmdline_rotate_90
[05:13:00] [PASSED] drm_test_cmdline_rotate_180
[05:13:00] [PASSED] drm_test_cmdline_rotate_270
[05:13:00] [PASSED] drm_test_cmdline_hmirror
[05:13:00] [PASSED] drm_test_cmdline_vmirror
[05:13:00] [PASSED] drm_test_cmdline_margin_options
[05:13:00] [PASSED] drm_test_cmdline_multiple_options
[05:13:00] [PASSED] drm_test_cmdline_bpp_extra_and_option
[05:13:00] [PASSED] drm_test_cmdline_extra_and_option
[05:13:00] [PASSED] drm_test_cmdline_freestanding_options
[05:13:00] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[05:13:00] [PASSED] drm_test_cmdline_panel_orientation
[05:13:00] ================ drm_test_cmdline_invalid  =================
[05:13:00] [PASSED] margin_only
[05:13:00] [PASSED] interlace_only
[05:13:00] [PASSED] res_missing_x
[05:13:00] [PASSED] res_missing_y
[05:13:00] [PASSED] res_bad_y
[05:13:00] [PASSED] res_missing_y_bpp
[05:13:00] [PASSED] res_bad_bpp
[05:13:00] [PASSED] res_bad_refresh
[05:13:00] [PASSED] res_bpp_refresh_force_on_off
[05:13:00] [PASSED] res_invalid_mode
[05:13:00] [PASSED] res_bpp_wrong_place_mode
[05:13:00] [PASSED] name_bpp_refresh
[05:13:00] [PASSED] name_refresh
[05:13:00] [PASSED] name_refresh_wrong_mode
[05:13:00] [PASSED] name_refresh_invalid_mode
[05:13:00] [PASSED] rotate_multiple
[05:13:00] [PASSED] rotate_invalid_val
[05:13:00] [PASSED] rotate_truncated
[05:13:00] [PASSED] invalid_option
[05:13:00] [PASSED] invalid_tv_option
[05:13:00] [PASSED] truncated_tv_option
[05:13:00] ============ [PASSED] drm_test_cmdline_invalid =============
[05:13:00] =============== drm_test_cmdline_tv_options  ===============
[05:13:00] [PASSED] NTSC
[05:13:00] [PASSED] NTSC_443
[05:13:00] [PASSED] NTSC_J
[05:13:00] [PASSED] PAL
[05:13:00] [PASSED] PAL_M
[05:13:00] [PASSED] PAL_N
[05:13:00] [PASSED] SECAM
[05:13:00] [PASSED] MONO_525
[05:13:00] [PASSED] MONO_625
[05:13:00] =========== [PASSED] drm_test_cmdline_tv_options ===========
[05:13:00] =============== [PASSED] drm_cmdline_parser ================
[05:13:00] ========== drmm_connector_hdmi_init (20 subtests) ==========
[05:13:00] [PASSED] drm_test_connector_hdmi_init_valid
[05:13:00] [PASSED] drm_test_connector_hdmi_init_bpc_8
[05:13:00] [PASSED] drm_test_connector_hdmi_init_bpc_10
[05:13:00] [PASSED] drm_test_connector_hdmi_init_bpc_12
[05:13:00] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[05:13:00] [PASSED] drm_test_connector_hdmi_init_bpc_null
[05:13:00] [PASSED] drm_test_connector_hdmi_init_formats_empty
[05:13:00] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[05:13:00] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[05:13:00] [PASSED] supported_formats=0x9 yuv420_allowed=1
[05:13:00] [PASSED] supported_formats=0x9 yuv420_allowed=0
[05:13:00] [PASSED] supported_formats=0x3 yuv420_allowed=1
[05:13:00] [PASSED] supported_formats=0x3 yuv420_allowed=0
[05:13:00] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[05:13:00] [PASSED] drm_test_connector_hdmi_init_null_ddc
[05:13:00] [PASSED] drm_test_connector_hdmi_init_null_product
[05:13:00] [PASSED] drm_test_connector_hdmi_init_null_vendor
[05:13:00] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[05:13:00] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[05:13:00] [PASSED] drm_test_connector_hdmi_init_product_valid
[05:13:00] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[05:13:00] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[05:13:00] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[05:13:00] ========= drm_test_connector_hdmi_init_type_valid  =========
[05:13:00] [PASSED] HDMI-A
[05:13:00] [PASSED] HDMI-B
[05:13:00] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[05:13:00] ======== drm_test_connector_hdmi_init_type_invalid  ========
[05:13:00] [PASSED] Unknown
[05:13:00] [PASSED] VGA
[05:13:00] [PASSED] DVI-I
[05:13:00] [PASSED] DVI-D
[05:13:00] [PASSED] DVI-A
[05:13:00] [PASSED] Composite
[05:13:00] [PASSED] SVIDEO
[05:13:00] [PASSED] LVDS
[05:13:00] [PASSED] Component
[05:13:00] [PASSED] DIN
[05:13:00] [PASSED] DP
[05:13:00] [PASSED] TV
[05:13:00] [PASSED] eDP
[05:13:00] [PASSED] Virtual
[05:13:00] [PASSED] DSI
[05:13:00] [PASSED] DPI
[05:13:00] [PASSED] Writeback
[05:13:00] [PASSED] SPI
[05:13:00] [PASSED] USB
[05:13:00] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[05:13:00] ============ [PASSED] drmm_connector_hdmi_init =============
[05:13:00] ============= drmm_connector_init (3 subtests) =============
[05:13:00] [PASSED] drm_test_drmm_connector_init
[05:13:00] [PASSED] drm_test_drmm_connector_init_null_ddc
[05:13:00] ========= drm_test_drmm_connector_init_type_valid  =========
[05:13:00] [PASSED] Unknown
[05:13:00] [PASSED] VGA
[05:13:00] [PASSED] DVI-I
[05:13:00] [PASSED] DVI-D
[05:13:00] [PASSED] DVI-A
[05:13:00] [PASSED] Composite
[05:13:00] [PASSED] SVIDEO
[05:13:00] [PASSED] LVDS
[05:13:00] [PASSED] Component
[05:13:00] [PASSED] DIN
[05:13:00] [PASSED] DP
[05:13:00] [PASSED] HDMI-A
[05:13:00] [PASSED] HDMI-B
[05:13:00] [PASSED] TV
[05:13:00] [PASSED] eDP
[05:13:00] [PASSED] Virtual
[05:13:00] [PASSED] DSI
[05:13:00] [PASSED] DPI
[05:13:00] [PASSED] Writeback
[05:13:00] [PASSED] SPI
[05:13:00] [PASSED] USB
[05:13:00] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[05:13:00] =============== [PASSED] drmm_connector_init ===============
[05:13:00] ========= drm_connector_dynamic_init (6 subtests) ==========
[05:13:00] [PASSED] drm_test_drm_connector_dynamic_init
[05:13:00] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[05:13:00] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[05:13:00] [PASSED] drm_test_drm_connector_dynamic_init_properties
[05:13:00] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[05:13:00] [PASSED] Unknown
[05:13:00] [PASSED] VGA
[05:13:00] [PASSED] DVI-I
[05:13:00] [PASSED] DVI-D
[05:13:00] [PASSED] DVI-A
[05:13:00] [PASSED] Composite
[05:13:00] [PASSED] SVIDEO
[05:13:00] [PASSED] LVDS
[05:13:00] [PASSED] Component
[05:13:00] [PASSED] DIN
[05:13:00] [PASSED] DP
[05:13:00] [PASSED] HDMI-A
[05:13:00] [PASSED] HDMI-B
[05:13:00] [PASSED] TV
[05:13:00] [PASSED] eDP
[05:13:00] [PASSED] Virtual
[05:13:00] [PASSED] DSI
[05:13:00] [PASSED] DPI
[05:13:00] [PASSED] Writeback
[05:13:00] [PASSED] SPI
[05:13:00] [PASSED] USB
[05:13:00] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[05:13:00] ======== drm_test_drm_connector_dynamic_init_name  =========
[05:13:00] [PASSED] Unknown
[05:13:00] [PASSED] VGA
[05:13:00] [PASSED] DVI-I
[05:13:00] [PASSED] DVI-D
[05:13:00] [PASSED] DVI-A
[05:13:00] [PASSED] Composite
[05:13:00] [PASSED] SVIDEO
[05:13:00] [PASSED] LVDS
[05:13:00] [PASSED] Component
[05:13:00] [PASSED] DIN
[05:13:00] [PASSED] DP
[05:13:00] [PASSED] HDMI-A
[05:13:00] [PASSED] HDMI-B
[05:13:00] [PASSED] TV
[05:13:00] [PASSED] eDP
[05:13:00] [PASSED] Virtual
[05:13:00] [PASSED] DSI
[05:13:00] [PASSED] DPI
[05:13:00] [PASSED] Writeback
[05:13:00] [PASSED] SPI
[05:13:00] [PASSED] USB
[05:13:00] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[05:13:00] =========== [PASSED] drm_connector_dynamic_init ============
[05:13:00] ==== drm_connector_dynamic_register_early (4 subtests) =====
[05:13:00] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[05:13:00] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[05:13:00] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[05:13:00] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[05:13:00] ====== [PASSED] drm_connector_dynamic_register_early =======
[05:13:00] ======= drm_connector_dynamic_register (7 subtests) ========
[05:13:00] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[05:13:00] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[05:13:00] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[05:13:00] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[05:13:00] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[05:13:00] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[05:13:00] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[05:13:00] ========= [PASSED] drm_connector_dynamic_register ==========
[05:13:00] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[05:13:00] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[05:13:00] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[05:13:00] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[05:13:00] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[05:13:00] ========== drm_test_get_tv_mode_from_name_valid  ===========
[05:13:00] [PASSED] NTSC
[05:13:00] [PASSED] NTSC-443
[05:13:00] [PASSED] NTSC-J
[05:13:00] [PASSED] PAL
[05:13:00] [PASSED] PAL-M
[05:13:00] [PASSED] PAL-N
[05:13:00] [PASSED] SECAM
[05:13:00] [PASSED] Mono
[05:13:00] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[05:13:00] [PASSED] drm_test_get_tv_mode_from_name_truncated
[05:13:00] ============ [PASSED] drm_get_tv_mode_from_name ============
[05:13:00] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[05:13:00] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[05:13:00] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[05:13:00] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[05:13:00] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[05:13:00] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[05:13:00] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[05:13:00] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[05:13:00] [PASSED] VIC 96
[05:13:00] [PASSED] VIC 97
[05:13:00] [PASSED] VIC 101
[05:13:00] [PASSED] VIC 102
[05:13:00] [PASSED] VIC 106
[05:13:00] [PASSED] VIC 107
[05:13:00] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[05:13:00] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[05:13:00] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[05:13:00] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[05:13:00] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[05:13:00] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[05:13:00] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[05:13:00] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[05:13:00] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[05:13:00] [PASSED] Automatic
[05:13:00] [PASSED] Full
[05:13:00] [PASSED] Limited 16:235
[05:13:00] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[05:13:00] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[05:13:00] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[05:13:00] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[05:13:00] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[05:13:00] [PASSED] RGB
[05:13:00] [PASSED] YUV 4:2:0
[05:13:00] [PASSED] YUV 4:2:2
[05:13:00] [PASSED] YUV 4:4:4
[05:13:00] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[05:13:00] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[05:13:00] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[05:13:00] ============= drm_damage_helper (21 subtests) ==============
[05:13:00] [PASSED] drm_test_damage_iter_no_damage
[05:13:00] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[05:13:00] [PASSED] drm_test_damage_iter_no_damage_src_moved
[05:13:00] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[05:13:00] [PASSED] drm_test_damage_iter_no_damage_not_visible
[05:13:00] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[05:13:00] [PASSED] drm_test_damage_iter_no_damage_no_fb
[05:13:00] [PASSED] drm_test_damage_iter_simple_damage
[05:13:00] [PASSED] drm_test_damage_iter_single_damage
[05:13:00] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[05:13:00] [PASSED] drm_test_damage_iter_single_damage_outside_src
[05:13:00] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[05:13:00] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[05:13:00] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[05:13:00] [PASSED] drm_test_damage_iter_single_damage_src_moved
[05:13:00] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[05:13:00] [PASSED] drm_test_damage_iter_damage
[05:13:00] [PASSED] drm_test_damage_iter_damage_one_intersect
[05:13:00] [PASSED] drm_test_damage_iter_damage_one_outside
[05:13:00] [PASSED] drm_test_damage_iter_damage_src_moved
[05:13:00] [PASSED] drm_test_damage_iter_damage_not_visible
[05:13:00] ================ [PASSED] drm_damage_helper ================
[05:13:00] ============== drm_dp_mst_helper (3 subtests) ==============
[05:13:00] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[05:13:00] [PASSED] Clock 154000 BPP 30 DSC disabled
[05:13:00] [PASSED] Clock 234000 BPP 30 DSC disabled
[05:13:00] [PASSED] Clock 297000 BPP 24 DSC disabled
[05:13:00] [PASSED] Clock 332880 BPP 24 DSC enabled
[05:13:00] [PASSED] Clock 324540 BPP 24 DSC enabled
[05:13:00] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[05:13:00] ============== drm_test_dp_mst_calc_pbn_div  ===============
[05:13:00] [PASSED] Link rate 2000000 lane count 4
[05:13:00] [PASSED] Link rate 2000000 lane count 2
[05:13:00] [PASSED] Link rate 2000000 lane count 1
[05:13:00] [PASSED] Link rate 1350000 lane count 4
[05:13:00] [PASSED] Link rate 1350000 lane count 2
[05:13:00] [PASSED] Link rate 1350000 lane count 1
[05:13:00] [PASSED] Link rate 1000000 lane count 4
[05:13:00] [PASSED] Link rate 1000000 lane count 2
[05:13:00] [PASSED] Link rate 1000000 lane count 1
[05:13:00] [PASSED] Link rate 810000 lane count 4
[05:13:00] [PASSED] Link rate 810000 lane count 2
[05:13:00] [PASSED] Link rate 810000 lane count 1
[05:13:00] [PASSED] Link rate 540000 lane count 4
[05:13:00] [PASSED] Link rate 540000 lane count 2
[05:13:00] [PASSED] Link rate 540000 lane count 1
[05:13:00] [PASSED] Link rate 270000 lane count 4
[05:13:00] [PASSED] Link rate 270000 lane count 2
[05:13:00] [PASSED] Link rate 270000 lane count 1
[05:13:00] [PASSED] Link rate 162000 lane count 4
[05:13:00] [PASSED] Link rate 162000 lane count 2
[05:13:00] [PASSED] Link rate 162000 lane count 1
[05:13:00] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[05:13:00] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[05:13:00] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[05:13:00] [PASSED] DP_POWER_UP_PHY with port number
[05:13:00] [PASSED] DP_POWER_DOWN_PHY with port number
[05:13:00] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[05:13:00] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[05:13:00] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[05:13:00] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[05:13:00] [PASSED] DP_QUERY_PAYLOAD with port number
[05:13:00] [PASSED] DP_QUERY_PAYLOAD with VCPI
[05:13:00] [PASSED] DP_REMOTE_DPCD_READ with port number
[05:13:00] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[05:13:00] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[05:13:00] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[05:13:00] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[05:13:00] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[05:13:00] [PASSED] DP_REMOTE_I2C_READ with port number
[05:13:00] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[05:13:00] [PASSED] DP_REMOTE_I2C_READ with transactions array
[05:13:00] [PASSED] DP_REMOTE_I2C_WRITE with port number
[05:13:00] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[05:13:00] [PASSED] DP_REMOTE_I2C_WRITE with data array
[05:13:00] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[05:13:00] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[05:13:00] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[05:13:00] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[05:13:00] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[05:13:00] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[05:13:00] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[05:13:00] ================ [PASSED] drm_dp_mst_helper ================
[05:13:00] ================== drm_exec (7 subtests) ===================
[05:13:00] [PASSED] sanitycheck
[05:13:00] [PASSED] test_lock
[05:13:00] [PASSED] test_lock_unlock
[05:13:00] [PASSED] test_duplicates
[05:13:00] [PASSED] test_prepare
[05:13:00] [PASSED] test_prepare_array
[05:13:00] [PASSED] test_multiple_loops
[05:13:00] ==================== [PASSED] drm_exec =====================
[05:13:00] =========== drm_format_helper_test (17 subtests) ===========
[05:13:00] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[05:13:00] [PASSED] single_pixel_source_buffer
[05:13:00] [PASSED] single_pixel_clip_rectangle
[05:13:00] [PASSED] well_known_colors
[05:13:00] [PASSED] destination_pitch
[05:13:00] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[05:13:00] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[05:13:00] [PASSED] single_pixel_source_buffer
[05:13:00] [PASSED] single_pixel_clip_rectangle
[05:13:00] [PASSED] well_known_colors
[05:13:00] [PASSED] destination_pitch
[05:13:00] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[05:13:00] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[05:13:00] [PASSED] single_pixel_source_buffer
[05:13:00] [PASSED] single_pixel_clip_rectangle
[05:13:00] [PASSED] well_known_colors
[05:13:00] [PASSED] destination_pitch
[05:13:00] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[05:13:00] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[05:13:00] [PASSED] single_pixel_source_buffer
[05:13:00] [PASSED] single_pixel_clip_rectangle
[05:13:00] [PASSED] well_known_colors
[05:13:00] [PASSED] destination_pitch
[05:13:00] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[05:13:00] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[05:13:00] [PASSED] single_pixel_source_buffer
[05:13:00] [PASSED] single_pixel_clip_rectangle
[05:13:00] [PASSED] well_known_colors
[05:13:00] [PASSED] destination_pitch
[05:13:00] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[05:13:00] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[05:13:00] [PASSED] single_pixel_source_buffer
[05:13:00] [PASSED] single_pixel_clip_rectangle
[05:13:00] [PASSED] well_known_colors
[05:13:00] [PASSED] destination_pitch
[05:13:00] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[05:13:00] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[05:13:00] [PASSED] single_pixel_source_buffer
[05:13:00] [PASSED] single_pixel_clip_rectangle
[05:13:00] [PASSED] well_known_colors
[05:13:00] [PASSED] destination_pitch
[05:13:00] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[05:13:00] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[05:13:00] [PASSED] single_pixel_source_buffer
[05:13:00] [PASSED] single_pixel_clip_rectangle
[05:13:00] [PASSED] well_known_colors
[05:13:00] [PASSED] destination_pitch
[05:13:00] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[05:13:00] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[05:13:00] [PASSED] single_pixel_source_buffer
[05:13:00] [PASSED] single_pixel_clip_rectangle
[05:13:00] [PASSED] well_known_colors
[05:13:00] [PASSED] destination_pitch
[05:13:00] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[05:13:00] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[05:13:00] [PASSED] single_pixel_source_buffer
[05:13:00] [PASSED] single_pixel_clip_rectangle
[05:13:00] [PASSED] well_known_colors
[05:13:00] [PASSED] destination_pitch
[05:13:00] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[05:13:00] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[05:13:00] [PASSED] single_pixel_source_buffer
[05:13:00] [PASSED] single_pixel_clip_rectangle
[05:13:00] [PASSED] well_known_colors
[05:13:00] [PASSED] destination_pitch
[05:13:00] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[05:13:00] ============== drm_test_fb_xrgb8888_to_mono  ===============
[05:13:00] [PASSED] single_pixel_source_buffer
[05:13:00] [PASSED] single_pixel_clip_rectangle
[05:13:00] [PASSED] well_known_colors
[05:13:00] [PASSED] destination_pitch
[05:13:00] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[05:13:00] ==================== drm_test_fb_swab  =====================
[05:13:00] [PASSED] single_pixel_source_buffer
[05:13:00] [PASSED] single_pixel_clip_rectangle
[05:13:00] [PASSED] well_known_colors
[05:13:00] [PASSED] destination_pitch
[05:13:00] ================ [PASSED] drm_test_fb_swab =================
[05:13:00] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[05:13:00] [PASSED] single_pixel_source_buffer
[05:13:00] [PASSED] single_pixel_clip_rectangle
[05:13:00] [PASSED] well_known_colors
[05:13:00] [PASSED] destination_pitch
[05:13:00] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[05:13:00] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[05:13:00] [PASSED] single_pixel_source_buffer
[05:13:00] [PASSED] single_pixel_clip_rectangle
[05:13:00] [PASSED] well_known_colors
[05:13:00] [PASSED] destination_pitch
[05:13:00] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[05:13:00] ================= drm_test_fb_clip_offset  =================
[05:13:00] [PASSED] pass through
[05:13:00] [PASSED] horizontal offset
[05:13:00] [PASSED] vertical offset
[05:13:00] [PASSED] horizontal and vertical offset
[05:13:00] [PASSED] horizontal offset (custom pitch)
[05:13:00] [PASSED] vertical offset (custom pitch)
[05:13:00] [PASSED] horizontal and vertical offset (custom pitch)
[05:13:00] ============= [PASSED] drm_test_fb_clip_offset =============
[05:13:00] =================== drm_test_fb_memcpy  ====================
[05:13:00] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[05:13:00] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[05:13:00] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[05:13:00] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[05:13:00] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[05:13:00] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[05:13:00] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[05:13:00] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[05:13:00] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[05:13:00] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[05:13:00] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[05:13:00] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[05:13:00] =============== [PASSED] drm_test_fb_memcpy ================
[05:13:00] ============= [PASSED] drm_format_helper_test ==============
[05:13:00] ================= drm_format (18 subtests) =================
[05:13:00] [PASSED] drm_test_format_block_width_invalid
[05:13:00] [PASSED] drm_test_format_block_width_one_plane
[05:13:00] [PASSED] drm_test_format_block_width_two_plane
[05:13:00] [PASSED] drm_test_format_block_width_three_plane
[05:13:00] [PASSED] drm_test_format_block_width_tiled
[05:13:00] [PASSED] drm_test_format_block_height_invalid
[05:13:00] [PASSED] drm_test_format_block_height_one_plane
[05:13:00] [PASSED] drm_test_format_block_height_two_plane
[05:13:00] [PASSED] drm_test_format_block_height_three_plane
[05:13:00] [PASSED] drm_test_format_block_height_tiled
[05:13:00] [PASSED] drm_test_format_min_pitch_invalid
[05:13:00] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[05:13:00] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[05:13:00] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[05:13:00] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[05:13:00] [PASSED] drm_test_format_min_pitch_two_plane
[05:13:00] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[05:13:00] [PASSED] drm_test_format_min_pitch_tiled
[05:13:00] =================== [PASSED] drm_format ====================
[05:13:00] ============== drm_framebuffer (10 subtests) ===============
[05:13:00] ========== drm_test_framebuffer_check_src_coords  ==========
[05:13:00] [PASSED] Success: source fits into fb
[05:13:00] [PASSED] Fail: overflowing fb with x-axis coordinate
[05:13:00] [PASSED] Fail: overflowing fb with y-axis coordinate
[05:13:00] [PASSED] Fail: overflowing fb with source width
[05:13:00] [PASSED] Fail: overflowing fb with source height
[05:13:00] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[05:13:00] [PASSED] drm_test_framebuffer_cleanup
[05:13:00] =============== drm_test_framebuffer_create  ===============
[05:13:00] [PASSED] ABGR8888 normal sizes
[05:13:00] [PASSED] ABGR8888 max sizes
[05:13:00] [PASSED] ABGR8888 pitch greater than min required
[05:13:00] [PASSED] ABGR8888 pitch less than min required
[05:13:00] [PASSED] ABGR8888 Invalid width
[05:13:00] [PASSED] ABGR8888 Invalid buffer handle
[05:13:00] [PASSED] No pixel format
[05:13:00] [PASSED] ABGR8888 Width 0
[05:13:00] [PASSED] ABGR8888 Height 0
[05:13:00] [PASSED] ABGR8888 Out of bound height * pitch combination
[05:13:00] [PASSED] ABGR8888 Large buffer offset
[05:13:00] [PASSED] ABGR8888 Buffer offset for inexistent plane
[05:13:00] [PASSED] ABGR8888 Invalid flag
[05:13:00] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[05:13:00] [PASSED] ABGR8888 Valid buffer modifier
[05:13:00] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[05:13:00] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[05:13:00] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[05:13:00] [PASSED] NV12 Normal sizes
[05:13:00] [PASSED] NV12 Max sizes
[05:13:00] [PASSED] NV12 Invalid pitch
[05:13:00] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[05:13:00] [PASSED] NV12 different  modifier per-plane
[05:13:00] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[05:13:00] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[05:13:00] [PASSED] NV12 Modifier for inexistent plane
[05:13:00] [PASSED] NV12 Handle for inexistent plane
[05:13:00] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[05:13:00] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[05:13:00] [PASSED] YVU420 Normal sizes
[05:13:00] [PASSED] YVU420 Max sizes
[05:13:00] [PASSED] YVU420 Invalid pitch
[05:13:00] [PASSED] YVU420 Different pitches
[05:13:00] [PASSED] YVU420 Different buffer offsets/pitches
[05:13:00] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[05:13:00] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[05:13:00] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[05:13:00] [PASSED] YVU420 Valid modifier
[05:13:00] [PASSED] YVU420 Different modifiers per plane
[05:13:00] [PASSED] YVU420 Modifier for inexistent plane
[05:13:00] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[05:13:00] [PASSED] X0L2 Normal sizes
[05:13:00] [PASSED] X0L2 Max sizes
[05:13:00] [PASSED] X0L2 Invalid pitch
[05:13:00] [PASSED] X0L2 Pitch greater than minimum required
[05:13:00] [PASSED] X0L2 Handle for inexistent plane
[05:13:00] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[05:13:00] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[05:13:00] [PASSED] X0L2 Valid modifier
[05:13:00] [PASSED] X0L2 Modifier for inexistent plane
[05:13:00] =========== [PASSED] drm_test_framebuffer_create ===========
[05:13:00] [PASSED] drm_test_framebuffer_free
[05:13:00] [PASSED] drm_test_framebuffer_init
[05:13:00] [PASSED] drm_test_framebuffer_init_bad_format
[05:13:00] [PASSED] drm_test_framebuffer_init_dev_mismatch
[05:13:00] [PASSED] drm_test_framebuffer_lookup
[05:13:00] [PASSED] drm_test_framebuffer_lookup_inexistent
[05:13:00] [PASSED] drm_test_framebuffer_modifiers_not_supported
[05:13:00] ================= [PASSED] drm_framebuffer =================
[05:13:00] ================ drm_gem_shmem (8 subtests) ================
[05:13:00] [PASSED] drm_gem_shmem_test_obj_create
[05:13:00] [PASSED] drm_gem_shmem_test_obj_create_private
[05:13:00] [PASSED] drm_gem_shmem_test_pin_pages
[05:13:00] [PASSED] drm_gem_shmem_test_vmap
[05:13:00] [PASSED] drm_gem_shmem_test_get_pages_sgt
[05:13:00] [PASSED] drm_gem_shmem_test_get_sg_table
[05:13:00] [PASSED] drm_gem_shmem_test_madvise
[05:13:00] [PASSED] drm_gem_shmem_test_purge
[05:13:00] ================== [PASSED] drm_gem_shmem ==================
[05:13:00] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[05:13:00] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[05:13:00] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[05:13:00] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[05:13:00] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[05:13:00] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[05:13:00] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[05:13:00] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[05:13:00] [PASSED] Automatic
[05:13:00] [PASSED] Full
[05:13:00] [PASSED] Limited 16:235
[05:13:00] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[05:13:00] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[05:13:00] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[05:13:00] [PASSED] drm_test_check_disable_connector
[05:13:00] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[05:13:00] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[05:13:00] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[05:13:00] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[05:13:00] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[05:13:00] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[05:13:00] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[05:13:00] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[05:13:00] [PASSED] drm_test_check_output_bpc_dvi
[05:13:00] [PASSED] drm_test_check_output_bpc_format_vic_1
[05:13:00] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[05:13:00] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[05:13:00] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[05:13:00] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[05:13:00] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[05:13:00] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[05:13:00] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[05:13:00] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[05:13:00] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[05:13:00] [PASSED] drm_test_check_broadcast_rgb_value
[05:13:00] [PASSED] drm_test_check_bpc_8_value
[05:13:00] [PASSED] drm_test_check_bpc_10_value
[05:13:00] [PASSED] drm_test_check_bpc_12_value
[05:13:00] [PASSED] drm_test_check_format_value
[05:13:00] [PASSED] drm_test_check_tmds_char_value
[05:13:00] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[05:13:00] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[05:13:00] [PASSED] drm_test_check_mode_valid
[05:13:00] [PASSED] drm_test_check_mode_valid_reject
[05:13:00] [PASSED] drm_test_check_mode_valid_reject_rate
[05:13:00] [PASSED] drm_test_check_mode_valid_reject_max_clock
[05:13:00] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[05:13:00] ================= drm_managed (2 subtests) =================
[05:13:00] [PASSED] drm_test_managed_release_action
[05:13:00] [PASSED] drm_test_managed_run_action
[05:13:00] =================== [PASSED] drm_managed ===================
[05:13:00] =================== drm_mm (6 subtests) ====================
[05:13:00] [PASSED] drm_test_mm_init
[05:13:00] [PASSED] drm_test_mm_debug
[05:13:00] [PASSED] drm_test_mm_align32
[05:13:00] [PASSED] drm_test_mm_align64
[05:13:00] [PASSED] drm_test_mm_lowest
[05:13:00] [PASSED] drm_test_mm_highest
[05:13:00] ===================== [PASSED] drm_mm ======================
[05:13:00] ============= drm_modes_analog_tv (5 subtests) =============
[05:13:00] [PASSED] drm_test_modes_analog_tv_mono_576i
[05:13:00] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[05:13:00] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[05:13:00] [PASSED] drm_test_modes_analog_tv_pal_576i
[05:13:00] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[05:13:00] =============== [PASSED] drm_modes_analog_tv ===============
[05:13:00] ============== drm_plane_helper (2 subtests) ===============
[05:13:00] =============== drm_test_check_plane_state  ================
[05:13:00] [PASSED] clipping_simple
[05:13:00] [PASSED] clipping_rotate_reflect
[05:13:00] [PASSED] positioning_simple
[05:13:00] [PASSED] upscaling
[05:13:00] [PASSED] downscaling
[05:13:00] [PASSED] rounding1
[05:13:00] [PASSED] rounding2
[05:13:00] [PASSED] rounding3
[05:13:00] [PASSED] rounding4
[05:13:00] =========== [PASSED] drm_test_check_plane_state ============
[05:13:00] =========== drm_test_check_invalid_plane_state  ============
[05:13:00] [PASSED] positioning_invalid
[05:13:00] [PASSED] upscaling_invalid
[05:13:00] [PASSED] downscaling_invalid
[05:13:00] ======= [PASSED] drm_test_check_invalid_plane_state ========
[05:13:00] ================ [PASSED] drm_plane_helper =================
[05:13:00] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[05:13:00] ====== drm_test_connector_helper_tv_get_modes_check  =======
[05:13:00] [PASSED] None
[05:13:00] [PASSED] PAL
[05:13:00] [PASSED] NTSC
[05:13:00] [PASSED] Both, NTSC Default
[05:13:00] [PASSED] Both, PAL Default
[05:13:00] [PASSED] Both, NTSC Default, with PAL on command-line
[05:13:00] [PASSED] Both, PAL Default, with NTSC on command-line
[05:13:00] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[05:13:00] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[05:13:00] ================== drm_rect (9 subtests) ===================
[05:13:00] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[05:13:00] [PASSED] drm_test_rect_clip_scaled_not_clipped
[05:13:00] [PASSED] drm_test_rect_clip_scaled_clipped
[05:13:00] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[05:13:00] ================= drm_test_rect_intersect  =================
[05:13:00] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[05:13:00] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[05:13:00] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[05:13:00] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[05:13:00] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[05:13:00] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[05:13:00] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[05:13:00] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[05:13:00] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[05:13:00] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[05:13:00] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[05:13:00] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[05:13:00] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[05:13:00] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[05:13:00] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[05:13:00] ============= [PASSED] drm_test_rect_intersect =============
[05:13:00] ================ drm_test_rect_calc_hscale  ================
[05:13:00] [PASSED] normal use
[05:13:00] [PASSED] out of max range
[05:13:00] [PASSED] out of min range
[05:13:00] [PASSED] zero dst
[05:13:00] [PASSED] negative src
[05:13:00] [PASSED] negative dst
[05:13:00] ============ [PASSED] drm_test_rect_calc_hscale ============
[05:13:00] ================ drm_test_rect_calc_vscale  ================
[05:13:00] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[05:13:00] [PASSED] out of max range
[05:13:00] [PASSED] out of min range
[05:13:00] [PASSED] zero dst
[05:13:00] [PASSED] negative src
[05:13:00] [PASSED] negative dst
[05:13:00] ============ [PASSED] drm_test_rect_calc_vscale ============
[05:13:00] ================== drm_test_rect_rotate  ===================
[05:13:00] [PASSED] reflect-x
[05:13:00] [PASSED] reflect-y
[05:13:00] [PASSED] rotate-0
[05:13:00] [PASSED] rotate-90
[05:13:00] [PASSED] rotate-180
[05:13:00] [PASSED] rotate-270
[05:13:00] ============== [PASSED] drm_test_rect_rotate ===============
[05:13:00] ================ drm_test_rect_rotate_inv  =================
[05:13:00] [PASSED] reflect-x
[05:13:00] [PASSED] reflect-y
[05:13:00] [PASSED] rotate-0
[05:13:00] [PASSED] rotate-90
[05:13:00] [PASSED] rotate-180
[05:13:00] [PASSED] rotate-270
[05:13:00] ============ [PASSED] drm_test_rect_rotate_inv =============
[05:13:00] ==================== [PASSED] drm_rect =====================
[05:13:00] ============ drm_sysfb_modeset_test (1 subtest) ============
[05:13:00] ============ drm_test_sysfb_build_fourcc_list  =============
[05:13:00] [PASSED] no native formats
[05:13:00] [PASSED] XRGB8888 as native format
[05:13:00] [PASSED] remove duplicates
[05:13:00] [PASSED] convert alpha formats
[05:13:00] [PASSED] random formats
[05:13:00] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[05:13:00] ============= [PASSED] drm_sysfb_modeset_test ==============
[05:13:00] ============================================================
[05:13:00] Testing complete. Ran 622 tests: passed: 622
[05:13:00] Elapsed time: 31.774s total, 1.657s configuring, 29.600s building, 0.469s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[05:13:00] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:13:01] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[05:13:11] Starting KUnit Kernel (1/1)...
[05:13:11] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:13:11] ================= ttm_device (5 subtests) ==================
[05:13:11] [PASSED] ttm_device_init_basic
[05:13:11] [PASSED] ttm_device_init_multiple
[05:13:11] [PASSED] ttm_device_fini_basic
[05:13:11] [PASSED] ttm_device_init_no_vma_man
[05:13:11] ================== ttm_device_init_pools  ==================
[05:13:11] [PASSED] No DMA allocations, no DMA32 required
[05:13:11] [PASSED] DMA allocations, DMA32 required
[05:13:11] [PASSED] No DMA allocations, DMA32 required
[05:13:11] [PASSED] DMA allocations, no DMA32 required
[05:13:11] ============== [PASSED] ttm_device_init_pools ==============
[05:13:11] =================== [PASSED] ttm_device ====================
[05:13:11] ================== ttm_pool (8 subtests) ===================
[05:13:11] ================== ttm_pool_alloc_basic  ===================
[05:13:11] [PASSED] One page
[05:13:11] [PASSED] More than one page
[05:13:11] [PASSED] Above the allocation limit
[05:13:11] [PASSED] One page, with coherent DMA mappings enabled
[05:13:11] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:13:11] ============== [PASSED] ttm_pool_alloc_basic ===============
[05:13:11] ============== ttm_pool_alloc_basic_dma_addr  ==============
[05:13:11] [PASSED] One page
[05:13:11] [PASSED] More than one page
[05:13:11] [PASSED] Above the allocation limit
[05:13:11] [PASSED] One page, with coherent DMA mappings enabled
[05:13:11] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:13:11] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[05:13:11] [PASSED] ttm_pool_alloc_order_caching_match
[05:13:11] [PASSED] ttm_pool_alloc_caching_mismatch
[05:13:11] [PASSED] ttm_pool_alloc_order_mismatch
[05:13:11] [PASSED] ttm_pool_free_dma_alloc
[05:13:11] [PASSED] ttm_pool_free_no_dma_alloc
[05:13:11] [PASSED] ttm_pool_fini_basic
[05:13:11] ==================== [PASSED] ttm_pool =====================
[05:13:11] ================ ttm_resource (8 subtests) =================
[05:13:11] ================= ttm_resource_init_basic  =================
[05:13:11] [PASSED] Init resource in TTM_PL_SYSTEM
[05:13:11] [PASSED] Init resource in TTM_PL_VRAM
[05:13:11] [PASSED] Init resource in a private placement
[05:13:11] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[05:13:11] ============= [PASSED] ttm_resource_init_basic =============
[05:13:11] [PASSED] ttm_resource_init_pinned
[05:13:11] [PASSED] ttm_resource_fini_basic
[05:13:11] [PASSED] ttm_resource_manager_init_basic
[05:13:11] [PASSED] ttm_resource_manager_usage_basic
[05:13:11] [PASSED] ttm_resource_manager_set_used_basic
[05:13:11] [PASSED] ttm_sys_man_alloc_basic
[05:13:11] [PASSED] ttm_sys_man_free_basic
[05:13:11] ================== [PASSED] ttm_resource ===================
[05:13:11] =================== ttm_tt (15 subtests) ===================
[05:13:11] ==================== ttm_tt_init_basic  ====================
[05:13:11] [PASSED] Page-aligned size
[05:13:11] [PASSED] Extra pages requested
[05:13:11] ================ [PASSED] ttm_tt_init_basic ================
[05:13:11] [PASSED] ttm_tt_init_misaligned
[05:13:11] [PASSED] ttm_tt_fini_basic
[05:13:11] [PASSED] ttm_tt_fini_sg
[05:13:11] [PASSED] ttm_tt_fini_shmem
[05:13:11] [PASSED] ttm_tt_create_basic
[05:13:11] [PASSED] ttm_tt_create_invalid_bo_type
[05:13:11] [PASSED] ttm_tt_create_ttm_exists
[05:13:11] [PASSED] ttm_tt_create_failed
[05:13:11] [PASSED] ttm_tt_destroy_basic
[05:13:11] [PASSED] ttm_tt_populate_null_ttm
[05:13:11] [PASSED] ttm_tt_populate_populated_ttm
[05:13:11] [PASSED] ttm_tt_unpopulate_basic
[05:13:11] [PASSED] ttm_tt_unpopulate_empty_ttm
[05:13:11] [PASSED] ttm_tt_swapin_basic
[05:13:11] ===================== [PASSED] ttm_tt ======================
[05:13:11] =================== ttm_bo (14 subtests) ===================
[05:13:11] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[05:13:11] [PASSED] Cannot be interrupted and sleeps
[05:13:11] [PASSED] Cannot be interrupted, locks straight away
[05:13:11] [PASSED] Can be interrupted, sleeps
[05:13:11] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[05:13:11] [PASSED] ttm_bo_reserve_locked_no_sleep
[05:13:11] [PASSED] ttm_bo_reserve_no_wait_ticket
[05:13:11] [PASSED] ttm_bo_reserve_double_resv
[05:13:11] [PASSED] ttm_bo_reserve_interrupted
[05:13:11] [PASSED] ttm_bo_reserve_deadlock
[05:13:11] [PASSED] ttm_bo_unreserve_basic
[05:13:11] [PASSED] ttm_bo_unreserve_pinned
[05:13:11] [PASSED] ttm_bo_unreserve_bulk
[05:13:11] [PASSED] ttm_bo_fini_basic
[05:13:11] [PASSED] ttm_bo_fini_shared_resv
[05:13:11] [PASSED] ttm_bo_pin_basic
[05:13:11] [PASSED] ttm_bo_pin_unpin_resource
[05:13:11] [PASSED] ttm_bo_multiple_pin_one_unpin
[05:13:11] ===================== [PASSED] ttm_bo ======================
[05:13:11] ============== ttm_bo_validate (21 subtests) ===============
[05:13:11] ============== ttm_bo_init_reserved_sys_man  ===============
[05:13:11] [PASSED] Buffer object for userspace
[05:13:11] [PASSED] Kernel buffer object
[05:13:11] [PASSED] Shared buffer object
[05:13:11] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[05:13:11] ============== ttm_bo_init_reserved_mock_man  ==============
[05:13:11] [PASSED] Buffer object for userspace
[05:13:11] [PASSED] Kernel buffer object
[05:13:11] [PASSED] Shared buffer object
[05:13:11] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[05:13:11] [PASSED] ttm_bo_init_reserved_resv
[05:13:11] ================== ttm_bo_validate_basic  ==================
[05:13:11] [PASSED] Buffer object for userspace
[05:13:11] [PASSED] Kernel buffer object
[05:13:11] [PASSED] Shared buffer object
[05:13:11] ============== [PASSED] ttm_bo_validate_basic ==============
[05:13:11] [PASSED] ttm_bo_validate_invalid_placement
[05:13:11] ============= ttm_bo_validate_same_placement  ==============
[05:13:11] [PASSED] System manager
[05:13:11] [PASSED] VRAM manager
[05:13:11] ========= [PASSED] ttm_bo_validate_same_placement ==========
[05:13:11] [PASSED] ttm_bo_validate_failed_alloc
[05:13:11] [PASSED] ttm_bo_validate_pinned
[05:13:11] [PASSED] ttm_bo_validate_busy_placement
[05:13:11] ================ ttm_bo_validate_multihop  =================
[05:13:11] [PASSED] Buffer object for userspace
[05:13:11] [PASSED] Kernel buffer object
[05:13:11] [PASSED] Shared buffer object
[05:13:11] ============ [PASSED] ttm_bo_validate_multihop =============
[05:13:11] ========== ttm_bo_validate_no_placement_signaled  ==========
[05:13:11] [PASSED] Buffer object in system domain, no page vector
[05:13:11] [PASSED] Buffer object in system domain with an existing page vector
[05:13:11] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[05:13:11] ======== ttm_bo_validate_no_placement_not_signaled  ========
[05:13:11] [PASSED] Buffer object for userspace
[05:13:11] [PASSED] Kernel buffer object
[05:13:11] [PASSED] Shared buffer object
[05:13:11] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[05:13:11] [PASSED] ttm_bo_validate_move_fence_signaled
[05:13:11] ========= ttm_bo_validate_move_fence_not_signaled  =========
[05:13:11] [PASSED] Waits for GPU
[05:13:11] [PASSED] Tries to lock straight away
[05:13:11] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[05:13:11] [PASSED] ttm_bo_validate_happy_evict
[05:13:11] [PASSED] ttm_bo_validate_all_pinned_evict
[05:13:11] [PASSED] ttm_bo_validate_allowed_only_evict
[05:13:11] [PASSED] ttm_bo_validate_deleted_evict
[05:13:11] [PASSED] ttm_bo_validate_busy_domain_evict
[05:13:11] [PASSED] ttm_bo_validate_evict_gutting
[05:13:11] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[05:13:11] ================= [PASSED] ttm_bo_validate =================
[05:13:11] ============================================================
[05:13:11] Testing complete. Ran 101 tests: passed: 101
[05:13:11] Elapsed time: 11.086s total, 1.628s configuring, 9.242s building, 0.177s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

Re: [PATCH v2 19/22] drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx

[Lucas De Marchi]

On Wed, Oct 15, 2025 at 05:07:42PM -0700, Matt Roper wrote:
>On Wed, Oct 15, 2025 at 03:06:34PM -0700, Lucas De Marchi wrote:
>> Current implementation of compute walker has dependency on GPU/SW Stack
>> which requires SW/UMD to wait for event from KMD to indicate
>> PIPE_CONTROL interrupt was done. This created latency on SW stack.
>>
>> This feature adds support to generate completion interrupt from GPGPU
>> walker which does not support MSIx and avoid software using Pipe control
>> drain/idle latency.
>>
>> Suggested-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>> Signed-off-by: S A Muqthyar Ahmed <syed.abdul.muqthyar.ahmed@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> v2: Rebase on split mask per engine class
>> ---
>>  drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
>>  drivers/gpu/drm/xe/xe_irq.c           | 6 ++++++
>>  2 files changed, 7 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
>> index 7c2a3a1401424..9c46b5fb81412 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
>> @@ -82,6 +82,7 @@
>>  #define   GSC_ER_COMPLETE			REG_BIT(5)
>>  #define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)
>>  #define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
>> +#define   GT_COMPUTE_WALKER_INTERRUPT		REG_BIT(2)
>>  #define   GT_RENDER_USER_INTERRUPT		REG_BIT(0)
>>
>>  /* irqs for OTHER_KCR_INSTANCE */
>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>> index 103804546b280..ac5524cbe4b9a 100644
>> --- a/drivers/gpu/drm/xe/xe_irq.c
>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>> @@ -149,6 +149,12 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>>  	if (xe_device_uc_enabled(xe)) {
>>  		common_mask = GT_RENDER_USER_INTERRUPT |
>>  			      GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
>> +
>> +		/* Enable Compute Walker Interrupt for non-MSIX platforms */
>> +		if (GRAPHICS_VERx100(xe) >= 3511 && !xe_device_has_msix(xe)) {
>> +			rcs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
>> +			ccs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
>> +		}
>
>It probably doesn't matter since our execlist support isn't functional
>and we only really support GuC-based submission, but technically
>shouldn't this be outside the 'uc_enabled' check so that we'd also get
>these interrupts if we tried to use execlist submission?
>
>BTW, is there more support for this coming in future patches?  Without
>MSI-X, what's the mechanism by which userspace finds out this interrupt
>has fired?  We're unmasking/enabling the interrupt here, but I don't see
>how anything happens once the interrupts start showing up.

Himal / Syed: any detail missing here?

Yes, AFAIU we are still missing the change in the irq handler to get the
notification and the mechanism on exec queue creation for registration.

Lucas De Marchi
>
>
>Matt
>
>>  	} else {
>>  		common_mask = GT_RENDER_USER_INTERRUPT |
>>  			      GT_CS_MASTER_ERROR_INTERRUPT |
>>
>> --
>> 2.51.0
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

✗ Xe.CI.BAT: failure for drm/xe: Add Xe3p support (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4025 bytes --]

== Series Details ==

Series: drm/xe: Add Xe3p support (rev2)
URL   : https://patchwork.freedesktop.org/series/155866/
State : failure

== Summary ==

CI Bug Log - changes from xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8_BAT -> xe-pw-155866v2_BAT
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-155866v2_BAT absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-155866v2_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 10)
------------------------------

  Missing    (1): bat-adlp-vm 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-155866v2_BAT:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_module_load@load:
    - bat-ptl-2:          [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/bat-ptl-2/igt@xe_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/bat-ptl-2/igt@xe_module_load@load.html
    - bat-dg2-oem2:       [PASS][3] -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/bat-dg2-oem2/igt@xe_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/bat-dg2-oem2/igt@xe_module_load@load.html
    - bat-atsm-2:         [PASS][5] -> [ABORT][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/bat-atsm-2/igt@xe_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/bat-atsm-2/igt@xe_module_load@load.html
    - bat-ptl-1:          [PASS][7] -> [ABORT][8]
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/bat-ptl-1/igt@xe_module_load@load.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/bat-ptl-1/igt@xe_module_load@load.html
    - bat-lnl-1:          [PASS][9] -> [ABORT][10]
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/bat-lnl-1/igt@xe_module_load@load.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/bat-lnl-1/igt@xe_module_load@load.html
    - bat-bmg-2:          [PASS][11] -> [ABORT][12]
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/bat-bmg-2/igt@xe_module_load@load.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/bat-bmg-2/igt@xe_module_load@load.html
    - bat-bmg-1:          [PASS][13] -> [ABORT][14]
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/bat-bmg-1/igt@xe_module_load@load.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/bat-bmg-1/igt@xe_module_load@load.html
    - bat-adlp-7:         [PASS][15] -> [ABORT][16]
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/bat-adlp-7/igt@xe_module_load@load.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/bat-adlp-7/igt@xe_module_load@load.html
    - bat-lnl-2:          [PASS][17] -> [ABORT][18]
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/bat-lnl-2/igt@xe_module_load@load.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/bat-lnl-2/igt@xe_module_load@load.html

  


Build changes
-------------

  * Linux: xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8 -> xe-pw-155866v2

  IGT_8587: 8587
  xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8: 7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8
  xe-pw-155866v2: 155866v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/index.html

[-- Attachment #2: Type: text/html, Size: 4656 bytes --]

RE: [PATCH v2 19/22] drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx

[Muqthyar Ahmed, Syed Abdul]

> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@intel.com>
> Sent: Thursday, October 16, 2025 11:03 AM
> To: Roper, Matthew D <matthew.d.roper@intel.com>
> Cc: intel-xe@lists.freedesktop.org; Chauhan, Shekhar
> <shekhar.chauhan@intel.com>; Vivekanandan, Balasubramani
> <balasubramani.vivekanandan@intel.com>; Upadhyay, Tejas
> <tejas.upadhyay@intel.com>; Ghimiray, Himal Prasad
> <himal.prasad.ghimiray@intel.com>; Muqthyar Ahmed, Syed Abdul
> <syed.abdul.muqthyar.ahmed@intel.com>
> Subject: Re: [PATCH v2 19/22] drm/xe/xe3p_xpc: Add support for compute
> walker for non-MSIx
> 
> On Wed, Oct 15, 2025 at 05:07:42PM -0700, Matt Roper wrote:
> >On Wed, Oct 15, 2025 at 03:06:34PM -0700, Lucas De Marchi wrote:
> >> Current implementation of compute walker has dependency on GPU/SW
> >> Stack which requires SW/UMD to wait for event from KMD to indicate
> >> PIPE_CONTROL interrupt was done. This created latency on SW stack.
> >>
> >> This feature adds support to generate completion interrupt from GPGPU
> >> walker which does not support MSIx and avoid software using Pipe
> >> control drain/idle latency.
> >>
> >> Suggested-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> >> Signed-off-by: S A Muqthyar Ahmed
> >> <syed.abdul.muqthyar.ahmed@intel.com>
> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >> ---
> >> v2: Rebase on split mask per engine class
> >> ---
> >>  drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
> >>  drivers/gpu/drm/xe/xe_irq.c           | 6 ++++++
> >>  2 files changed, 7 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> >> b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> >> index 7c2a3a1401424..9c46b5fb81412 100644
> >> --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> >> +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> >> @@ -82,6 +82,7 @@
> >>  #define   GSC_ER_COMPLETE			REG_BIT(5)
> >>  #define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)
> >>  #define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
> >> +#define   GT_COMPUTE_WALKER_INTERRUPT		REG_BIT(2)
> >>  #define   GT_RENDER_USER_INTERRUPT		REG_BIT(0)
> >>
> >>  /* irqs for OTHER_KCR_INSTANCE */
> >> diff --git a/drivers/gpu/drm/xe/xe_irq.c
> >> b/drivers/gpu/drm/xe/xe_irq.c index 103804546b280..ac5524cbe4b9a
> >> 100644
> >> --- a/drivers/gpu/drm/xe/xe_irq.c
> >> +++ b/drivers/gpu/drm/xe/xe_irq.c
> >> @@ -149,6 +149,12 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
> >>  	if (xe_device_uc_enabled(xe)) {
> >>  		common_mask = GT_RENDER_USER_INTERRUPT |
> >>  			      GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
> >> +
> >> +		/* Enable Compute Walker Interrupt for non-MSIX platforms
> */
> >> +		if (GRAPHICS_VERx100(xe) >= 3511 &&
> !xe_device_has_msix(xe)) {
> >> +			rcs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
> >> +			ccs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
> >> +		}
> >
> >It probably doesn't matter since our execlist support isn't functional
> >and we only really support GuC-based submission, but technically
> >shouldn't this be outside the 'uc_enabled' check so that we'd also get
> >these interrupts if we tried to use execlist submission?
> >
> >BTW, is there more support for this coming in future patches?  Without
> >MSI-X, what's the mechanism by which userspace finds out this interrupt
> >has fired?  We're unmasking/enabling the interrupt here, but I don't
> >see how anything happens once the interrupts start showing up.
> 
> Himal / Syed: any detail missing here?
> 
> Yes, AFAIU we are still missing the change in the irq handler to get the
> notification and the mechanism on exec queue creation for registration.
> 

For exec queue creation control can only be supported on  platform supporting MSIX . 
This is for non-MSIX/MSI. 
For this irq handler just need to wake up waiting kernel or user thread and that is happening for all irq lines in handler so nothing special need to be handled.

> Lucas De Marchi
> >
> >
> >Matt
> >
> >>  	} else {
> >>  		common_mask = GT_RENDER_USER_INTERRUPT |
> >>  			      GT_CS_MASTER_ERROR_INTERRUPT |
> >>
> >> --
> >> 2.51.0
> >>
> >
> >--
> >Matt Roper
> >Graphics Software Engineer
> >Linux GPU Platform Enablement
> >Intel Corporation

Re: [PATCH v2 16/22] drm/xe/xe3p_xpc: Add MCR steering

[Gustavo Sousa]

Quoting Lucas De Marchi (2025-10-15 19:06:31-03:00)
>From: Matt Roper <matthew.d.roper@intel.com>
>
>Xe3p_XPC's steering has a few changes from Xe3.  Aside from
>minor changes to the XeCore (the new name for what used to be "DSS") and
>INSTANCE0 tables, different rules apply to different subranges of type
>"GAM."  Certain GAM subranges require steering to grp/instance (0,0)
>(and thus use the INSTANCE0 table), while others require special
>steering to (1,0) instead.  Similarly, there are multiple classes of
>"PSMI" steering, with some requiring steering to (0,0) while others
>require (19,0).
>
>FIXME: There's an "L3BANK" range listed in the bspec that needs
>clarification.

I think we also have a NODE range that is also missing termination
details.  I think a TODO/FIXME in the code for those two types of range
would help reminind ourselves about the need to complete the tables.

For the ranges added in this patch, I checked and they match the Bspec,
so:

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

>
>Bspec: 74418
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>---
> drivers/gpu/drm/xe/xe_gt_mcr.c   | 56 ++++++++++++++++++++++++++++++++++++++--
> drivers/gpu/drm/xe/xe_gt_types.h | 15 +++++++++++
> 2 files changed, 69 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
>index e1a2b38fc2a86..e5506ec28e147 100644
>--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
>+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
>@@ -169,6 +169,15 @@ static const struct xe_mmio_range xelpg_dss_steering_table[] = {
>         {},
> };
> 
>+static const struct xe_mmio_range xe3p_xpc_xecore_steering_table[] = {
>+        { 0x008140, 0x00817F },         /* SLICE, XeCore, SLICE */
>+        { 0x009480, 0x00955F },         /* SLICE, XeCore */
>+        { 0x00D800, 0x00D87F },                /* SLICE */
>+        { 0x00DC00, 0x00E9FF },         /* SLICE, rsvd, XeCore, rsvd, XeCore, rsvd, XeCore */
>+        { 0x013000, 0x0135FF },         /* XeCore, SLICE */
>+        {},
>+};
>+
> static const struct xe_mmio_range xelpmp_oaddrm_steering_table[] = {
>         { 0x393200, 0x39323F },
>         { 0x393400, 0x3934FF },
>@@ -247,6 +256,30 @@ static const struct xe_mmio_range xe3lpm_instance0_steering_table[] = {
>         {},
> };
> 
>+/*
>+ * Different "GAM" ranges have different rules; GAMWKRS, STLB, and GAMREQSTRM
>+ * range subtypes need to be steered to (1,0), while all other GAM subtypes
>+ * are steered to (0,0) and are included in the "INSTANCE0" table farther
>+ * down.
>+ */
>+static const struct xe_mmio_range xe3p_xpc_gam_grp1_steering_table[] = {
>+        { 0x004000, 0x004AFF },                /* GAMREQSTRM, rsvd, STLB, GAMWKRS, GAMREQSTRM */
>+        { 0x00F100, 0x00FFFF },                /* GAMWKRS */
>+        {},
>+};
>+
>+static const struct xe_mmio_range xe3p_xpc_psmi_grp19_steering_table[] = {
>+        { 0x00B500, 0x00B5FF },
>+        {},
>+};
>+
>+static const struct xe_mmio_range xe3p_xpc_instance0_steering_table[] = {
>+        { 0x00B600, 0x00B6FF },                /* PSMI0 */
>+        { 0x00C800, 0x00CFFF },                /* GAMCTRL */
>+        { 0x00F000, 0x00F0FF },                /* GAMCTRL */
>+        {},
>+};
>+
> static void init_steering_l3bank(struct xe_gt *gt)
> {
>         struct xe_mmio *mmio = &gt->mmio;
>@@ -419,6 +452,18 @@ static void init_steering_sqidi_psmi(struct xe_gt *gt)
>         gt->steering[SQIDI_PSMI].instance_target = select & 0x1;
> }
> 
>+static void init_steering_psmi(struct xe_gt *gt)
>+{
>+        gt->steering[PSMI19].group_target = 19;
>+        gt->steering[PSMI19].instance_target = 0;
>+}
>+
>+static void init_steering_gam1(struct xe_gt *gt)
>+{
>+        gt->steering[GAM1].group_target = 1;
>+        gt->steering[GAM1].instance_target = 0;
>+}
>+
> static const struct {
>         const char *name;
>         void (*init)(struct xe_gt *gt);
>@@ -426,9 +471,11 @@ static const struct {
>         [L3BANK] =        { "L3BANK",        init_steering_l3bank },
>         [MSLICE] =        { "MSLICE",        init_steering_mslice },
>         [LNCF] =        { "LNCF",        NULL }, /* initialized by mslice init */
>-        [DSS] =                { "DSS",        init_steering_dss },
>+        [DSS] =                { "DSS / XeCore", init_steering_dss },
>         [OADDRM] =        { "OADDRM / GPMXMT", init_steering_oaddrm },
>         [SQIDI_PSMI] =  { "SQIDI_PSMI", init_steering_sqidi_psmi },
>+        [PSMI19] =        { "PSMI[19]",        init_steering_psmi },
>+        [GAM1] =        { "GAMWKRS / STLB / GAMREQSTRM", init_steering_gam1 },
>         [INSTANCE0] =        { "INSTANCE 0",        NULL },
>         [IMPLICIT_STEERING] = { "IMPLICIT", NULL },
> };
>@@ -467,7 +514,12 @@ void xe_gt_mcr_init_early(struct xe_gt *gt)
>                         gt->steering[OADDRM].ranges = xelpmp_oaddrm_steering_table;
>                 }
>         } else {
>-                if (GRAPHICS_VER(xe) >= 20) {
>+                if (GRAPHICS_VERx100(xe) == 3511) {
>+                        gt->steering[DSS].ranges = xe3p_xpc_xecore_steering_table;
>+                        gt->steering[GAM1].ranges = xe3p_xpc_gam_grp1_steering_table;
>+                        gt->steering[INSTANCE0].ranges = xe3p_xpc_instance0_steering_table;
>+                        gt->steering[PSMI19].ranges = xe3p_xpc_psmi_grp19_steering_table;
>+                } else if (GRAPHICS_VER(xe) >= 20) {
>                         gt->steering[DSS].ranges = xe2lpg_dss_steering_table;
>                         gt->steering[SQIDI_PSMI].ranges = xe2lpg_sqidi_psmi_steering_table;
>                         gt->steering[INSTANCE0].ranges = xe2lpg_instance0_steering_table;
>diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
>index 8b5f604d7883a..d93faa1eedef8 100644
>--- a/drivers/gpu/drm/xe/xe_gt_types.h
>+++ b/drivers/gpu/drm/xe/xe_gt_types.h
>@@ -72,6 +72,21 @@ enum xe_steering_type {
>         OADDRM,
>         SQIDI_PSMI,
> 
>+        /*
>+         * The bspec lists multiple ranges as "PSMI," but the different
>+         * ranges with that label have different grpid steering values so we
>+         * treat them independently in code.  Note that the ranges with grpid=0
>+         * are included in the INSTANCE0 group above.
>+         */
>+        PSMI19,
>+
>+        /*
>+         * Although most GAM ranges must be steered to (0,0) and thus use the
>+         * INSTANCE0 type farther down, some platforms have special rules
>+         * for specific subtypes that require steering to (1,0) instead.
>+         */
>+        GAM1,
>+
>         /*
>          * On some platforms there are multiple types of MCR registers that
>          * will always return a non-terminated value at instance (0, 0).  We'll
>
>-- 
>2.51.0
>

Re: [PATCH v2 20/22] drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs

[Gustavo Sousa]

Quoting Lucas De Marchi (2025-10-15 19:06:35-03:00)
>From: Matt Roper <matthew.d.roper@intel.com>
>
>The compression overfetch tuning settings only apply to platforms that
>support FlatCCS.  In Xe3p_XPC (and any future IPs that also lack
>compression) some of the registers being adjusted by this tuning will
>not exist or may have been repurposed for something else, so we should
>take care not to try to program them.
>
>Note that our xe_rtp_match_has_flatccs() function will also return false
>on platforms that do have FlatCCS in the hardware design, but have
>compression manually disabled in the BIOS.  On such platforms the
>registers still exist (and it would be fine to continue programming
>them), but they would have no effect, so skipping that tuning is also
>safe.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>---
> drivers/gpu/drm/xe/xe_rtp.c    |  7 +++++++
> drivers/gpu/drm/xe/xe_rtp.h    | 12 ++++++++++++
> drivers/gpu/drm/xe/xe_tuning.c |  9 ++++++---
> 3 files changed, 25 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
>index 66707cc89ec97..ed509b1c8cfcd 100644
>--- a/drivers/gpu/drm/xe/xe_rtp.c
>+++ b/drivers/gpu/drm/xe/xe_rtp.c
>@@ -378,3 +378,10 @@ bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_device *xe,
> {
>         return xe_gt_has_discontiguous_dss_groups(gt);
> }
>+
>+bool xe_rtp_match_has_flat_ccs(const struct xe_device *xe,
>+                               const struct xe_gt *gt,
>+                               const struct xe_hw_engine *hwe)
>+{
>+        return xe->info.has_flat_ccs;
>+}

One possible issue here is that OOB RTP entries are processed before we
call probe_has_flat_ccs().  Not a real problem right now, because we are
only using xe_rtp_match_has_flat_ccs() in gt_tunnings, but this could be
problematic if in the future someone added a
FUNC(xe_rtp_match_has_flat_ccs) in OOB rules files.

--
Gustavo Sousa

>diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
>index e5b8a9452e29e..ba5f940c0a961 100644
>--- a/drivers/gpu/drm/xe/xe_rtp.h
>+++ b/drivers/gpu/drm/xe/xe_rtp.h
>@@ -491,4 +491,16 @@ bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_device *xe,
>                                                   const struct xe_gt *gt,
>                                                   const struct xe_hw_engine *hwe);
> 
>+/**
>+ * xe_rtp_match_has_flat_ccs - Match when platform has FlatCCS compression
>+ * @xe: Device structure
>+ * @gt: GT structure
>+ * @hwe: Engine instance
>+ *
>+ * Returns: true if platform has FlatCCS compression, false otherwise
>+ */
>+bool xe_rtp_match_has_flat_ccs(const struct xe_device *xe,
>+                               const struct xe_gt *gt,
>+                               const struct xe_hw_engine *hwe);
>+
> #endif
>diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
>index fd58ea5e78bf6..7c140d8cb1e07 100644
>--- a/drivers/gpu/drm/xe/xe_tuning.c
>+++ b/drivers/gpu/drm/xe/xe_tuning.c
>@@ -40,7 +40,8 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>                                    REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
>         },
>         { XE_RTP_NAME("Tuning: Compression Overfetch"),
>-          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
>+          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
>+                       FUNC(xe_rtp_match_has_flat_ccs)),
>           XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
>                          SET(CCCHKNREG1, L3CMPCTRL))
>         },
>@@ -58,12 +59,14 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>           XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3, COMPPWOVERFETCHEN))
>         },
>         { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
>-          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
>+          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
>+                       FUNC(xe_rtp_match_has_flat_ccs)),
>           XE_RTP_ACTIONS(SET(L3SQCREG2,
>                              COMPMEMRD256BOVRFETCHEN))
>         },
>         { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only - media"),
>-          XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
>+          XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED),
>+                       FUNC(xe_rtp_match_has_flat_ccs)),
>           XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
>                              COMPMEMRD256BOVRFETCHEN))
>         },
>
>-- 
>2.51.0
>

Re: [PATCH v2 19/22] drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx

[Lucas De Marchi]

On Thu, Oct 16, 2025 at 06:52:20AM +0000, Muqthyar Ahmed, Syed Abdul wrote:
>
>
>> -----Original Message-----
>> From: De Marchi, Lucas <lucas.demarchi@intel.com>
>> Sent: Thursday, October 16, 2025 11:03 AM
>> To: Roper, Matthew D <matthew.d.roper@intel.com>
>> Cc: intel-xe@lists.freedesktop.org; Chauhan, Shekhar
>> <shekhar.chauhan@intel.com>; Vivekanandan, Balasubramani
>> <balasubramani.vivekanandan@intel.com>; Upadhyay, Tejas
>> <tejas.upadhyay@intel.com>; Ghimiray, Himal Prasad
>> <himal.prasad.ghimiray@intel.com>; Muqthyar Ahmed, Syed Abdul
>> <syed.abdul.muqthyar.ahmed@intel.com>
>> Subject: Re: [PATCH v2 19/22] drm/xe/xe3p_xpc: Add support for compute
>> walker for non-MSIx
>>
>> On Wed, Oct 15, 2025 at 05:07:42PM -0700, Matt Roper wrote:
>> >On Wed, Oct 15, 2025 at 03:06:34PM -0700, Lucas De Marchi wrote:
>> >> Current implementation of compute walker has dependency on GPU/SW
>> >> Stack which requires SW/UMD to wait for event from KMD to indicate
>> >> PIPE_CONTROL interrupt was done. This created latency on SW stack.
>> >>
>> >> This feature adds support to generate completion interrupt from GPGPU
>> >> walker which does not support MSIx and avoid software using Pipe
>> >> control drain/idle latency.
>> >>
>> >> Suggested-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>> >> Signed-off-by: S A Muqthyar Ahmed
>> >> <syed.abdul.muqthyar.ahmed@intel.com>
>> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> >> ---
>> >> v2: Rebase on split mask per engine class
>> >> ---
>> >>  drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
>> >>  drivers/gpu/drm/xe/xe_irq.c           | 6 ++++++
>> >>  2 files changed, 7 insertions(+)
>> >>
>> >> diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
>> >> b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
>> >> index 7c2a3a1401424..9c46b5fb81412 100644
>> >> --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
>> >> +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
>> >> @@ -82,6 +82,7 @@
>> >>  #define   GSC_ER_COMPLETE			REG_BIT(5)
>> >>  #define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)
>> >>  #define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
>> >> +#define   GT_COMPUTE_WALKER_INTERRUPT		REG_BIT(2)
>> >>  #define   GT_RENDER_USER_INTERRUPT		REG_BIT(0)
>> >>
>> >>  /* irqs for OTHER_KCR_INSTANCE */
>> >> diff --git a/drivers/gpu/drm/xe/xe_irq.c
>> >> b/drivers/gpu/drm/xe/xe_irq.c index 103804546b280..ac5524cbe4b9a
>> >> 100644
>> >> --- a/drivers/gpu/drm/xe/xe_irq.c
>> >> +++ b/drivers/gpu/drm/xe/xe_irq.c
>> >> @@ -149,6 +149,12 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>> >>  	if (xe_device_uc_enabled(xe)) {
>> >>  		common_mask = GT_RENDER_USER_INTERRUPT |
>> >>  			      GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
>> >> +
>> >> +		/* Enable Compute Walker Interrupt for non-MSIX platforms
>> */
>> >> +		if (GRAPHICS_VERx100(xe) >= 3511 &&
>> !xe_device_has_msix(xe)) {
>> >> +			rcs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
>> >> +			ccs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
>> >> +		}
>> >
>> >It probably doesn't matter since our execlist support isn't functional
>> >and we only really support GuC-based submission, but technically
>> >shouldn't this be outside the 'uc_enabled' check so that we'd also get
>> >these interrupts if we tried to use execlist submission?
>> >
>> >BTW, is there more support for this coming in future patches?  Without
>> >MSI-X, what's the mechanism by which userspace finds out this interrupt
>> >has fired?  We're unmasking/enabling the interrupt here, but I don't
>> >see how anything happens once the interrupts start showing up.
>>
>> Himal / Syed: any detail missing here?
>>
>> Yes, AFAIU we are still missing the change in the irq handler to get the
>> notification and the mechanism on exec queue creation for registration.
>>
>
>For exec queue creation control can only be supported on  platform supporting MSIX .
>This is for non-MSIX/MSI.
>For this irq handler just need to wake up waiting kernel or user thread and that is happening for all irq lines in handler so nothing special need to be handled.

yes, we will wake up the waiters on the ufence, but then how is this
different than the pipectl notification? Is this part just so
userspace can be compatible with non-msix platform?

Lucas De Marchi?

>
>> Lucas De Marchi
>> >
>> >
>> >Matt
>> >
>> >>  	} else {
>> >>  		common_mask = GT_RENDER_USER_INTERRUPT |
>> >>  			      GT_CS_MASTER_ERROR_INTERRUPT |
>> >>
>> >> --
>> >> 2.51.0
>> >>
>> >
>> >--
>> >Matt Roper
>> >Graphics Software Engineer
>> >Linux GPU Platform Enablement
>> >Intel Corporation

Re: [PATCH v2 21/22] drm/xe/xe3p_xpc: Setup PAT table

[Vivekanandan, Balasubramani]

On 15.10.2025 15:06, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Xe3p_XPC IP requires a new PAT table; note that this table has one fewer
> column than the Xe2/Xe3 tables since compression is not supported.
> There's also no "WT" entry (which we wouldn't have used on a platform
> without display anyway).
> 
> Bspec: 71582
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_pat.c | 96 ++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 95 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
> index 6e48ff84ad0a0..7649b554942aa 100644
> --- a/drivers/gpu/drm/xe/xe_pat.c
> +++ b/drivers/gpu/drm/xe/xe_pat.c
> @@ -154,6 +154,41 @@ static const struct xe_pat_table_entry xe2_pat_table[] = {
>  static const struct xe_pat_table_entry xe2_pat_ats = XE2_PAT( 0, 0, 0, 0, 3, 3 );
>  static const struct xe_pat_table_entry xe2_pat_pta = XE2_PAT( 0, 0, 0, 0, 3, 0 );
>  
> +/*
> + * Xe3p_XPC PAT table uses the same layout as Xe2/Xe3, except that there's no
> + * option for compression.  Also note that the "L3" and "L4" register fields
> + * actually control L2 and L3 cache respectively on this platform.
> + */
> +#define XE3P_XPC_PAT(no_promote, l3clos, l3_policy, l4_policy, __coh_mode) \
> +	XE2_PAT(no_promote, 0, l3clos, l3_policy, l4_policy, __coh_mode)
> +
> +static const struct xe_pat_table_entry xe3p_xpc_pat_ats = XE3P_XPC_PAT( 0, 0, 0, 0, 3 );
> +static const struct xe_pat_table_entry xe3p_xpc_pat_pta = XE3P_XPC_PAT( 0, 0, 0, 0, 0 );
> +
> +static const struct xe_pat_table_entry xe3p_xpc_pat_table[] = {
> +	[ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ),
> +	[ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ),
> +	[ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ),
> +	[ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ),
> +	[ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ),
> +	[ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ),
> +	[ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ),
> +	[ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ),
> +	[ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ),
> +	[ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ),
> +	[10] = XE3P_XPC_PAT( 0, 0, 0, 3, 3 ),
> +	/* 11..22 are reserved; leave set to all 0's */
> +	[23] = XE3P_XPC_PAT( 0, 1, 0, 0, 0 ),
> +	[24] = XE3P_XPC_PAT( 0, 1, 0, 0, 2 ),
> +	[25] = XE3P_XPC_PAT( 0, 1, 0, 0, 3 ),
> +	[26] = XE3P_XPC_PAT( 0, 2, 0, 0, 0 ),
> +	[27] = XE3P_XPC_PAT( 0, 2, 0, 0, 2 ),
> +	[28] = XE3P_XPC_PAT( 0, 2, 0, 0, 3 ),
> +	[29] = XE3P_XPC_PAT( 0, 3, 0, 0, 0 ),
> +	[30] = XE3P_XPC_PAT( 0, 3, 0, 0, 2 ),
> +	[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),
> +};
> +
>  u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index)
>  {
>  	WARN_ON(pat_index >= xe->pat.n_entries);
> @@ -380,9 +415,68 @@ static const struct xe_pat_ops xe2_pat_ops = {
>  	.dump = xe2_dump,
>  };
>  
> +static int xe3p_xpc_dump(struct xe_gt *gt, struct drm_printer *p)
> +{
> +	struct xe_device *xe = gt_to_xe(gt);
> +	unsigned int fw_ref;
> +	u32 pat;
> +	int i;
> +
> +	fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
> +	if (!fw_ref)
> +		return -ETIMEDOUT;
> +
> +	drm_printf(p, "PAT table:\n");
> +
> +	for (i = 0; i < xe->pat.n_entries; i++) {
> +		pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));
> +
> +		drm_printf(p, "PAT[%2d] = [ %u, %u, %u, %u, %u ]  (%#8x)\n", i,
> +			   !!(pat & XE2_NO_PROMOTE),
> +			   REG_FIELD_GET(XE2_L3_CLOS, pat),
> +			   REG_FIELD_GET(XE2_L3_POLICY, pat),
> +			   REG_FIELD_GET(XE2_L4_POLICY, pat),
> +			   REG_FIELD_GET(XE2_COH_MODE, pat),
> +			   pat);
> +	}
> +
> +	/*
> +	 * Also print PTA_MODE, which describes how the hardware accesses
> +	 * PPGTT entries.
> +	 */
> +	pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA));
> +
> +	drm_printf(p, "Page Table Access:\n");
> +	drm_printf(p, "PTA_MODE= [ %u, %u, %u, %u, %u ]  (%#8x)\n",
> +		   !!(pat & XE2_NO_PROMOTE),
> +		   REG_FIELD_GET(XE2_L3_CLOS, pat),
> +		   REG_FIELD_GET(XE2_L3_POLICY, pat),
> +		   REG_FIELD_GET(XE2_L4_POLICY, pat),
> +		   REG_FIELD_GET(XE2_COH_MODE, pat),
> +		   pat);

< Resending what was already sent to v1 by mistake. >

For completeness, we can print the _PTA_ATS register also.
Outside that, patch LGTM.

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

> +
> +	xe_force_wake_put(gt_to_fw(gt), fw_ref);
> +	return 0;
> +}
> +
> +static const struct xe_pat_ops xe3p_xpc_pat_ops = {
> +	.program_graphics = program_pat_mcr,
> +	.program_media = program_pat,
> +	.dump = xe3p_xpc_dump,
> +};
> +
>  void xe_pat_init_early(struct xe_device *xe)
>  {
> -	if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
> +	if (GRAPHICS_VERx100(xe) == 3511) {
> +		xe->pat.ops = &xe3p_xpc_pat_ops;
> +		xe->pat.table = xe3p_xpc_pat_table;
> +		xe->pat.pat_ats = &xe3p_xpc_pat_ats;
> +		xe->pat.pat_pta = &xe3p_xpc_pat_pta;
> +		xe->pat.n_entries = ARRAY_SIZE(xe3p_xpc_pat_table);
> +		xe->pat.idx[XE_CACHE_NONE] = 3;
> +		xe->pat.idx[XE_CACHE_WT] = 3;	/* N/A (no display); use UC */
> +		xe->pat.idx[XE_CACHE_WB] = 2;
> +	} else if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
>  		xe->pat.ops = &xe2_pat_ops;
>  		xe->pat.table = xe2_pat_table;
>  		xe->pat.pat_ats = &xe2_pat_ats;
> 
> -- 
> 2.51.0
> 

Re: [PATCH v2 02/22] drm/xe/xe3p_lpm: Add support for media IP versions 35.00 & 35.03

[Gustavo Sousa]

Quoting Lucas De Marchi (2025-10-15 19:06:17-03:00)
>From: Shekhar Chauhan <shekhar.chauhan@intel.com>
>
>Xe3p_LPM is very similar to Xe3_LPM on the kmd interface, so it can use
>the same descriptor structure. Add both 35.00 and 35.03 IP versions.
>
>BSpec: 74201, 74202, 77977, 77979
>Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>---
> drivers/gpu/drm/xe/xe_pci.c | 2 ++
> 1 file changed, 2 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index 3ea8ccfcbca55..b72f71b0f52c9 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -151,6 +151,8 @@ static const struct xe_ip media_ips[] = {
>         { 2000, "Xe2_LPM", &media_xelpmp },
>         { 3000, "Xe3_LPM", &media_xelpmp },
>         { 3002, "Xe3_LPM", &media_xelpmp },
>+        { 3500, "Xe3p_LPM", &media_xelpmp },
>+        { 3503, "Xe3p_LPM", &media_xelpmp },

I believe it should be "Xe3p_HPM" for 3503, no?

--
Gustavo Sousa

> };
> 
> static const struct xe_device_desc tgl_desc = {
>
>-- 
>2.51.0
>

Re: [PATCH v2 11/22] drm/xe/nvl: Define NVL-S platform

[Gustavo Sousa]

Quoting Lucas De Marchi (2025-10-15 19:06:26-03:00)
>From: Matt Roper <matthew.d.roper@intel.com>
>
>Provide the basic platform definitions and PCI IDs for NVL-S.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>---
> drivers/gpu/drm/xe/xe_pci.c            | 9 +++++++++
> drivers/gpu/drm/xe/xe_platform_types.h | 1 +
> include/drm/intel/pciids.h             | 9 +++++++++
> 3 files changed, 19 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index b72f71b0f52c9..d836fd8e187a6 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -377,6 +377,14 @@ static const struct xe_device_desc ptl_desc = {
>         .vm_max_level = 4,
> };
> 
>+static const struct xe_device_desc nvls_desc = {
>+        PLATFORM(NOVALAKE_S),
>+        .dma_mask_size = 46,
>+        .has_display = true,
>+        .max_gt_per_tile = 2,
>+        .require_force_probe = true,

With the recent merge of [1], we now need to define some extra
attributes here.  I believe we need to define: va_bits, vm_max_level,
has_flat_ccs.

[1] https://lore.kernel.org/all/20251013200944.2499947-25-matthew.d.roper@intel.com/T/

--
Gustavo Sousa

>+};
>+
> #undef PLATFORM
> __diag_pop();
> 
>@@ -405,6 +413,7 @@ static const struct pci_device_id pciidlist[] = {
>         INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
>         INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
>         INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
>+        INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
>         { }
> };
> MODULE_DEVICE_TABLE(pci, pciidlist);
>diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
>index 3e332214c7bb4..78286285c2495 100644
>--- a/drivers/gpu/drm/xe/xe_platform_types.h
>+++ b/drivers/gpu/drm/xe/xe_platform_types.h
>@@ -24,6 +24,7 @@ enum xe_platform {
>         XE_LUNARLAKE,
>         XE_BATTLEMAGE,
>         XE_PANTHERLAKE,
>+        XE_NOVALAKE_S,
> };
> 
> enum xe_subplatform {
>diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
>index 452c1de606ff2..13c592e1a28c7 100644
>--- a/include/drm/intel/pciids.h
>+++ b/include/drm/intel/pciids.h
>@@ -887,4 +887,13 @@
>         MACRO__(0xFD80, ## __VA_ARGS__), \
>         MACRO__(0xFD81, ## __VA_ARGS__)
> 
>+/* NVL-S */
>+#define INTEL_NVLS_IDS(MACRO__, ...) \
>+        MACRO__(0xD740, ## __VA_ARGS__), \
>+        MACRO__(0xD741, ## __VA_ARGS__), \
>+        MACRO__(0xD742, ## __VA_ARGS__), \
>+        MACRO__(0xD743, ## __VA_ARGS__), \
>+        MACRO__(0xD744, ## __VA_ARGS__), \
>+        MACRO__(0xD745, ## __VA_ARGS__)
>+
> #endif /* __PCIIDS_H__ */
>
>-- 
>2.51.0
>

Re: [PATCH v2 02/22] drm/xe/xe3p_lpm: Add support for media IP versions 35.00 & 35.03

[Lucas De Marchi]

On Thu, Oct 16, 2025 at 01:12:39PM -0300, Gustavo Sousa wrote:
>Quoting Lucas De Marchi (2025-10-15 19:06:17-03:00)
>>From: Shekhar Chauhan <shekhar.chauhan@intel.com>
>>
>>Xe3p_LPM is very similar to Xe3_LPM on the kmd interface, so it can use
>>the same descriptor structure. Add both 35.00 and 35.03 IP versions.
>>
>>BSpec: 74201, 74202, 77977, 77979
>>Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>>Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
>>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>---
>> drivers/gpu/drm/xe/xe_pci.c | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>>index 3ea8ccfcbca55..b72f71b0f52c9 100644
>>--- a/drivers/gpu/drm/xe/xe_pci.c
>>+++ b/drivers/gpu/drm/xe/xe_pci.c
>>@@ -151,6 +151,8 @@ static const struct xe_ip media_ips[] = {
>>         { 2000, "Xe2_LPM", &media_xelpmp },
>>         { 3000, "Xe3_LPM", &media_xelpmp },
>>         { 3002, "Xe3_LPM", &media_xelpmp },
>>+        { 3500, "Xe3p_LPM", &media_xelpmp },
>>+        { 3503, "Xe3p_LPM", &media_xelpmp },
>
>I believe it should be "Xe3p_HPM" for 3503, no?

oh, good catch. I think I ended squashing 2 patches and erroneously kept
them as lpm. I will change this and the commit message. Queueing this
fix for next version.

thanks
Lucas De Marchi

>
>--
>Gustavo Sousa
>
>> };
>>
>> static const struct xe_device_desc tgl_desc = {
>>
>>--
>>2.51.0
>>

Re: [PATCH v2 20/22] drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs

[Matt Roper]

On Thu, Oct 16, 2025 at 09:30:58AM -0300, Gustavo Sousa wrote:
> Quoting Lucas De Marchi (2025-10-15 19:06:35-03:00)
> >From: Matt Roper <matthew.d.roper@intel.com>
> >
> >The compression overfetch tuning settings only apply to platforms that
> >support FlatCCS.  In Xe3p_XPC (and any future IPs that also lack
> >compression) some of the registers being adjusted by this tuning will
> >not exist or may have been repurposed for something else, so we should
> >take care not to try to program them.
> >
> >Note that our xe_rtp_match_has_flatccs() function will also return false
> >on platforms that do have FlatCCS in the hardware design, but have
> >compression manually disabled in the BIOS.  On such platforms the
> >registers still exist (and it would be fine to continue programming
> >them), but they would have no effect, so skipping that tuning is also
> >safe.
> >
> >Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> >Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
> >Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >---
> > drivers/gpu/drm/xe/xe_rtp.c    |  7 +++++++
> > drivers/gpu/drm/xe/xe_rtp.h    | 12 ++++++++++++
> > drivers/gpu/drm/xe/xe_tuning.c |  9 ++++++---
> > 3 files changed, 25 insertions(+), 3 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
> >index 66707cc89ec97..ed509b1c8cfcd 100644
> >--- a/drivers/gpu/drm/xe/xe_rtp.c
> >+++ b/drivers/gpu/drm/xe/xe_rtp.c
> >@@ -378,3 +378,10 @@ bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_device *xe,
> > {
> >         return xe_gt_has_discontiguous_dss_groups(gt);
> > }
> >+
> >+bool xe_rtp_match_has_flat_ccs(const struct xe_device *xe,
> >+                               const struct xe_gt *gt,
> >+                               const struct xe_hw_engine *hwe)
> >+{
> >+        return xe->info.has_flat_ccs;
> >+}
> 
> One possible issue here is that OOB RTP entries are processed before we
> call probe_has_flat_ccs().  Not a real problem right now, because we are
> only using xe_rtp_match_has_flat_ccs() in gt_tunnings, but this could be
> problematic if in the future someone added a
> FUNC(xe_rtp_match_has_flat_ccs) in OOB rules files.

I don't think that would be a problem; xe->info.has_flat_ccs at that
point will reflect the architectural availability of FlatCCS, which is
what we're actually trying to test here.  The value just won't be
adjusted according to BIOS settings, effectively removing the caveat in
the 2nd paragraph of the commit message.  The only problem would be if
we had a workaround that specifically wanted to check whether FlatCCS
was enabled/disabled in the BIOS; in that case this function might not
work properly.  But I think that's a lot less likely than
workarounds/tuning like this one that need to check the architectural
presence of FlatCCS.


Matt

> 
> --
> Gustavo Sousa
> 
> >diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
> >index e5b8a9452e29e..ba5f940c0a961 100644
> >--- a/drivers/gpu/drm/xe/xe_rtp.h
> >+++ b/drivers/gpu/drm/xe/xe_rtp.h
> >@@ -491,4 +491,16 @@ bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_device *xe,
> >                                                   const struct xe_gt *gt,
> >                                                   const struct xe_hw_engine *hwe);
> > 
> >+/**
> >+ * xe_rtp_match_has_flat_ccs - Match when platform has FlatCCS compression
> >+ * @xe: Device structure
> >+ * @gt: GT structure
> >+ * @hwe: Engine instance
> >+ *
> >+ * Returns: true if platform has FlatCCS compression, false otherwise
> >+ */
> >+bool xe_rtp_match_has_flat_ccs(const struct xe_device *xe,
> >+                               const struct xe_gt *gt,
> >+                               const struct xe_hw_engine *hwe);
> >+
> > #endif
> >diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> >index fd58ea5e78bf6..7c140d8cb1e07 100644
> >--- a/drivers/gpu/drm/xe/xe_tuning.c
> >+++ b/drivers/gpu/drm/xe/xe_tuning.c
> >@@ -40,7 +40,8 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
> >                                    REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
> >         },
> >         { XE_RTP_NAME("Tuning: Compression Overfetch"),
> >-          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
> >+          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
> >+                       FUNC(xe_rtp_match_has_flat_ccs)),
> >           XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
> >                          SET(CCCHKNREG1, L3CMPCTRL))
> >         },
> >@@ -58,12 +59,14 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
> >           XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3, COMPPWOVERFETCHEN))
> >         },
> >         { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
> >-          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
> >+          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
> >+                       FUNC(xe_rtp_match_has_flat_ccs)),
> >           XE_RTP_ACTIONS(SET(L3SQCREG2,
> >                              COMPMEMRD256BOVRFETCHEN))
> >         },
> >         { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only - media"),
> >-          XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
> >+          XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED),
> >+                       FUNC(xe_rtp_match_has_flat_ccs)),
> >           XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
> >                              COMPMEMRD256BOVRFETCHEN))
> >         },
> >
> >-- 
> >2.51.0
> >

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v2 16/22] drm/xe/xe3p_xpc: Add MCR steering

[Lucas De Marchi]

On Thu, Oct 16, 2025 at 08:44:34AM -0300, Gustavo Sousa wrote:
>Quoting Lucas De Marchi (2025-10-15 19:06:31-03:00)
>>From: Matt Roper <matthew.d.roper@intel.com>
>>
>>Xe3p_XPC's steering has a few changes from Xe3.  Aside from
>>minor changes to the XeCore (the new name for what used to be "DSS") and
>>INSTANCE0 tables, different rules apply to different subranges of type
>>"GAM."  Certain GAM subranges require steering to grp/instance (0,0)
>>(and thus use the INSTANCE0 table), while others require special
>>steering to (1,0) instead.  Similarly, there are multiple classes of
>>"PSMI" steering, with some requiring steering to (0,0) while others
>>require (19,0).
>>
>>FIXME: There's an "L3BANK" range listed in the bspec that needs
>>clarification.
>
>I think we also have a NODE range that is also missing termination
>details.  I think a TODO/FIXME in the code for those two types of range
>would help reminind ourselves about the need to complete the tables.

Like this?


| diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
| index e5506ec28e147..f35d8a31c1079 100644
| --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
| +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
| @@ -515,6 +515,12 @@ void xe_gt_mcr_init_early(struct xe_gt *gt)
|                 }
|         } else {
|                 if (GRAPHICS_VERx100(xe) == 3511) {
| +                       /*
| +                        * TODO: there are 2 ranges in bspec with missing
| +                        * termination: [0x00B000, 0x00B0FF] (NODE) and
| +                        * [0x00B100, 0x00B3FF] (L3BANK). Updated them here once
| +                        * bspec is updated.
| +                        */
|                         gt->steering[DSS].ranges = xe3p_xpc_xecore_steering_table;
|                         gt->steering[GAM1].ranges = xe3p_xpc_gam_grp1_steering_table;
|                         gt->steering[INSTANCE0].ranges = xe3p_xpc_instance0_steering_table;

>
>For the ranges added in this patch, I checked and they match the Bspec,
>so:
>
>Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

thanks
Lucas De Marchi

>
>>
>>Bspec: 74418
>>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>---
>> drivers/gpu/drm/xe/xe_gt_mcr.c   | 56 ++++++++++++++++++++++++++++++++++++++--
>> drivers/gpu/drm/xe/xe_gt_types.h | 15 +++++++++++
>> 2 files changed, 69 insertions(+), 2 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
>>index e1a2b38fc2a86..e5506ec28e147 100644
>>--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
>>+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
>>@@ -169,6 +169,15 @@ static const struct xe_mmio_range xelpg_dss_steering_table[] = {
>>         {},
>> };
>>
>>+static const struct xe_mmio_range xe3p_xpc_xecore_steering_table[] = {
>>+        { 0x008140, 0x00817F },         /* SLICE, XeCore, SLICE */
>>+        { 0x009480, 0x00955F },         /* SLICE, XeCore */
>>+        { 0x00D800, 0x00D87F },                /* SLICE */
>>+        { 0x00DC00, 0x00E9FF },         /* SLICE, rsvd, XeCore, rsvd, XeCore, rsvd, XeCore */
>>+        { 0x013000, 0x0135FF },         /* XeCore, SLICE */
>>+        {},
>>+};
>>+
>> static const struct xe_mmio_range xelpmp_oaddrm_steering_table[] = {
>>         { 0x393200, 0x39323F },
>>         { 0x393400, 0x3934FF },
>>@@ -247,6 +256,30 @@ static const struct xe_mmio_range xe3lpm_instance0_steering_table[] = {
>>         {},
>> };
>>
>>+/*
>>+ * Different "GAM" ranges have different rules; GAMWKRS, STLB, and GAMREQSTRM
>>+ * range subtypes need to be steered to (1,0), while all other GAM subtypes
>>+ * are steered to (0,0) and are included in the "INSTANCE0" table farther
>>+ * down.
>>+ */
>>+static const struct xe_mmio_range xe3p_xpc_gam_grp1_steering_table[] = {
>>+        { 0x004000, 0x004AFF },                /* GAMREQSTRM, rsvd, STLB, GAMWKRS, GAMREQSTRM */
>>+        { 0x00F100, 0x00FFFF },                /* GAMWKRS */
>>+        {},
>>+};
>>+
>>+static const struct xe_mmio_range xe3p_xpc_psmi_grp19_steering_table[] = {
>>+        { 0x00B500, 0x00B5FF },
>>+        {},
>>+};
>>+
>>+static const struct xe_mmio_range xe3p_xpc_instance0_steering_table[] = {
>>+        { 0x00B600, 0x00B6FF },                /* PSMI0 */
>>+        { 0x00C800, 0x00CFFF },                /* GAMCTRL */
>>+        { 0x00F000, 0x00F0FF },                /* GAMCTRL */
>>+        {},
>>+};
>>+
>> static void init_steering_l3bank(struct xe_gt *gt)
>> {
>>         struct xe_mmio *mmio = &gt->mmio;
>>@@ -419,6 +452,18 @@ static void init_steering_sqidi_psmi(struct xe_gt *gt)
>>         gt->steering[SQIDI_PSMI].instance_target = select & 0x1;
>> }
>>
>>+static void init_steering_psmi(struct xe_gt *gt)
>>+{
>>+        gt->steering[PSMI19].group_target = 19;
>>+        gt->steering[PSMI19].instance_target = 0;
>>+}
>>+
>>+static void init_steering_gam1(struct xe_gt *gt)
>>+{
>>+        gt->steering[GAM1].group_target = 1;
>>+        gt->steering[GAM1].instance_target = 0;
>>+}
>>+
>> static const struct {
>>         const char *name;
>>         void (*init)(struct xe_gt *gt);
>>@@ -426,9 +471,11 @@ static const struct {
>>         [L3BANK] =        { "L3BANK",        init_steering_l3bank },
>>         [MSLICE] =        { "MSLICE",        init_steering_mslice },
>>         [LNCF] =        { "LNCF",        NULL }, /* initialized by mslice init */
>>-        [DSS] =                { "DSS",        init_steering_dss },
>>+        [DSS] =                { "DSS / XeCore", init_steering_dss },
>>         [OADDRM] =        { "OADDRM / GPMXMT", init_steering_oaddrm },
>>         [SQIDI_PSMI] =  { "SQIDI_PSMI", init_steering_sqidi_psmi },
>>+        [PSMI19] =        { "PSMI[19]",        init_steering_psmi },
>>+        [GAM1] =        { "GAMWKRS / STLB / GAMREQSTRM", init_steering_gam1 },
>>         [INSTANCE0] =        { "INSTANCE 0",        NULL },
>>         [IMPLICIT_STEERING] = { "IMPLICIT", NULL },
>> };
>>@@ -467,7 +514,12 @@ void xe_gt_mcr_init_early(struct xe_gt *gt)
>>                         gt->steering[OADDRM].ranges = xelpmp_oaddrm_steering_table;
>>                 }
>>         } else {
>>-                if (GRAPHICS_VER(xe) >= 20) {
>>+                if (GRAPHICS_VERx100(xe) == 3511) {
>>+                        gt->steering[DSS].ranges = xe3p_xpc_xecore_steering_table;
>>+                        gt->steering[GAM1].ranges = xe3p_xpc_gam_grp1_steering_table;
>>+                        gt->steering[INSTANCE0].ranges = xe3p_xpc_instance0_steering_table;
>>+                        gt->steering[PSMI19].ranges = xe3p_xpc_psmi_grp19_steering_table;
>>+                } else if (GRAPHICS_VER(xe) >= 20) {
>>                         gt->steering[DSS].ranges = xe2lpg_dss_steering_table;
>>                         gt->steering[SQIDI_PSMI].ranges = xe2lpg_sqidi_psmi_steering_table;
>>                         gt->steering[INSTANCE0].ranges = xe2lpg_instance0_steering_table;
>>diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
>>index 8b5f604d7883a..d93faa1eedef8 100644
>>--- a/drivers/gpu/drm/xe/xe_gt_types.h
>>+++ b/drivers/gpu/drm/xe/xe_gt_types.h
>>@@ -72,6 +72,21 @@ enum xe_steering_type {
>>         OADDRM,
>>         SQIDI_PSMI,
>>
>>+        /*
>>+         * The bspec lists multiple ranges as "PSMI," but the different
>>+         * ranges with that label have different grpid steering values so we
>>+         * treat them independently in code.  Note that the ranges with grpid=0
>>+         * are included in the INSTANCE0 group above.
>>+         */
>>+        PSMI19,
>>+
>>+        /*
>>+         * Although most GAM ranges must be steered to (0,0) and thus use the
>>+         * INSTANCE0 type farther down, some platforms have special rules
>>+         * for specific subtypes that require steering to (1,0) instead.
>>+         */
>>+        GAM1,
>>+
>>         /*
>>          * On some platforms there are multiple types of MCR registers that
>>          * will always return a non-terminated value at instance (0, 0).  We'll
>>
>>--
>>2.51.0
>>

Re: [PATCH v2 16/22] drm/xe/xe3p_xpc: Add MCR steering

[Gustavo Sousa]

Quoting Lucas De Marchi (2025-10-16 16:48:01-03:00)
>On Thu, Oct 16, 2025 at 08:44:34AM -0300, Gustavo Sousa wrote:
>>Quoting Lucas De Marchi (2025-10-15 19:06:31-03:00)
>>>From: Matt Roper <matthew.d.roper@intel.com>
>>>
>>>Xe3p_XPC's steering has a few changes from Xe3.  Aside from
>>>minor changes to the XeCore (the new name for what used to be "DSS") and
>>>INSTANCE0 tables, different rules apply to different subranges of type
>>>"GAM."  Certain GAM subranges require steering to grp/instance (0,0)
>>>(and thus use the INSTANCE0 table), while others require special
>>>steering to (1,0) instead.  Similarly, there are multiple classes of
>>>"PSMI" steering, with some requiring steering to (0,0) while others
>>>require (19,0).
>>>
>>>FIXME: There's an "L3BANK" range listed in the bspec that needs
>>>clarification.
>>
>>I think we also have a NODE range that is also missing termination
>>details.  I think a TODO/FIXME in the code for those two types of range
>>would help reminind ourselves about the need to complete the tables.
>
>Like this?

Yep, but with a few tweaks, noted below.

>
>
>| diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
>| index e5506ec28e147..f35d8a31c1079 100644
>| --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
>| +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
>| @@ -515,6 +515,12 @@ void xe_gt_mcr_init_early(struct xe_gt *gt)
>|                 }
>|         } else {
>|                 if (GRAPHICS_VERx100(xe) == 3511) {
>| +                       /*
>| +                        * TODO: there are 2 ranges in bspec with missing
>| +                        * termination: [0x00B000, 0x00B0FF] (NODE) and

The range [0x00D880, 0x00D8FF] is also tagged as NODE.

>| +                        * [0x00B100, 0x00B3FF] (L3BANK). Updated them here once


s/Updated/Update/


--
Gustavo Sousa

>| +                        * bspec is updated.
>| +                        */
>|                         gt->steering[DSS].ranges = xe3p_xpc_xecore_steering_table;
>|                         gt->steering[GAM1].ranges = xe3p_xpc_gam_grp1_steering_table;
>|                         gt->steering[INSTANCE0].ranges = xe3p_xpc_instance0_steering_table;
>
>>
>>For the ranges added in this patch, I checked and they match the Bspec,
>>so:
>>
>>Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
>
>thanks
>Lucas De Marchi
>
>>
>>>
>>>Bspec: 74418
>>>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>>---
>>> drivers/gpu/drm/xe/xe_gt_mcr.c   | 56 ++++++++++++++++++++++++++++++++++++++--
>>> drivers/gpu/drm/xe/xe_gt_types.h | 15 +++++++++++
>>> 2 files changed, 69 insertions(+), 2 deletions(-)
>>>
>>>diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
>>>index e1a2b38fc2a86..e5506ec28e147 100644
>>>--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
>>>+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
>>>@@ -169,6 +169,15 @@ static const struct xe_mmio_range xelpg_dss_steering_table[] = {
>>>         {},
>>> };
>>>
>>>+static const struct xe_mmio_range xe3p_xpc_xecore_steering_table[] = {
>>>+        { 0x008140, 0x00817F },         /* SLICE, XeCore, SLICE */
>>>+        { 0x009480, 0x00955F },         /* SLICE, XeCore */
>>>+        { 0x00D800, 0x00D87F },                /* SLICE */
>>>+        { 0x00DC00, 0x00E9FF },         /* SLICE, rsvd, XeCore, rsvd, XeCore, rsvd, XeCore */
>>>+        { 0x013000, 0x0135FF },         /* XeCore, SLICE */
>>>+        {},
>>>+};
>>>+
>>> static const struct xe_mmio_range xelpmp_oaddrm_steering_table[] = {
>>>         { 0x393200, 0x39323F },
>>>         { 0x393400, 0x3934FF },
>>>@@ -247,6 +256,30 @@ static const struct xe_mmio_range xe3lpm_instance0_steering_table[] = {
>>>         {},
>>> };
>>>
>>>+/*
>>>+ * Different "GAM" ranges have different rules; GAMWKRS, STLB, and GAMREQSTRM
>>>+ * range subtypes need to be steered to (1,0), while all other GAM subtypes
>>>+ * are steered to (0,0) and are included in the "INSTANCE0" table farther
>>>+ * down.
>>>+ */
>>>+static const struct xe_mmio_range xe3p_xpc_gam_grp1_steering_table[] = {
>>>+        { 0x004000, 0x004AFF },                /* GAMREQSTRM, rsvd, STLB, GAMWKRS, GAMREQSTRM */
>>>+        { 0x00F100, 0x00FFFF },                /* GAMWKRS */
>>>+        {},
>>>+};
>>>+
>>>+static const struct xe_mmio_range xe3p_xpc_psmi_grp19_steering_table[] = {
>>>+        { 0x00B500, 0x00B5FF },
>>>+        {},
>>>+};
>>>+
>>>+static const struct xe_mmio_range xe3p_xpc_instance0_steering_table[] = {
>>>+        { 0x00B600, 0x00B6FF },                /* PSMI0 */
>>>+        { 0x00C800, 0x00CFFF },                /* GAMCTRL */
>>>+        { 0x00F000, 0x00F0FF },                /* GAMCTRL */
>>>+        {},
>>>+};
>>>+
>>> static void init_steering_l3bank(struct xe_gt *gt)
>>> {
>>>         struct xe_mmio *mmio = &gt->mmio;
>>>@@ -419,6 +452,18 @@ static void init_steering_sqidi_psmi(struct xe_gt *gt)
>>>         gt->steering[SQIDI_PSMI].instance_target = select & 0x1;
>>> }
>>>
>>>+static void init_steering_psmi(struct xe_gt *gt)
>>>+{
>>>+        gt->steering[PSMI19].group_target = 19;
>>>+        gt->steering[PSMI19].instance_target = 0;
>>>+}
>>>+
>>>+static void init_steering_gam1(struct xe_gt *gt)
>>>+{
>>>+        gt->steering[GAM1].group_target = 1;
>>>+        gt->steering[GAM1].instance_target = 0;
>>>+}
>>>+
>>> static const struct {
>>>         const char *name;
>>>         void (*init)(struct xe_gt *gt);
>>>@@ -426,9 +471,11 @@ static const struct {
>>>         [L3BANK] =        { "L3BANK",        init_steering_l3bank },
>>>         [MSLICE] =        { "MSLICE",        init_steering_mslice },
>>>         [LNCF] =        { "LNCF",        NULL }, /* initialized by mslice init */
>>>-        [DSS] =                { "DSS",        init_steering_dss },
>>>+        [DSS] =                { "DSS / XeCore", init_steering_dss },
>>>         [OADDRM] =        { "OADDRM / GPMXMT", init_steering_oaddrm },
>>>         [SQIDI_PSMI] =  { "SQIDI_PSMI", init_steering_sqidi_psmi },
>>>+        [PSMI19] =        { "PSMI[19]",        init_steering_psmi },
>>>+        [GAM1] =        { "GAMWKRS / STLB / GAMREQSTRM", init_steering_gam1 },
>>>         [INSTANCE0] =        { "INSTANCE 0",        NULL },
>>>         [IMPLICIT_STEERING] = { "IMPLICIT", NULL },
>>> };
>>>@@ -467,7 +514,12 @@ void xe_gt_mcr_init_early(struct xe_gt *gt)
>>>                         gt->steering[OADDRM].ranges = xelpmp_oaddrm_steering_table;
>>>                 }
>>>         } else {
>>>-                if (GRAPHICS_VER(xe) >= 20) {
>>>+                if (GRAPHICS_VERx100(xe) == 3511) {
>>>+                        gt->steering[DSS].ranges = xe3p_xpc_xecore_steering_table;
>>>+                        gt->steering[GAM1].ranges = xe3p_xpc_gam_grp1_steering_table;
>>>+                        gt->steering[INSTANCE0].ranges = xe3p_xpc_instance0_steering_table;
>>>+                        gt->steering[PSMI19].ranges = xe3p_xpc_psmi_grp19_steering_table;
>>>+                } else if (GRAPHICS_VER(xe) >= 20) {
>>>                         gt->steering[DSS].ranges = xe2lpg_dss_steering_table;
>>>                         gt->steering[SQIDI_PSMI].ranges = xe2lpg_sqidi_psmi_steering_table;
>>>                         gt->steering[INSTANCE0].ranges = xe2lpg_instance0_steering_table;
>>>diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
>>>index 8b5f604d7883a..d93faa1eedef8 100644
>>>--- a/drivers/gpu/drm/xe/xe_gt_types.h
>>>+++ b/drivers/gpu/drm/xe/xe_gt_types.h
>>>@@ -72,6 +72,21 @@ enum xe_steering_type {
>>>         OADDRM,
>>>         SQIDI_PSMI,
>>>
>>>+        /*
>>>+         * The bspec lists multiple ranges as "PSMI," but the different
>>>+         * ranges with that label have different grpid steering values so we
>>>+         * treat them independently in code.  Note that the ranges with grpid=0
>>>+         * are included in the INSTANCE0 group above.
>>>+         */
>>>+        PSMI19,
>>>+
>>>+        /*
>>>+         * Although most GAM ranges must be steered to (0,0) and thus use the
>>>+         * INSTANCE0 type farther down, some platforms have special rules
>>>+         * for specific subtypes that require steering to (1,0) instead.
>>>+         */
>>>+        GAM1,
>>>+
>>>         /*
>>>          * On some platforms there are multiple types of MCR registers that
>>>          * will always return a non-terminated value at instance (0, 0).  We'll
>>>
>>>--
>>>2.51.0
>>>

Re: [PATCH v2 21/22] drm/xe/xe3p_xpc: Setup PAT table

[Lucas De Marchi]

On Thu, Oct 16, 2025 at 08:00:32PM +0530, Vivekanandan, Balasubramani wrote:
>On 15.10.2025 15:06, Lucas De Marchi wrote:
>> From: Matt Roper <matthew.d.roper@intel.com>
>>
>> Xe3p_XPC IP requires a new PAT table; note that this table has one fewer
>> column than the Xe2/Xe3 tables since compression is not supported.
>> There's also no "WT" entry (which we wouldn't have used on a platform
>> without display anyway).
>>
>> Bspec: 71582
>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/xe/xe_pat.c | 96 ++++++++++++++++++++++++++++++++++++++++++++-
>>  1 file changed, 95 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
>> index 6e48ff84ad0a0..7649b554942aa 100644
>> --- a/drivers/gpu/drm/xe/xe_pat.c
>> +++ b/drivers/gpu/drm/xe/xe_pat.c
>> @@ -154,6 +154,41 @@ static const struct xe_pat_table_entry xe2_pat_table[] = {
>>  static const struct xe_pat_table_entry xe2_pat_ats = XE2_PAT( 0, 0, 0, 0, 3, 3 );
>>  static const struct xe_pat_table_entry xe2_pat_pta = XE2_PAT( 0, 0, 0, 0, 3, 0 );
>>
>> +/*
>> + * Xe3p_XPC PAT table uses the same layout as Xe2/Xe3, except that there's no
>> + * option for compression.  Also note that the "L3" and "L4" register fields
>> + * actually control L2 and L3 cache respectively on this platform.
>> + */
>> +#define XE3P_XPC_PAT(no_promote, l3clos, l3_policy, l4_policy, __coh_mode) \
>> +	XE2_PAT(no_promote, 0, l3clos, l3_policy, l4_policy, __coh_mode)
>> +
>> +static const struct xe_pat_table_entry xe3p_xpc_pat_ats = XE3P_XPC_PAT( 0, 0, 0, 0, 3 );
>> +static const struct xe_pat_table_entry xe3p_xpc_pat_pta = XE3P_XPC_PAT( 0, 0, 0, 0, 0 );
>> +
>> +static const struct xe_pat_table_entry xe3p_xpc_pat_table[] = {
>> +	[ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ),
>> +	[ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ),
>> +	[ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ),
>> +	[ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ),
>> +	[ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ),
>> +	[ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ),
>> +	[ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ),
>> +	[ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ),
>> +	[ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ),
>> +	[ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ),
>> +	[10] = XE3P_XPC_PAT( 0, 0, 0, 3, 3 ),
>> +	/* 11..22 are reserved; leave set to all 0's */
>> +	[23] = XE3P_XPC_PAT( 0, 1, 0, 0, 0 ),
>> +	[24] = XE3P_XPC_PAT( 0, 1, 0, 0, 2 ),
>> +	[25] = XE3P_XPC_PAT( 0, 1, 0, 0, 3 ),
>> +	[26] = XE3P_XPC_PAT( 0, 2, 0, 0, 0 ),
>> +	[27] = XE3P_XPC_PAT( 0, 2, 0, 0, 2 ),
>> +	[28] = XE3P_XPC_PAT( 0, 2, 0, 0, 3 ),
>> +	[29] = XE3P_XPC_PAT( 0, 3, 0, 0, 0 ),
>> +	[30] = XE3P_XPC_PAT( 0, 3, 0, 0, 2 ),
>> +	[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),
>> +};
>> +
>>  u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index)
>>  {
>>  	WARN_ON(pat_index >= xe->pat.n_entries);
>> @@ -380,9 +415,68 @@ static const struct xe_pat_ops xe2_pat_ops = {
>>  	.dump = xe2_dump,
>>  };
>>
>> +static int xe3p_xpc_dump(struct xe_gt *gt, struct drm_printer *p)
>> +{
>> +	struct xe_device *xe = gt_to_xe(gt);
>> +	unsigned int fw_ref;
>> +	u32 pat;
>> +	int i;
>> +
>> +	fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
>> +	if (!fw_ref)
>> +		return -ETIMEDOUT;
>> +
>> +	drm_printf(p, "PAT table:\n");
>> +
>> +	for (i = 0; i < xe->pat.n_entries; i++) {
>> +		pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));
>> +
>> +		drm_printf(p, "PAT[%2d] = [ %u, %u, %u, %u, %u ]  (%#8x)\n", i,
>> +			   !!(pat & XE2_NO_PROMOTE),
>> +			   REG_FIELD_GET(XE2_L3_CLOS, pat),
>> +			   REG_FIELD_GET(XE2_L3_POLICY, pat),
>> +			   REG_FIELD_GET(XE2_L4_POLICY, pat),
>> +			   REG_FIELD_GET(XE2_COH_MODE, pat),
>> +			   pat);
>> +	}
>> +
>> +	/*
>> +	 * Also print PTA_MODE, which describes how the hardware accesses
>> +	 * PPGTT entries.
>> +	 */
>> +	pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA));
>> +
>> +	drm_printf(p, "Page Table Access:\n");
>> +	drm_printf(p, "PTA_MODE= [ %u, %u, %u, %u, %u ]  (%#8x)\n",
>> +		   !!(pat & XE2_NO_PROMOTE),
>> +		   REG_FIELD_GET(XE2_L3_CLOS, pat),
>> +		   REG_FIELD_GET(XE2_L3_POLICY, pat),
>> +		   REG_FIELD_GET(XE2_L4_POLICY, pat),
>> +		   REG_FIELD_GET(XE2_COH_MODE, pat),
>> +		   pat);
>
>< Resending what was already sent to v1 by mistake. >
>
>For completeness, we can print the _PTA_ATS register also.
>Outside that, patch LGTM.

but that would be in a separate patch, right? We already have this:

	} else if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
		...
		xe->pat.pat_ats = &xe2_pat_ats;

which will cause us to write to it and thus we should also add the dump
in the xe2_dump()  for completeness.

>
>Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

thanks
Lucas De Marchi

>
>> +
>> +	xe_force_wake_put(gt_to_fw(gt), fw_ref);
>> +	return 0;
>> +}
>> +
>> +static const struct xe_pat_ops xe3p_xpc_pat_ops = {
>> +	.program_graphics = program_pat_mcr,
>> +	.program_media = program_pat,
>> +	.dump = xe3p_xpc_dump,
>> +};
>> +
>>  void xe_pat_init_early(struct xe_device *xe)
>>  {
>> -	if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
>> +	if (GRAPHICS_VERx100(xe) == 3511) {
>> +		xe->pat.ops = &xe3p_xpc_pat_ops;
>> +		xe->pat.table = xe3p_xpc_pat_table;
>> +		xe->pat.pat_ats = &xe3p_xpc_pat_ats;
>> +		xe->pat.pat_pta = &xe3p_xpc_pat_pta;
>> +		xe->pat.n_entries = ARRAY_SIZE(xe3p_xpc_pat_table);
>> +		xe->pat.idx[XE_CACHE_NONE] = 3;
>> +		xe->pat.idx[XE_CACHE_WT] = 3;	/* N/A (no display); use UC */
>> +		xe->pat.idx[XE_CACHE_WB] = 2;
>> +	} else if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
>>  		xe->pat.ops = &xe2_pat_ops;
>>  		xe->pat.table = xe2_pat_table;
>>  		xe->pat.pat_ats = &xe2_pat_ats;
>>
>> --
>> 2.51.0
>>

✗ Xe.CI.Full: failure for drm/xe: Add Xe3p support (rev2)

[Patchwork]

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== Series Details ==

Series: drm/xe: Add Xe3p support (rev2)
URL   : https://patchwork.freedesktop.org/series/155866/
State : failure

== Summary ==

CI Bug Log - changes from xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8_FULL -> xe-pw-155866v2_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-155866v2_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-155866v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-155866v2_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_module_load@load:
    - shard-adlp:         ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) -> ([DMESG-FAIL][27], [DMESG-FAIL][28], [DMESG-FAIL][29], [DMESG-FAIL][30], [DMESG-FAIL][31], [DMESG-FAIL][32], [DMESG-FAIL][33], [DMESG-FAIL][34], [DMESG-FAIL][35], [DMESG-FAIL][36], [DMESG-FAIL][37], [DMESG-FAIL][38], [DMESG-FAIL][39], [DMESG-FAIL][40], [DMESG-FAIL][41], [DMESG-FAIL][42], [DMESG-FAIL][43], [DMESG-FAIL][44], [DMESG-FAIL][45], [DMESG-FAIL][46])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-1/igt@xe_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-1/igt@xe_module_load@load.html
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-1/igt@xe_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-6/igt@xe_module_load@load.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-6/igt@xe_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-8/igt@xe_module_load@load.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-2/igt@xe_module_load@load.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-6/igt@xe_module_load@load.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-6/igt@xe_module_load@load.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-9/igt@xe_module_load@load.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-6/igt@xe_module_load@load.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-8/igt@xe_module_load@load.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-6/igt@xe_module_load@load.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-2/igt@xe_module_load@load.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-2/igt@xe_module_load@load.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-9/igt@xe_module_load@load.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-9/igt@xe_module_load@load.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-8/igt@xe_module_load@load.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-8/igt@xe_module_load@load.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-2/igt@xe_module_load@load.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-8/igt@xe_module_load@load.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-8/igt@xe_module_load@load.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-2/igt@xe_module_load@load.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-8/igt@xe_module_load@load.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-9/igt@xe_module_load@load.html
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-adlp-9/igt@xe_module_load@load.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-6/igt@xe_module_load@load.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-6/igt@xe_module_load@load.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-6/igt@xe_module_load@load.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-6/igt@xe_module_load@load.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-9/igt@xe_module_load@load.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-9/igt@xe_module_load@load.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-9/igt@xe_module_load@load.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-9/igt@xe_module_load@load.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-8/igt@xe_module_load@load.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-8/igt@xe_module_load@load.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-8/igt@xe_module_load@load.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-8/igt@xe_module_load@load.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-2/igt@xe_module_load@load.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-2/igt@xe_module_load@load.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-2/igt@xe_module_load@load.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-2/igt@xe_module_load@load.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-1/igt@xe_module_load@load.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-1/igt@xe_module_load@load.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-1/igt@xe_module_load@load.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-adlp-1/igt@xe_module_load@load.html

  
#### Warnings ####

  * igt@xe_module_load@load:
    - shard-lnl:          ([PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [SKIP][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77], [PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91]) ([Intel XE#378]) -> ([DMESG-FAIL][92], [DMESG-FAIL][93], [DMESG-FAIL][94], [DMESG-FAIL][95], [DMESG-FAIL][96], [DMESG-FAIL][97], [DMESG-FAIL][98], [DMESG-FAIL][99], [DMESG-FAIL][100], [DMESG-FAIL][101], [DMESG-FAIL][102], [DMESG-FAIL][103], [DMESG-FAIL][104], [DMESG-FAIL][105], [DMESG-FAIL][106], [DMESG-FAIL][107], [DMESG-FAIL][108], [DMESG-FAIL][109], [DMESG-FAIL][110], [DMESG-FAIL][111], [DMESG-FAIL][112], [DMESG-FAIL][113], [DMESG-FAIL][114], [DMESG-FAIL][115], [DMESG-FAIL][116])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-4/igt@xe_module_load@load.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-4/igt@xe_module_load@load.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-7/igt@xe_module_load@load.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-1/igt@xe_module_load@load.html
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-8/igt@xe_module_load@load.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-5/igt@xe_module_load@load.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-7/igt@xe_module_load@load.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-5/igt@xe_module_load@load.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-7/igt@xe_module_load@load.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-8/igt@xe_module_load@load.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-8/igt@xe_module_load@load.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-7/igt@xe_module_load@load.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-2/igt@xe_module_load@load.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-2/igt@xe_module_load@load.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-4/igt@xe_module_load@load.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-4/igt@xe_module_load@load.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-5/igt@xe_module_load@load.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-5/igt@xe_module_load@load.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-5/igt@xe_module_load@load.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-2/igt@xe_module_load@load.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-5/igt@xe_module_load@load.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-1/igt@xe_module_load@load.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-1/igt@xe_module_load@load.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-4/igt@xe_module_load@load.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-3/igt@xe_module_load@load.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-3/igt@xe_module_load@load.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-3/igt@xe_module_load@load.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-7/igt@xe_module_load@load.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-8/igt@xe_module_load@load.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-7/igt@xe_module_load@load.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-3/igt@xe_module_load@load.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-3/igt@xe_module_load@load.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-1/igt@xe_module_load@load.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-1/igt@xe_module_load@load.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-8/igt@xe_module_load@load.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-8/igt@xe_module_load@load.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-1/igt@xe_module_load@load.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-1/igt@xe_module_load@load.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-5/igt@xe_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-2/igt@xe_module_load@load.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-8/igt@xe_module_load@load.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-2/igt@xe_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-1/igt@xe_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-3/igt@xe_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-lnl-4/igt@xe_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-1/igt@xe_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-1/igt@xe_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-1/igt@xe_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-8/igt@xe_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-8/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-8/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-8/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-4/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-4/igt@xe_module_load@load.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-4/igt@xe_module_load@load.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-4/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-3/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-3/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-3/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-2/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-2/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-2/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-2/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-7/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-7/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-7/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-5/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-5/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-5/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-lnl-5/igt@xe_module_load@load.html
    - shard-bmg:          ([PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [PASS][135], [PASS][136], [PASS][137], [PASS][138], [PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143], [SKIP][144], [PASS][145], [PASS][146], [PASS][147], [PASS][148], [PASS][149], [PASS][150], [PASS][151], [PASS][152], [PASS][153], [PASS][154], [PASS][155], [PASS][156], [PASS][157], [PASS][158], [PASS][159], [PASS][160], [PASS][161], [PASS][162], [PASS][163], [PASS][164], [PASS][165], [PASS][166], [PASS][167]) ([Intel XE#2457]) -> ([DMESG-FAIL][168], [DMESG-FAIL][169], [DMESG-FAIL][170], [DMESG-FAIL][171], [DMESG-FAIL][172], [DMESG-FAIL][173], [DMESG-FAIL][174], [DMESG-FAIL][175], [DMESG-FAIL][176], [DMESG-FAIL][177], [DMESG-FAIL][178], [DMESG-FAIL][179], [DMESG-FAIL][180], [DMESG-FAIL][181], [DMESG-FAIL][182], [DMESG-FAIL][183], [DMESG-FAIL][184], [DMESG-FAIL][185], [DMESG-FAIL][186], [DMESG-FAIL][187], [DMESG-FAIL][188], [DMESG-FAIL][189], [DMESG-FAIL][190], [DMESG-FAIL][191])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-7/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-7/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-2/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-2/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-6/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-7/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-7/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-7/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-6/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-4/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-1/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-5/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-3/igt@xe_module_load@load.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-3/igt@xe_module_load@load.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-3/igt@xe_module_load@load.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-2/igt@xe_module_load@load.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-5/igt@xe_module_load@load.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-3/igt@xe_module_load@load.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-5/igt@xe_module_load@load.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-1/igt@xe_module_load@load.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-1/igt@xe_module_load@load.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-1/igt@xe_module_load@load.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-1/igt@xe_module_load@load.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-4/igt@xe_module_load@load.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-6/igt@xe_module_load@load.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-5/igt@xe_module_load@load.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-4/igt@xe_module_load@load.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-3/igt@xe_module_load@load.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-4/igt@xe_module_load@load.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-5/igt@xe_module_load@load.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-1/igt@xe_module_load@load.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-4/igt@xe_module_load@load.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-1/igt@xe_module_load@load.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-4/igt@xe_module_load@load.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-2/igt@xe_module_load@load.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-8/igt@xe_module_load@load.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-8/igt@xe_module_load@load.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-1/igt@xe_module_load@load.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-7/igt@xe_module_load@load.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-7/igt@xe_module_load@load.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-8/igt@xe_module_load@load.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-8/igt@xe_module_load@load.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-8/igt@xe_module_load@load.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-4/igt@xe_module_load@load.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-3/igt@xe_module_load@load.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-3/igt@xe_module_load@load.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-5/igt@xe_module_load@load.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-8/igt@xe_module_load@load.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-2/igt@xe_module_load@load.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-2/igt@xe_module_load@load.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-bmg-5/igt@xe_module_load@load.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-4/igt@xe_module_load@load.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-4/igt@xe_module_load@load.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-4/igt@xe_module_load@load.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-8/igt@xe_module_load@load.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-8/igt@xe_module_load@load.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-8/igt@xe_module_load@load.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-1/igt@xe_module_load@load.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-1/igt@xe_module_load@load.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-7/igt@xe_module_load@load.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-7/igt@xe_module_load@load.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-7/igt@xe_module_load@load.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-2/igt@xe_module_load@load.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-2/igt@xe_module_load@load.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-6/igt@xe_module_load@load.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-6/igt@xe_module_load@load.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-6/igt@xe_module_load@load.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-6/igt@xe_module_load@load.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-6/igt@xe_module_load@load.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-3/igt@xe_module_load@load.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-3/igt@xe_module_load@load.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-3/igt@xe_module_load@load.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-3/igt@xe_module_load@load.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-3/igt@xe_module_load@load.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-bmg-5/igt@xe_module_load@load.html
    - shard-dg2-set2:     ([PASS][192], [PASS][193], [PASS][194], [PASS][195], [PASS][196], [PASS][197], [PASS][198], [PASS][199], [PASS][200], [PASS][201], [PASS][202], [PASS][203], [PASS][204], [PASS][205], [PASS][206], [PASS][207], [PASS][208], [PASS][209], [PASS][210], [PASS][211], [PASS][212], [PASS][213], [PASS][214], [PASS][215], [PASS][216], [PASS][217], [PASS][218], [PASS][219], [PASS][220], [PASS][221], [PASS][222], [SKIP][223], [PASS][224], [PASS][225], [PASS][226], [PASS][227], [PASS][228], [PASS][229], [PASS][230], [PASS][231], [PASS][232], [PASS][233], [PASS][234], [PASS][235], [PASS][236], [PASS][237], [PASS][238], [PASS][239], [PASS][240], [SKIP][241], [PASS][242], [PASS][243], [PASS][244]) ([Intel XE#378]) -> ([DMESG-FAIL][245], [DMESG-FAIL][246], [DMESG-FAIL][247], [DMESG-FAIL][248], [DMESG-FAIL][249], [DMESG-FAIL][250], [DMESG-FAIL][251], [DMESG-FAIL][252], [DMESG-FAIL][253], [DMESG-FAIL][254], [DMESG-FAIL][255], [DMESG-FAIL][256], [DMESG-FAIL][257], [DMESG-FAIL][258], [DMESG-FAIL][259], [DMESG-FAIL][260], [DMESG-FAIL][261], [DMESG-FAIL][262], [DMESG-FAIL][263], [DMESG-FAIL][264], [DMESG-FAIL][265], [DMESG-FAIL][266], [DMESG-FAIL][267], [DMESG-FAIL][268], [DMESG-FAIL][269])
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-dg2-463/igt@xe_module_load@load.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-dg2-434/igt@xe_module_load@load.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-dg2-434/igt@xe_module_load@load.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-dg2-434/igt@xe_module_load@load.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-dg2-432/igt@xe_module_load@load.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-dg2-436/igt@xe_module_load@load.html
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-dg2-466/igt@xe_module_load@load.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-dg2-434/igt@xe_module_load@load.html
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-dg2-466/igt@xe_module_load@load.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-dg2-466/igt@xe_module_load@load.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8/shard-dg2-463/igt@xe_module_load@load.html
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   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/shard-dg2-432/igt@xe_module_load@load.html

  
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378


Build changes
-------------

  * Linux: xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8 -> xe-pw-155866v2

  IGT_8587: 8587
  xe-3929-7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8: 7ba235d0e0cf055008e2f28b3b3bea6673bfc6c8
  xe-pw-155866v2: 155866v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v2/index.html

[-- Attachment #2: Type: text/html, Size: 40954 bytes --]

Re: [PATCH v2 19/22] drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx

[Joonas Lahtinen]

(Switching to my @linux.intel.com address)

Quoting Lucas De Marchi (2025-10-16 16:59:34)
> On Thu, Oct 16, 2025 at 06:52:20AM +0000, Muqthyar Ahmed, Syed Abdul wrote:
> >> -----Original Message-----
> >> From: De Marchi, Lucas <lucas.demarchi@intel.com>
> >> On Wed, Oct 15, 2025 at 05:07:42PM -0700, Matt Roper wrote:
> >> >On Wed, Oct 15, 2025 at 03:06:34PM -0700, Lucas De Marchi wrote:
> >> >> Current implementation of compute walker has dependency on GPU/SW
> >> >> Stack which requires SW/UMD to wait for event from KMD to indicate
> >> >> PIPE_CONTROL interrupt was done. This created latency on SW stack.
> >> >>
> >> >> This feature adds support to generate completion interrupt from GPGPU
> >> >> walker which does not support MSIx and avoid software using Pipe
> >> >> control drain/idle latency.
> >> >>
> >> >> Suggested-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> >> >> Signed-off-by: S A Muqthyar Ahmed
> >> >> <syed.abdul.muqthyar.ahmed@intel.com>
> >> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >> >> ---

<SNIP>

> >> >> +++ b/drivers/gpu/drm/xe/xe_irq.c
> >> >> @@ -149,6 +149,12 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
> >> >>   if (xe_device_uc_enabled(xe)) {
> >> >>           common_mask = GT_RENDER_USER_INTERRUPT |
> >> >>                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
> >> >> +
> >> >> +         /* Enable Compute Walker Interrupt for non-MSIX platforms
> >> */
> >> >> +         if (GRAPHICS_VERx100(xe) >= 3511 &&
> >> !xe_device_has_msix(xe)) {
> >> >> +                 rcs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
> >> >> +                 ccs_mask |= GT_COMPUTE_WALKER_INTERRUPT;
> >> >> +         }
> >> >
> >> >It probably doesn't matter since our execlist support isn't functional
> >> >and we only really support GuC-based submission, but technically
> >> >shouldn't this be outside the 'uc_enabled' check so that we'd also get
> >> >these interrupts if we tried to use execlist submission?
> >> >
> >> >BTW, is there more support for this coming in future patches?  Without
> >> >MSI-X, what's the mechanism by which userspace finds out this interrupt
> >> >has fired?  We're unmasking/enabling the interrupt here, but I don't
> >> >see how anything happens once the interrupts start showing up.
> >>
> >> Himal / Syed: any detail missing here?
> >>
> >> Yes, AFAIU we are still missing the change in the irq handler to get the
> >> notification and the mechanism on exec queue creation for registration.
> >>
> >
> >For exec queue creation control can only be supported on  platform supporting MSIX .
> >This is for non-MSIX/MSI.
> >For this irq handler just need to wake up waiting kernel or user thread and that is happening for all irq lines in handler so nothing special need to be handled.
> 
> yes, we will wake up the waiters on the ufence, but then how is this
> different than the pipectl notification?

The action of waking up threads and userspace to wait for the interrupt
is all the same. It is all about having a faster way to generate that
interrupt from the batch buffer without having to issue pipe control.

> Is this part just so
> userspace can be compatible with non-msix platform?

The difference between MSI-X and non-MSI-X implementation is just that
with MSI-X, there are multiple vectors so less latency for kernel driver
to search which threads to wake up. Other than that it should be the
same here, just a faster way to generate interrupt from batch buffer.

Regards, Joonas

> 
> Lucas De Marchi?