From: Suraj Kandpal <suraj.kandpal@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: ankit.k.nautiyal@intel.com, arun.r.murthy@intel.com,
uma.shankar@intel.com, gustavo.sousa@intel.com,
lucas.demarchi@intel.com, Suraj Kandpal <suraj.kandpal@intel.com>
Subject: [PATCH 00/25] Enable LT PHY
Date: Wed, 15 Oct 2025 09:37:52 +0530 [thread overview]
Message-ID: <20251015040817.3431297-1-suraj.kandpal@intel.com> (raw)
From Xe3p we move on to LT PHY from CX0 PHY. This series implements
all the required enable/disable sequences, DP/HDMI PLL state calculation
using tables, HDMI Algorithm to calculate PLL state and the reverse Algo
where we use the state to calculate the portclock, new Vswing tables and
programming required to get everything up and running.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Suraj Kandpal (25):
drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers
drm/i915/cx0: Change register bit naming for powerdown values
drm/i915/ltphy: Phy lane reset for LT Phy
drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT Phy
drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence
drm/i915/ltphy: Read PHY_VDR_0_CONFIG register
drm/i915/ltphy: Add LT Phy Programming recipe tables
drm/i915/ltphy: Program the VDR PLL registers for LT PHY
drm/i915/ltphy: Update the ltpll config table value for eDP
drm/i915/ltphy: Enable SSC during port clock programming
drm/i915/ltphy: Add function to calculate LT PHY port clock
drm/i915/ltphy: Program the P2P Transaction flow for LT Phy
drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL steps
drm/i915/ltphy: Program the rest of the LT Phy Enable sequence
drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequence
drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences
drm/i915/ddi: Define LT Phy Swing tables
drm/i915/ltphy: Program LT Phy Voltage Swing
drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence
drm/i915/ltphy: Define the LT Phy state compare function
drm/i915/ltphy: Define function to readout LT Phy PLL state
drm/i915/ltphy: Define LT PHY PLL state verify function
drm/i915/display: Aux Enable and Display powerwell timeouts
drm/i915/ltphy: Modify the step that need to by skipped
drm/i915/ltphy: Implement HDMI Algo for Pll state
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 64 +-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 22 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 15 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 34 +-
.../drm/i915/display/intel_ddi_buf_trans.c | 81 +-
.../drm/i915/display/intel_ddi_buf_trans.h | 9 +
drivers/gpu/drm/i915/display/intel_display.c | 33 +-
.../i915/display/intel_display_power_well.c | 23 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 31 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 11 +
drivers/gpu/drm/i915/display/intel_lt_phy.c | 2303 +++++++++++++++++
drivers/gpu/drm/i915/display/intel_lt_phy.h | 47 +
.../gpu/drm/i915/display/intel_lt_phy_regs.h | 78 +
.../drm/i915/display/intel_modeset_verify.c | 2 +
drivers/gpu/drm/xe/Makefile | 1 +
16 files changed, 2708 insertions(+), 47 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_lt_phy.c
create mode 100644 drivers/gpu/drm/i915/display/intel_lt_phy.h
create mode 100644 drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
--
2.34.1
next reply other threads:[~2025-10-15 4:08 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-15 4:07 Suraj Kandpal [this message]
2025-10-15 4:07 ` [PATCH 01/25] drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers Suraj Kandpal
2025-10-20 11:10 ` Jani Nikula
2025-10-22 4:05 ` Kandpal, Suraj
2025-10-22 7:57 ` Murthy, Arun R
2025-10-15 4:07 ` [PATCH 02/25] drm/i915/cx0: Change register bit naming for powerdown values Suraj Kandpal
2025-10-22 8:01 ` Murthy, Arun R
2025-10-15 4:07 ` [PATCH 03/25] drm/i915/ltphy: Phy lane reset for LT Phy Suraj Kandpal
2025-10-22 8:41 ` Murthy, Arun R
2025-10-22 9:01 ` Kandpal, Suraj
2025-10-15 4:07 ` [PATCH 04/25] drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL " Suraj Kandpal
2025-10-22 8:49 ` Murthy, Arun R
2025-10-22 8:58 ` Kandpal, Suraj
2025-10-22 9:06 ` Murthy, Arun R
2025-10-15 4:07 ` [PATCH 05/25] drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence Suraj Kandpal
2025-10-22 9:13 ` Murthy, Arun R
2025-10-15 4:07 ` [PATCH 06/25] drm/i915/ltphy: Read PHY_VDR_0_CONFIG register Suraj Kandpal
2025-10-23 7:29 ` Murthy, Arun R
2025-10-15 4:07 ` [PATCH 07/25] drm/i915/ltphy: Add LT Phy Programming recipe tables Suraj Kandpal
2025-10-23 7:36 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 08/25] drm/i915/ltphy: Program the VDR PLL registers for LT PHY Suraj Kandpal
2025-10-23 7:40 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 09/25] drm/i915/ltphy: Update the ltpll config table value for eDP Suraj Kandpal
2025-10-23 7:42 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 10/25] drm/i915/ltphy: Enable SSC during port clock programming Suraj Kandpal
2025-10-23 7:49 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 11/25] drm/i915/ltphy: Add function to calculate LT PHY port clock Suraj Kandpal
2025-10-15 4:08 ` [PATCH 12/25] drm/i915/ltphy: Program the P2P Transaction flow for LT Phy Suraj Kandpal
2025-10-23 8:18 ` Murthy, Arun R
2025-10-23 9:24 ` Kandpal, Suraj
2025-10-23 9:32 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 13/25] drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL steps Suraj Kandpal
2025-10-23 8:27 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 14/25] drm/i915/ltphy: Program the rest of the LT Phy Enable sequence Suraj Kandpal
2025-10-23 8:32 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 15/25] drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequence Suraj Kandpal
2025-10-23 8:40 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 16/25] drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences Suraj Kandpal
2025-10-23 8:43 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 17/25] drm/i915/ddi: Define LT Phy Swing tables Suraj Kandpal
2025-10-23 9:33 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 18/25] drm/i915/ltphy: Program LT Phy Voltage Swing Suraj Kandpal
2025-10-24 6:39 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 19/25] drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence Suraj Kandpal
2025-10-24 7:00 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 20/25] drm/i915/ltphy: Define the LT Phy state compare function Suraj Kandpal
2025-10-24 7:03 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 21/25] drm/i915/ltphy: Define function to readout LT Phy PLL state Suraj Kandpal
2025-10-24 7:14 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 22/25] drm/i915/ltphy: Define LT PHY PLL state verify function Suraj Kandpal
2025-10-24 7:26 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 23/25] drm/i915/display: Aux Enable and Display powerwell timeouts Suraj Kandpal
2025-10-24 7:32 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 24/25] drm/i915/ltphy: Modify the step that need to by skipped Suraj Kandpal
2025-10-24 7:33 ` Murthy, Arun R
2025-10-15 4:08 ` [PATCH 25/25] drm/i915/ltphy: Implement HDMI Algo for Pll state Suraj Kandpal
2025-10-15 4:22 ` ✗ CI.checkpatch: warning for Enable LT PHY Patchwork
2025-10-15 4:23 ` ✓ CI.KUnit: success " Patchwork
2025-10-15 4:38 ` ✗ CI.checksparse: warning " Patchwork
2025-10-15 5:00 ` ✓ Xe.CI.BAT: success " Patchwork
2025-10-15 14:28 ` ✗ Xe.CI.Full: failure " Patchwork
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