Intel-XE Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Suraj Kandpal <suraj.kandpal@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: ankit.k.nautiyal@intel.com, arun.r.murthy@intel.com,
	uma.shankar@intel.com, gustavo.sousa@intel.com,
	lucas.demarchi@intel.com, Suraj Kandpal <suraj.kandpal@intel.com>
Subject: [PATCH 23/25] drm/i915/display: Aux Enable and Display powerwell timeouts
Date: Wed, 15 Oct 2025 09:38:15 +0530	[thread overview]
Message-ID: <20251015040817.3431297-24-suraj.kandpal@intel.com> (raw)
In-Reply-To: <20251015040817.3431297-1-suraj.kandpal@intel.com>

From XE3P we can now poll if the AUX power is up or down define the
timeouts for each respectively.

Bspec: 68967
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../i915/display/intel_display_power_well.c   | 23 +++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 5e88b930f5aa..1fc2e9450f03 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1864,18 +1864,37 @@ static void xelpdp_aux_power_well_enable(struct intel_display *display,
 	 * expected to just wait a fixed 600us after raising the request
 	 * bit.
 	 */
-	usleep_range(600, 1200);
+
+	if (DISPLAY_VER(display) >= 35) {
+		if (intel_de_wait_for_set(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
+					  XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 2))
+			drm_warn(display->drm,
+				 "Timeout waiting for PHY %c AUX channel power to be up\n",
+				 phy_name(phy));
+	} else {
+		usleep_range(600, 1200);
+	}
 }
 
 static void xelpdp_aux_power_well_disable(struct intel_display *display,
 					  struct i915_power_well *power_well)
 {
 	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
+	enum phy phy = icl_aux_pw_to_phy(display, power_well);
 
 	intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
 		     0);
-	usleep_range(10, 30);
+
+	if (DISPLAY_VER(display) >= 35) {
+		if (intel_de_wait_for_clear(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
+					    XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1))
+			drm_warn(display->drm,
+				 "Timeout waiting for PHY %c AUX channel to powerdown\n",
+				 phy_name(phy));
+	} else {
+		usleep_range(10, 30);
+	}
 }
 
 static bool xelpdp_aux_power_well_enabled(struct intel_display *display,
-- 
2.34.1


  parent reply	other threads:[~2025-10-15  4:09 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-15  4:07 [PATCH 00/25] Enable LT PHY Suraj Kandpal
2025-10-15  4:07 ` [PATCH 01/25] drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers Suraj Kandpal
2025-10-20 11:10   ` Jani Nikula
2025-10-22  4:05     ` Kandpal, Suraj
2025-10-22  7:57   ` Murthy, Arun R
2025-10-15  4:07 ` [PATCH 02/25] drm/i915/cx0: Change register bit naming for powerdown values Suraj Kandpal
2025-10-22  8:01   ` Murthy, Arun R
2025-10-15  4:07 ` [PATCH 03/25] drm/i915/ltphy: Phy lane reset for LT Phy Suraj Kandpal
2025-10-22  8:41   ` Murthy, Arun R
2025-10-22  9:01     ` Kandpal, Suraj
2025-10-15  4:07 ` [PATCH 04/25] drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL " Suraj Kandpal
2025-10-22  8:49   ` Murthy, Arun R
2025-10-22  8:58     ` Kandpal, Suraj
2025-10-22  9:06       ` Murthy, Arun R
2025-10-15  4:07 ` [PATCH 05/25] drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence Suraj Kandpal
2025-10-22  9:13   ` Murthy, Arun R
2025-10-15  4:07 ` [PATCH 06/25] drm/i915/ltphy: Read PHY_VDR_0_CONFIG register Suraj Kandpal
2025-10-23  7:29   ` Murthy, Arun R
2025-10-15  4:07 ` [PATCH 07/25] drm/i915/ltphy: Add LT Phy Programming recipe tables Suraj Kandpal
2025-10-23  7:36   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 08/25] drm/i915/ltphy: Program the VDR PLL registers for LT PHY Suraj Kandpal
2025-10-23  7:40   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 09/25] drm/i915/ltphy: Update the ltpll config table value for eDP Suraj Kandpal
2025-10-23  7:42   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 10/25] drm/i915/ltphy: Enable SSC during port clock programming Suraj Kandpal
2025-10-23  7:49   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 11/25] drm/i915/ltphy: Add function to calculate LT PHY port clock Suraj Kandpal
2025-10-15  4:08 ` [PATCH 12/25] drm/i915/ltphy: Program the P2P Transaction flow for LT Phy Suraj Kandpal
2025-10-23  8:18   ` Murthy, Arun R
2025-10-23  9:24     ` Kandpal, Suraj
2025-10-23  9:32       ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 13/25] drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL steps Suraj Kandpal
2025-10-23  8:27   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 14/25] drm/i915/ltphy: Program the rest of the LT Phy Enable sequence Suraj Kandpal
2025-10-23  8:32   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 15/25] drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequence Suraj Kandpal
2025-10-23  8:40   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 16/25] drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences Suraj Kandpal
2025-10-23  8:43   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 17/25] drm/i915/ddi: Define LT Phy Swing tables Suraj Kandpal
2025-10-23  9:33   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 18/25] drm/i915/ltphy: Program LT Phy Voltage Swing Suraj Kandpal
2025-10-24  6:39   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 19/25] drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence Suraj Kandpal
2025-10-24  7:00   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 20/25] drm/i915/ltphy: Define the LT Phy state compare function Suraj Kandpal
2025-10-24  7:03   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 21/25] drm/i915/ltphy: Define function to readout LT Phy PLL state Suraj Kandpal
2025-10-24  7:14   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 22/25] drm/i915/ltphy: Define LT PHY PLL state verify function Suraj Kandpal
2025-10-24  7:26   ` Murthy, Arun R
2025-10-15  4:08 ` Suraj Kandpal [this message]
2025-10-24  7:32   ` [PATCH 23/25] drm/i915/display: Aux Enable and Display powerwell timeouts Murthy, Arun R
2025-10-15  4:08 ` [PATCH 24/25] drm/i915/ltphy: Modify the step that need to by skipped Suraj Kandpal
2025-10-24  7:33   ` Murthy, Arun R
2025-10-15  4:08 ` [PATCH 25/25] drm/i915/ltphy: Implement HDMI Algo for Pll state Suraj Kandpal
2025-10-15  4:22 ` ✗ CI.checkpatch: warning for Enable LT PHY Patchwork
2025-10-15  4:23 ` ✓ CI.KUnit: success " Patchwork
2025-10-15  4:38 ` ✗ CI.checksparse: warning " Patchwork
2025-10-15  5:00 ` ✓ Xe.CI.BAT: success " Patchwork
2025-10-15 14:28 ` ✗ Xe.CI.Full: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20251015040817.3431297-24-suraj.kandpal@intel.com \
    --to=suraj.kandpal@intel.com \
    --cc=ankit.k.nautiyal@intel.com \
    --cc=arun.r.murthy@intel.com \
    --cc=gustavo.sousa@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=lucas.demarchi@intel.com \
    --cc=uma.shankar@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox