Re: [PATCH 24/25] drm/i915/ltphy: Modify the step that need to by skipped

["Murthy, Arun R" <arun.r.murthy@intel.com>]

On 15-10-2025 09:38, Suraj Kandpal wrote:
> Bspec has changed the non tbt pll enable sequence now we skip
> steps 5-17 if no config change has occurred.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>   drivers/gpu/drm/i915/display/intel_lt_phy.c | 63 +++++++++++----------
>   1 file changed, 33 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 72c3ba787e2a..0262c3a97020 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1664,40 +1664,43 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   					 XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
>   			drm_warn(display->drm, "PHY %c PLL MacCLK Ack assertion Timeout after %dus.\n",
>   				 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
> +
> +		/*
> +		 * 13. Ungate the forward clock by setting
> +		 * PORT_CLOCK_CTL[Forward Clock Ungate] = 1.
> +		 */
> +		intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> +			     XELPDP_FORWARD_CLOCK_UNGATE,
> +			     XELPDP_FORWARD_CLOCK_UNGATE);
> +
> +		/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
> +		intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> +			     lane_phy_pulse_status,
> +			     lane_phy_pulse_status);
> +		/*
> +		 * 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over
> +		 * PHY message bus for Owned PHY Lanes.
> +		 */
> +		rate_update = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_RATE_UPDATE);
> +		rate_update &= ~LT_PHY_RATE_CONTROL_VDR_UPDATE;
> +		intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_RATE_UPDATE,
> +				   rate_update, MB_WRITE_COMMITTED);
> +
> +		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
> +		if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
> +					 lane_phy_pulse_status, lane_phy_pulse_status,
> +					 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
> +			drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
> +				 phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
> +
> +		/* 17. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
> +		intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> +			     lane_phy_pulse_status,
> +			     lane_phy_pulse_status);
>   	} else {
>   		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), crtc_state->port_clock);
>   	}
>   
> -	/* 13. Ungate the forward clock by setting PORT_CLOCK_CTL[Forward Clock Ungate] = 1. */
> -	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> -		     XELPDP_FORWARD_CLOCK_UNGATE,
> -		     XELPDP_FORWARD_CLOCK_UNGATE);
> -
> -	/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
> -	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> -		     lane_phy_pulse_status,
> -		     lane_phy_pulse_status);
> -	/*
> -	 * 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over PHY message bus for
> -	 * Owned PHY Lanes.
> -	 */
> -	rate_update = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_RATE_UPDATE);
> -	rate_update &= ~LT_PHY_RATE_CONTROL_VDR_UPDATE;
> -	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_RATE_UPDATE,
> -			   rate_update, MB_WRITE_COMMITTED);
> -
> -	/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
> -	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
> -				 lane_phy_pulse_status, lane_phy_pulse_status,
> -				 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
> -		drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
> -			 phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
> -
> -	/* 17. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
> -	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> -		     lane_phy_pulse_status,
> -		     lane_phy_pulse_status);
> -
>   	/*
>   	 * 18. Follow the Display Voltage Frequency Switching - Sequence After Frequency Change.
>   	 * We handle this step in bxt_set_cdclk()