Re: [PATCH 14/25] drm/i915/ltphy: Program the rest of the LT Phy Enable sequence

["Murthy, Arun R" <arun.r.murthy@intel.com>]

On 15-10-2025 09:38, Suraj Kandpal wrote:
> Program the rest of the LT Phy Non TBT PLL Enable sequence. This
> can be done in a single patch since the rest of the prequistie
> functions are already coded in.
>
> Bspec: 74492, 69701
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>   drivers/gpu/drm/i915/display/intel_cx0_phy.c |  4 +--
>   drivers/gpu/drm/i915/display/intel_cx0_phy.h |  2 ++
>   drivers/gpu/drm/i915/display/intel_lt_phy.c  | 28 ++++++++++++++++++++
>   3 files changed, 32 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index b060a5007921..914b215d8bd4 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -409,8 +409,8 @@ static void __intel_cx0_rmw(struct intel_encoder *encoder,
>   		__intel_cx0_write(encoder, lane, addr, val, committed);
>   }
>   
> -static void intel_cx0_rmw(struct intel_encoder *encoder,
> -			  u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed)
> +void intel_cx0_rmw(struct intel_encoder *encoder,
> +		   u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed)
>   {
>   	u8 lane;
>   
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index a5446686b23b..f0f0efa2d48b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -53,6 +53,8 @@ void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
>   bool intel_cx0_is_hdmi_frl(u32 clock);
>   u8 intel_cx0_read(struct intel_encoder *encoder,
>   		  u8 lane_mask, u16 addr);
> +void intel_cx0_rmw(struct intel_encoder *encoder,
> +		   u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed);
>   void intel_cx0_write(struct intel_encoder *encoder,
>   		     u8 lane_mask, u16 addr, u8 data, bool committed);
>   int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 08a5ed27d2d7..9e4868a15e7d 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1496,6 +1496,11 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   	enum phy phy = intel_encoder_to_phy(encoder);
>   	enum port port = encoder->port;
>   	intel_wakeref_t wakeref = 0;
> +	u32 lane_phy_pulse_status = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES
> +					? (XE3PLPDP_LANE_PHY_PULSE_STATUS(0) |
> +					   XE3PLPDP_LANE_PHY_PULSE_STATUS(1))
> +					: XE3PLPDP_LANE_PHY_PULSE_STATUS(0);
> +	u8 rate_update;
>   
>   	wakeref = intel_lt_phy_transaction_begin(encoder);
>   
> @@ -1550,6 +1555,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   		 * Change. We handle this step in bxt_set_cdclk().
>   		 */
>   		/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
> +		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> +			       crtc_state->port_clock);
> +
>   		/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
>   		intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
>   			     XELPDP_LANE_PCLK_PLL_REQUEST(0),
> @@ -1572,17 +1580,37 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   		     XELPDP_FORWARD_CLOCK_UNGATE);
>   
>   	/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
> +	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> +		     lane_phy_pulse_status,
> +		     lane_phy_pulse_status);
>   	/*
>   	 * 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over PHY message bus for
>   	 * Owned PHY Lanes.
>   	 */
> +	rate_update = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_RATE_UPDATE);
> +	rate_update &= ~LT_PHY_RATE_CONTROL_VDR_UPDATE;
> +	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_RATE_UPDATE,
> +			   rate_update, MB_WRITE_COMMITTED);
> +
>   	/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
> +	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
> +				 lane_phy_pulse_status, lane_phy_pulse_status,
> +				 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
> +		drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
> +			 phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
> +
>   	/* 17. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
> +	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> +		     lane_phy_pulse_status,
> +		     lane_phy_pulse_status);
> +
>   	/*
>   	 * 18. Follow the Display Voltage Frequency Switching - Sequence After Frequency Change.
>   	 * We handle this step in bxt_set_cdclk()
>   	 */
>   	/* 19. Move the PHY powerdown state to Active and program to enable/disable transmitters */
> +	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
> +					       XELPDP_P0_STATE_ACTIVE);
>   
>   	intel_lt_phy_transaction_end(encoder, wakeref);
>   }