Re: [PATCH 01/25] drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers

[Jani Nikula <jani.nikula@linux.intel.com>]

On Wed, 15 Oct 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Add LT Phy related VDR and pipe registers into its own new file.
>
> Bspec: 74500
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_lt_phy_regs.h  | 27 +++++++++++++++++++
>  1 file changed, 27 insertions(+)
>  create mode 100644 drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> new file mode 100644
> index 000000000000..499acb1975d1
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> @@ -0,0 +1,27 @@
> +/* SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __INTEL_LT_PHY_REGS_H__
> +#define __INTEL_LT_PHY_REGS_H__
> +
> +#include "i915_reg_defs.h"
> +#include "intel_display_limits.h"

Unnecessary.

> +
> +/* LT Phy Vendor Register */
> +#define LT_PHY_VDR_0_CONFIG	0xC02
> +#define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
> +#define LT_PHY_VDR_1_CONFIG	0xC03
> +#define  LT_PHY_VDR_RATE_ENCODING_MASK	REG_GENMASK8(6, 3)
> +#define  LT_PHY_VDR_MODE_ENCODING_MASK	REG_GENMASK8(2, 0)
> +#define LT_PHY_VDR_2_CONFIG	0xCC3
> +
> +#define LT_PHY_VDR_X_ADDR_MSB(idx)	(0xC04 + 0x6 * (idx))
> +#define LT_PHY_VDR_X_ADDR_LSB(idx)	(0xC05 + 0x6 * (idx))
> +
> +#define LT_PHY_VDR_X_DATAY(idx, y)	((0xC06 + (3 - (y))) + 0x6 * (idx))
> +
> +#define LT_PHY_RATE_UPDATE		0xCC4
> +
> +#endif /* __INTEL_LT_PHY_REGS_H__ */

-- 
Jani Nikula, Intel