[PATCH 01/21] drm/i915: Optimize pipe irq handling on bdw

[PATCH 01/21] drm/i915: Optimize pipe irq handling on bdw

[Ben Widawsky]

From: Daniel Vetter <daniel.vetter@ffwll.ch>

We have a per-pipe bit in the master irq control register, so use it.
This allows us to drop the masks for aggregate interrupt bits and be a
bit more explicit in the code. It also removes one indentation level.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_irq.c | 40 +++++++++++++++++++---------------------
 drivers/gpu/drm/i915/i915_reg.h |  5 +----
 2 files changed, 20 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 54338cf..c04fbbf 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1749,6 +1749,7 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 	u32 master_ctl;
 	irqreturn_t ret = IRQ_NONE;
 	uint32_t tmp = 0;
+	enum pipe pipe;
 
 	atomic_inc(&dev_priv->irq_received);
 
@@ -1777,31 +1778,28 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 		}
 	}
 
-	if (master_ctl & GEN8_DE_IRQS) {
-		int de_ret = 0;
-		int pipe;
-		for_each_pipe(pipe) {
-			uint32_t pipe_iir;
-
-			pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
-			if (pipe_iir & GEN8_PIPE_VBLANK)
-				drm_handle_vblank(dev, pipe);
+	for_each_pipe(pipe) {
+		uint32_t pipe_iir;
 
-			if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
-				intel_prepare_page_flip(dev, pipe);
-				intel_finish_page_flip_plane(dev, pipe);
-			}
+		if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
+			continue;
 
-			if (pipe_iir & GEN8_DE_PIPE_IRQ_ERRORS)
-				DRM_ERROR("Errors on pipe %c\n", 'A' + pipe);
+		pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
+		if (pipe_iir & GEN8_PIPE_VBLANK)
+			drm_handle_vblank(dev, pipe);
 
-			if (pipe_iir) {
-				de_ret++;
-				ret = IRQ_HANDLED;
-				I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
-			}
+		if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
+			intel_prepare_page_flip(dev, pipe);
+			intel_finish_page_flip_plane(dev, pipe);
 		}
-		if (!de_ret)
+
+		if (pipe_iir & GEN8_DE_PIPE_IRQ_ERRORS)
+			DRM_ERROR("Errors on pipe %c\n", 'A' + pipe);
+
+		if (pipe_iir) {
+			ret = IRQ_HANDLED;
+			I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
+		} else
 			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
 	}
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2b9e66c..f150eda 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4031,15 +4031,12 @@
 #define  GEN8_DE_PIPE_C_IRQ		(1<<18)
 #define  GEN8_DE_PIPE_B_IRQ		(1<<17)
 #define  GEN8_DE_PIPE_A_IRQ		(1<<16)
+#define  GEN8_DE_PIPE_IRQ(pipe)		(1<<(16+pipe))
 #define  GEN8_GT_VECS_IRQ		(1<<6)
 #define  GEN8_GT_VCS2_IRQ		(1<<3)
 #define  GEN8_GT_VCS1_IRQ		(1<<2)
 #define  GEN8_GT_BCS_IRQ		(1<<1)
 #define  GEN8_GT_RCS_IRQ		(1<<0)
-/* Lazy definition */
-#define  GEN8_GT_IRQS			0x000000ff
-#define  GEN8_DE_IRQS			0x01ff0000
-#define  GEN8_RSVD_IRQS			0xB700ff00
 
 #define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
 #define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
-- 
1.8.4.2

[PATCH 02/21] drm/i915: Fix up the bdw pipe interrupt enable lists

[Ben Widawsky]

From: Daniel Vetter <daniel.vetter@ffwll.ch>

- Pipe underrun can't just be enabled, we need some support code like
  on ilk-hsw to make this happen. So drop it for now.
- CRC error is a special mode of the CRC hardware that we don't use,
  so again drop it. Real CRC support for bdw will be added later.
- All the other error bits are about faults, so rename the #define and
  adjust the output.

v2: Use pipe_name as pointed out by Ville. Ville's comment was on a
previous patch, but it was easier to squash in here.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_irq.c | 10 ++++++----
 drivers/gpu/drm/i915/i915_reg.h |  9 ++++-----
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c04fbbf..e1bfc85 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1793,8 +1793,11 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 			intel_finish_page_flip_plane(dev, pipe);
 		}
 
-		if (pipe_iir & GEN8_DE_PIPE_IRQ_ERRORS)
-			DRM_ERROR("Errors on pipe %c\n", 'A' + pipe);
+		if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
+			DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
+				  pipe_name(pipe),
+				  pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
+		}
 
 		if (pipe_iir) {
 			ret = IRQ_HANDLED;
@@ -2863,9 +2866,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 {
 	struct drm_device *dev = dev_priv->dev;
 	uint32_t de_pipe_enables = GEN8_PIPE_FLIP_DONE |
-				   GEN8_PIPE_SCAN_LINE_EVENT |
 				   GEN8_PIPE_VBLANK |
-				   GEN8_DE_PIPE_IRQ_ERRORS;
+				   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
 	int pipe;
 	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_enables;
 	dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_enables;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f150eda..9e75883 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4064,11 +4064,10 @@
 #define  GEN8_PIPE_SCAN_LINE_EVENT	(1 << 2)
 #define  GEN8_PIPE_VSYNC		(1 << 1)
 #define  GEN8_PIPE_VBLANK		(1 << 0)
-#define GEN8_DE_PIPE_IRQ_ERRORS	(GEN8_PIPE_UNDERRUN | \
-				 GEN8_PIPE_CDCLK_CRC_ERROR | \
-				 GEN8_PIPE_CURSOR_FAULT | \
-				 GEN8_PIPE_SPRITE_FAULT | \
-				 GEN8_PIPE_PRIMARY_FAULT)
+#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
+	(GEN8_PIPE_CURSOR_FAULT | \
+	 GEN8_PIPE_SPRITE_FAULT | \
+	 GEN8_PIPE_PRIMARY_FAULT)
 
 #define GEN8_DE_PORT_ISR 0x44440
 #define GEN8_DE_PORT_IMR 0x44444
-- 
1.8.4.2

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[PATCH 03/21] drm/i915: Wire up port A aux channel

[Ben Widawsky]

From: Daniel Vetter <daniel.vetter@ffwll.ch>

Useful for dp aux to work better. Also stop enabling the port A
hotplug event - eDP panels are expected to fire that interupt and
we're not really ready to deal with them. This is consistent with how
we handle port A on ilk-hsw.

The more important bit is that we must delay the enabling of hotplug
interrupts until all the encoders are fully set up. But we need irq
support earlier than that, hence hotplug interrupts can only be
enabled in the ->hpd_irq_setup callback.

v2: Drop the _HOTPLUG, it isn't (Ville).

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_irq.c | 19 +++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h |  3 ++-
 2 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e1bfc85..9304ce3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1778,6 +1778,21 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 		}
 	}
 
+	if (master_ctl & GEN8_DE_PORT_IRQ) {
+		tmp = I915_READ(GEN8_DE_PORT_IIR);
+		if (tmp & GEN8_AUX_CHANNEL_A)
+			dp_aux_irq_handler(dev);
+		else if (tmp)
+			DRM_ERROR("Unexpected DE Port interrupt\n");
+		else
+			DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
+
+		if (tmp) {
+			I915_WRITE(GEN8_DE_PORT_IIR, tmp);
+			ret = IRQ_HANDLED;
+		}
+	}
+
 	for_each_pipe(pipe) {
 		uint32_t pipe_iir;
 
@@ -2883,8 +2898,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	}
 	POSTING_READ(GEN8_DE_PIPE_ISR(0));
 
-	I915_WRITE(GEN8_DE_PORT_IMR, ~_PORT_DP_A_HOTPLUG);
-	I915_WRITE(GEN8_DE_PORT_IER, _PORT_DP_A_HOTPLUG);
+	I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
+	I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
 	POSTING_READ(GEN8_DE_PORT_IER);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9e75883..fe8cb4c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4073,7 +4073,8 @@
 #define GEN8_DE_PORT_IMR 0x44444
 #define GEN8_DE_PORT_IIR 0x44448
 #define GEN8_DE_PORT_IER 0x4444c
-#define  _PORT_DP_A_HOTPLUG		(1 << 3)
+#define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
+#define  GEN8_AUX_CHANNEL_A		(1 << 0)
 
 #define GEN8_DE_MISC_ISR 0x44460
 #define GEN8_DE_MISC_IMR 0x44464
-- 
1.8.4.2

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[PATCH 04/21] drm/i915: Wire up PCH interrupts for bdw

[Ben Widawsky]

From: Daniel Vetter <daniel.vetter@ffwll.ch>

Gives us hotplug, gmbus, dp aux and south errors (underrun
reporting!).

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_irq.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9304ce3..4420944 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1821,6 +1821,22 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
 	}
 
+	if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
+		/*
+		 * FIXME(BDW): Assume for now that the new interrupt handling
+		 * scheme also closed the SDE interrupt handling race we've seen
+		 * on older pch-split platforms. But this needs testing.
+		 */
+		u32 pch_iir = I915_READ(SDEIIR);
+
+		cpt_irq_handler(dev, pch_iir);
+
+		if (pch_iir) {
+			I915_WRITE(SDEIIR, pch_iir);
+			ret = IRQ_HANDLED;
+		}
+	}
+
 	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
 	POSTING_READ(GEN8_MASTER_IRQ);
 
-- 
1.8.4.2

[PATCH 05/21] drm/i915: Wire up pipe CRC support for bdw

[Ben Widawsky]

From: Daniel Vetter <daniel.vetter@ffwll.ch>

The layout of the CRC registers is the same as on hsw, only the
interrupt handling has changed a bit. So trivial to wire up, yay!

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_irq.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4420944..a06de99 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1808,6 +1808,9 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 			intel_finish_page_flip_plane(dev, pipe);
 		}
 
+		if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
+			hsw_pipe_crc_irq_handler(dev, pipe);
+
 		if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
 			DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
 				  pipe_name(pipe),
@@ -2898,6 +2901,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	struct drm_device *dev = dev_priv->dev;
 	uint32_t de_pipe_enables = GEN8_PIPE_FLIP_DONE |
 				   GEN8_PIPE_VBLANK |
+				   GEN8_PIPE_CDCLK_CRC_DONE |
 				   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
 	int pipe;
 	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_enables;
-- 
1.8.4.2

[PATCH 06/21] drm/i915: Optimize gen8_enable|disable_vblank functions

[Ben Widawsky]

From: Daniel Vetter <daniel.vetter@ffwll.ch>

Let's cache the IMR value like on other platforms. This is needed to
implement the underrun reporting since then we'll have two places that
change the same register at runtime.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_irq.c | 18 ++++++------------
 1 file changed, 6 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a06de99..9ea0df2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2203,17 +2203,14 @@ static int gen8_enable_vblank(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	unsigned long irqflags;
-	uint32_t imr;
 
 	if (!i915_pipe_enabled(dev, pipe))
 		return -EINVAL;
 
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-	imr = I915_READ(GEN8_DE_PIPE_IMR(pipe));
-	if ((imr & GEN8_PIPE_VBLANK) == 1) {
-		I915_WRITE(GEN8_DE_PIPE_IMR(pipe), imr & ~GEN8_PIPE_VBLANK);
-		POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
-	}
+	dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
+	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
+	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 	return 0;
 }
@@ -2270,17 +2267,14 @@ static void gen8_disable_vblank(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	unsigned long irqflags;
-	uint32_t imr;
 
 	if (!i915_pipe_enabled(dev, pipe))
 		return;
 
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-	imr = I915_READ(GEN8_DE_PIPE_IMR(pipe));
-	if ((imr & GEN8_PIPE_VBLANK) == 0) {
-		I915_WRITE(GEN8_DE_PIPE_IMR(pipe), imr | GEN8_PIPE_VBLANK);
-		POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
-	}
+	dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
+	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
+	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 }
 
-- 
1.8.4.2

[PATCH 07/21] drm/i915: Wire up cpu fifo underrun reporting support for bdw

[Ben Widawsky]

From: Daniel Vetter <daniel.vetter@ffwll.ch>

HW engineers have listened and given us again a real interrupt with
masking and status regs. Yay!

For consistency with other platforms call the #define FIFO_UNDERRUN.
Eventually we also might need to have some enable/disable functions
for bdw display interrupts, but for now open-coding seems to be good
enough.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_irq.c | 25 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h |  2 +-
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9ea0df2..bf71e35 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -270,6 +270,21 @@ static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
 	}
 }
 
+static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
+						  enum pipe pipe, bool enable)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	assert_spin_locked(&dev_priv->irq_lock);
+
+	if (enable)
+		dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
+	else
+		dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
+	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
+	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
+}
+
 /**
  * ibx_display_interrupt_update - update SDEIMR
  * @dev_priv: driver private
@@ -382,6 +397,8 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 		ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 	else if (IS_GEN7(dev))
 		ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
+	else if (IS_GEN8(dev))
+		broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
 
 done:
 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
@@ -1811,6 +1828,13 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 		if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
 			hsw_pipe_crc_irq_handler(dev, pipe);
 
+		if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
+			if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
+								  false))
+				DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
+						 pipe_name(pipe));
+		}
+
 		if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
 			DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
 				  pipe_name(pipe),
@@ -2896,6 +2920,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	uint32_t de_pipe_enables = GEN8_PIPE_FLIP_DONE |
 				   GEN8_PIPE_VBLANK |
 				   GEN8_PIPE_CDCLK_CRC_DONE |
+				   GEN8_PIPE_FIFO_UNDERRUN |
 				   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
 	int pipe;
 	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_enables;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fe8cb4c..40fe67b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4053,7 +4053,7 @@
 #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
 #define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
 #define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
-#define  GEN8_PIPE_UNDERRUN		(1 << 31)
+#define  GEN8_PIPE_FIFO_UNDERRUN	(1 << 31)
 #define  GEN8_PIPE_CDCLK_CRC_ERROR	(1 << 29)
 #define  GEN8_PIPE_CDCLK_CRC_DONE	(1 << 28)
 #define  GEN8_PIPE_CURSOR_FAULT		(1 << 10)
-- 
1.8.4.2

[PATCH 08/21] drm/i915: Mask the vblank interrupt on bdw by default

[Ben Widawsky]

From: Daniel Vetter <daniel.vetter@ffwll.ch>

Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_irq.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index bf71e35..1ce5722 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2917,15 +2917,15 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 {
 	struct drm_device *dev = dev_priv->dev;
-	uint32_t de_pipe_enables = GEN8_PIPE_FLIP_DONE |
-				   GEN8_PIPE_VBLANK |
-				   GEN8_PIPE_CDCLK_CRC_DONE |
-				   GEN8_PIPE_FIFO_UNDERRUN |
-				   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
+	uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
+		GEN8_PIPE_CDCLK_CRC_DONE |
+		GEN8_PIPE_FIFO_UNDERRUN |
+		GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
+	uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK;
 	int pipe;
-	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_enables;
-	dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_enables;
-	dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_enables;
+	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
+	dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
+	dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
 
 	for_each_pipe(pipe) {
 		u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
-- 
1.8.4.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 09/21] drm/i915/bdw: Take render error interrupt out of the mask

[Ben Widawsky]

From: Daniel Vetter <daniel.vetter@ffwll.ch>

The handling of the error interrupts isn't wired up at all. And it
hasn't been ever since ilk happened, so don't bother.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e32c08a..b620337 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2132,8 +2132,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
 
 	if (INTEL_INFO(dev)->gen >= 8) {
 		ring->irq_enable_mask =
-			(GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT) |
-			GT_RENDER_CS_MASTER_ERROR_INTERRUPT;
+			GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
 		ring->irq_get = gen8_ring_get_irq;
 		ring->irq_put = gen8_ring_put_irq;
 		ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
-- 
1.8.4.2

[PATCH 10/21] drm/i915/bdw: Add missed break for forcewake mmio

[Ben Widawsky]

commit 771bafb1fef22206d96942e41826e317374df51e
Author: Ben Widawsky <benjamin.widawsky@intel.com>
Date:   Sat Nov 2 21:07:00 2013 -0700

    drm/i915/bdw: Handle forcewake for writes on gen8

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_uncore.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 5080f6a..db3a154 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -585,6 +585,7 @@ void intel_uncore_init(struct drm_device *dev)
 		dev_priv->uncore.funcs.mmio_readw  = gen6_read16;
 		dev_priv->uncore.funcs.mmio_readl  = gen6_read32;
 		dev_priv->uncore.funcs.mmio_readq  = gen6_read64;
+		break;
 	case 7:
 	case 6:
 		if (IS_HASWELL(dev)) {
-- 
1.8.4.2

[PATCH 11/21] drm/i915/bdw: Add BDW PCH check first

[Ben Widawsky]

Early platforms use the same PCH as HSW, and to avoid triggering the
!ULT, and !HSW warnings, simply put it first in the search.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f5220fb..925c911 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -448,17 +448,17 @@ void intel_detect_pch(struct drm_device *dev)
 				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 				WARN_ON(!IS_HASWELL(dev));
 				WARN_ON(IS_ULT(dev));
-			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
-				dev_priv->pch_type = PCH_LPT;
-				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
-				WARN_ON(!IS_HASWELL(dev));
-				WARN_ON(!IS_ULT(dev));
 			} else if (IS_BROADWELL(dev)) {
 				dev_priv->pch_type = PCH_LPT;
 				dev_priv->pch_id =
 					INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 				DRM_DEBUG_KMS("This is Broadwell, assuming "
 					      "LynxPoint LP PCH\n");
+			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
+				dev_priv->pch_type = PCH_LPT;
+				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
+				WARN_ON(!IS_HASWELL(dev));
+				WARN_ON(!IS_ULT(dev));
 			} else {
 				goto check_next;
 			}
-- 
1.8.4.2

[PATCH 12/21] drm/i915/bdw: posting read the full 64b PTE

[Ben Widawsky]

For our posting read we were reading only 32b on BDW. There was a FIXME
already - the warning is annoying.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 638fd09..3620a1b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -899,12 +899,9 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 	 * registers and PTEs are within the same BAR that they are potentially
 	 * of NUMA access patterns. Therefore, even with the way we assume
 	 * hardware should work, we must keep this posting read for paranoia.
-	 *
-	 * FIXME(BDW): The check is bogus - we read 32bit but the ptes are
-	 * 64bit.
 	 */
 	if (i != 0)
-		WARN_ON(readl(&gtt_entries[i-1])
+		WARN_ON(readq(&gtt_entries[i-1])
 			!= gen8_pte_encode(addr, level, true));
 
 #if 0 /* TODO: Still needed on GEN8? */
-- 
1.8.4.2

[PATCH 13/21] drm/i915/bdw: Initialize BDW forcewake vfuncs

[Ben Widawsky]

Somehow this got missed or dropped during development. The simulator
does not use forcewake, so it's entirely possible it never worked
correctly. After the mmio rework, this will end up in an OOPs, and the
system will not boot.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_uncore.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index db3a154..ca789b1 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -534,7 +534,7 @@ void intel_uncore_init(struct drm_device *dev)
 	if (IS_VALLEYVIEW(dev)) {
 		dev_priv->uncore.funcs.force_wake_get = vlv_force_wake_get;
 		dev_priv->uncore.funcs.force_wake_put = vlv_force_wake_put;
-	} else if (IS_HASWELL(dev)) {
+	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 		dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get;
 		dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put;
 	} else if (IS_IVYBRIDGE(dev)) {
-- 
1.8.4.2

[PATCH 14/21] drm/i915: Abstract backlight registers a bit

[Ben Widawsky]

Many GENs generally perform the same actions just on different
registers. This is true going forward as well. To ease the transition a
bit, extract the common code where possible.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_panel.c | 25 +++++++++++++------------
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index de15186..e8a749a 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -430,24 +430,25 @@ static u32 intel_panel_compute_brightness(struct drm_device *dev, u32 val)
 static u32 intel_panel_get_backlight(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 val;
+	u32 reg, val;
 	unsigned long flags;
 
 	spin_lock_irqsave(&dev_priv->backlight.lock, flags);
 
-	if (HAS_PCH_SPLIT(dev)) {
-		val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
-	} else {
-		val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
-		if (INTEL_INFO(dev)->gen < 4)
-			val >>= 1;
+	if (HAS_PCH_SPLIT(dev))
+		reg = BLC_PWM_CPU_CTL;
+	else
+		reg = BLC_PWM_CTL;
 
-		if (is_backlight_combination_mode(dev)) {
-			u8 lbpc;
+	val = I915_READ(reg) & BACKLIGHT_DUTY_CYCLE_MASK;
+	if (INTEL_INFO(dev)->gen < 4)
+		val >>= 1;
 
-			pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
-			val *= lbpc;
-		}
+	if (is_backlight_combination_mode(dev)) {
+		u8 lbpc;
+
+		pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
+		val *= lbpc;
 	}
 
 	val = intel_panel_compute_brightness(dev, val);
-- 
1.8.4.2

[PATCH 15/21] drm/i915/bdw: GEN8 backlight support

[Ben Widawsky]

Prior to Haswell the CPU control register for backlight
(BLC_PWM_CPU_CTL) toggled the PCH baclight pin for us. This made some
sense as there was no pin on the CPU. With Haswell came the introduction
of a CPU backlight pin, but the interface was still controlled by
software with the same mechnism. Behind the scenes, hardware did all the
dirty work for us.

Broadwell no longer provides this for free. If we want to use the PCH
backlight pin [1] then we have to set the override bit BLC_PWM_PCH_CTL1
and program BLC_PWM_PCH_CTL2 for the PWM values.

This patch implements that. This patch is compile tested only, and given
that I rarely if ever touch this code, careful review is welcome.

[1] According to Art, we know of no devices that exist which use the CPU
pin (and remember it has existed already on HSW). If such a device does
exist, we'll have to handle it properly - this is left as TODO until
then.

CC: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_panel.c | 25 +++++++++++++++++++++----
 1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index e8a749a..8ecd14a 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -435,7 +435,9 @@ static u32 intel_panel_get_backlight(struct drm_device *dev)
 
 	spin_lock_irqsave(&dev_priv->backlight.lock, flags);
 
-	if (HAS_PCH_SPLIT(dev))
+	if (IS_BROADWELL(dev))
+		reg = BLC_PWM_PCH_CTL2;
+	else if (HAS_PCH_SPLIT(dev))
 		reg = BLC_PWM_CPU_CTL;
 	else
 		reg = BLC_PWM_CTL;
@@ -462,8 +464,15 @@ static u32 intel_panel_get_backlight(struct drm_device *dev)
 static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
-	I915_WRITE(BLC_PWM_CPU_CTL, val | level);
+	u32 reg, val;
+
+	if (IS_BROADWELL(dev))
+		reg = BLC_PWM_PCH_CTL2;
+	else
+		reg = BLC_PWM_CPU_CTL;
+
+	val = I915_READ(reg) & ~BACKLIGHT_DUTY_CYCLE_MASK;
+	I915_WRITE(reg, val | level);
 }
 
 static void intel_panel_actually_set_backlight(struct drm_device *dev,
@@ -615,7 +624,15 @@ void intel_panel_enable_backlight(struct drm_device *dev,
 		POSTING_READ(reg);
 		I915_WRITE(reg, tmp | BLM_PWM_ENABLE);
 
-		if (HAS_PCH_SPLIT(dev) &&
+		if (IS_BROADWELL(dev) &&
+		    !(WARN_ON(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE))) {
+			/* Broadwell requires PCH override to drive the PCH
+			 * backlight pin. The above will configure the CPU
+			 * backlight pin, which we don't plan to use */
+			tmp = I915_READ(BLC_PWM_PCH_CTL1);
+			tmp |= BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE;
+			I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
+		} else if (HAS_PCH_SPLIT(dev) &&
 		    !(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) {
 			tmp = I915_READ(BLC_PWM_PCH_CTL1);
 			tmp |= BLM_PCH_PWM_ENABLE;
-- 
1.8.4.2

[PATCH 16/21] drm/i915/bdw: Remove semaphore disabled DRM_INFO

[Ben Widawsky]

It serves no real purpose and is displayed (in a non-maskable fashion)
on every object sync.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 925c911..989be12 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -481,7 +481,6 @@ bool i915_semaphore_is_enabled(struct drm_device *dev)
 	/* Until we get further testing... */
 	if (IS_GEN8(dev)) {
 		WARN_ON(!i915_preliminary_hw_support);
-		DRM_INFO("Semaphores disabled GEN8\n");
 		return 0;
 	}
 
-- 
1.8.4.2

[PATCH 17/21] drm/i915/bdw: Do gen6 style reset for gen8

[Ben Widawsky]

This patch existed before, but was lost over time.

Note that reset is still somewhat problematic in my limited testing (ie.
module_reload will not pass) but it can be disabled with a module
parameter, and support should be considered preliminary anyway.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_uncore.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index ca789b1..d37e6b7 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -782,6 +782,7 @@ static int gen6_do_reset(struct drm_device *dev)
 int intel_gpu_reset(struct drm_device *dev)
 {
 	switch (INTEL_INFO(dev)->gen) {
+	case 8:
 	case 7:
 	case 6: return gen6_do_reset(dev);
 	case 5: return ironlake_do_reset(dev);
-- 
1.8.4.2

[PATCH 18/21] drm/i915/bdw: Free correct number of ppgtt pages

[Ben Widawsky]

I am unclear how this got messed up in the shuffle, but it did.

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 3620a1b..5a3cc31 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -335,8 +335,8 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 		kfree(ppgtt->gen8_pt_dma_addr[i]);
 	}
 
-	__free_pages(ppgtt->gen8_pt_pages, ppgtt->num_pt_pages << PAGE_SHIFT);
-	__free_pages(ppgtt->pd_pages, ppgtt->num_pd_pages << PAGE_SHIFT);
+	__free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT));
+	__free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
 }
 
 /**
-- 
1.8.4.2

[PATCH 19/21] drm/i915: Never allow VGA on LPT LP PCH

[Ben Widawsky]

Sometimes the VBT lies, I guess? I can't explain why this occurs, but it
does on the early platforms we have.

Since it seems never unsafe to do this, I don't feel we need any quirk
or warnings.

Cc: Paulo Zanoni <przanoni@gmail.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_display.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6ced1a1..00b0bf9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5671,6 +5671,7 @@ static void lpt_disable_clkout_dp(struct drm_device *dev)
 
 static void lpt_init_pch_refclk(struct drm_device *dev)
 {
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_mode_config *mode_config = &dev->mode_config;
 	struct intel_encoder *encoder;
 	bool has_vga = false;
@@ -5683,7 +5684,7 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
 		}
 	}
 
-	if (has_vga)
+	if (dev_priv->pch_id != INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && has_vga)
 		lpt_enable_clkout_dp(dev, true, true);
 	else
 		lpt_disable_clkout_dp(dev);
-- 
1.8.4.2

[PATCH 20/21] drm/i915/bdw: Add comment about gen8 HWS PGA

[Ben Widawsky]

This confused me some many times that I think it is appropriate to add a
small comment to instruct the reader of the code that it is indeed doing
what it is supposed to do.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b620337..c2f09d45 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -965,6 +965,7 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 	} else if (IS_GEN6(ring->dev)) {
 		mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 	} else {
+		/* XXX: gen8 returns to sanity */
 		mmio = RING_HWS_PGA(ring->mmio_base);
 	}
 
-- 
1.8.4.2

[PATCH 21/21] drm/i915/bdw: Limit GTT to 2GB

[Ben Widawsky]

Because of the way in which we're allocating the pages for the Aliasing
PPGTT, we cannot actually successfully alloc enough space for anything
greater than 2GB.

Instead of a quick hack to fix this, we should defer until we have the
real solution in place (allocating much less contiguous space).

This wasn't found sooner because we didn't not have any systems
supporting more than a 2GB GTT.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 5a3cc31..f69bdc7 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1239,6 +1239,11 @@ static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
 	bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
 	if (bdw_gmch_ctl)
 		bdw_gmch_ctl = 1 << bdw_gmch_ctl;
+	if (bdw_gmch_ctl > 4) {
+		WARN_ON(!i915_preliminary_hw_support);
+		return 4<<20;
+	}
+
 	return bdw_gmch_ctl << 20;
 }
 
-- 
1.8.4.2

Re: [PATCH 19/21] drm/i915: Never allow VGA on LPT LP PCH

[Paulo Zanoni]

2013/11/8 Ben Widawsky <benjamin.widawsky@intel.com>:
> Sometimes the VBT lies, I guess? I can't explain why this occurs, but it
> does on the early platforms we have.

We don't decide to init/not-init VGA based on the VBT. Function
intel_setup_outputs has "if (!IS_ULT(dev)) intel_crtc_init(dev)". As
far as I remember, we're temporarily assuming BDW has the LPT-LP PCH
right? AFAIK, only ULT machines are supposed to have a LP PCH, so
maybe we should be treating your BDW machines as ULTs? Did you
physically check whether we have the CRT port or not? Maybe we should
request some clarification on how these PCH-LP/ULT combinations will
be handled in BDW.

>
> Since it seems never unsafe to do this, I don't feel we need any quirk
> or warnings.
>
> Cc: Paulo Zanoni <przanoni@gmail.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6ced1a1..00b0bf9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5671,6 +5671,7 @@ static void lpt_disable_clkout_dp(struct drm_device *dev)
>
>  static void lpt_init_pch_refclk(struct drm_device *dev)
>  {
> +       struct drm_i915_private *dev_priv = dev->dev_private;
>         struct drm_mode_config *mode_config = &dev->mode_config;
>         struct intel_encoder *encoder;
>         bool has_vga = false;
> @@ -5683,7 +5684,7 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
>                 }
>         }
>
> -       if (has_vga)
> +       if (dev_priv->pch_id != INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && has_vga)

As suggested above, this is really not the place to do this. Please
see intel_setup_outputs().

>                 lpt_enable_clkout_dp(dev, true, true);
>         else
>                 lpt_disable_clkout_dp(dev);
> --
> 1.8.4.2
>



-- 
Paulo Zanoni

Re: [PATCH 19/21] drm/i915: Never allow VGA on LPT LP PCH

[Ben Widawsky]

On Thu, Nov 07, 2013 at 09:40:49PM -0800, Ben Widawsky wrote:
> Sometimes the VBT lies, I guess? I can't explain why this occurs, but it
> does on the early platforms we have.
> 
> Since it seems never unsafe to do this, I don't feel we need any quirk
> or warnings.
> 
> Cc: Paulo Zanoni <przanoni@gmail.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

This one is nak'd
-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 14/21] drm/i915: Abstract backlight registers a bit

[Daniel Vetter]

On Thu, Nov 07, 2013 at 09:40:44PM -0800, Ben Widawsky wrote:
> Many GENs generally perform the same actions just on different
> registers. This is true going forward as well. To ease the transition a
> bit, extract the common code where possible.
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

As explained on internal irc I'm rather reluctant to pull in refactoring
patches into -fixes just for bdw enabling. Especially for fragile code
like the backlight.

So I'd just go with adding a copy-pasted version of set/get/enable for
broadwell. That should also fit in with Jani's plans for 3.14 with the
complete backlight refactoring. Adding Jani so he can explain what he'd
like.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 14/21] drm/i915: Abstract backlight registers a bit

[Jani Nikula]

On Fri, 08 Nov 2013, Daniel Vetter <daniel@ffwll.ch> wrote:
> So I'd just go with adding a copy-pasted version of set/get/enable for
> broadwell. That should also fit in with Jani's plans for 3.14 with the
> complete backlight refactoring. Adding Jani so he can explain what he'd
> like.

I'd like
http://mid.gmane.org/1384161177-29196-1-git-send-email-jani.nikula@intel.com

-- 
Jani Nikula, Intel Open Source Technology Center

Re: [PATCH 21/21] drm/i915/bdw: Limit GTT to 2GB

[Daniel Vetter]

On Thu, Nov 07, 2013 at 09:40:51PM -0800, Ben Widawsky wrote:
> Because of the way in which we're allocating the pages for the Aliasing
> PPGTT, we cannot actually successfully alloc enough space for anything
> greater than 2GB.
> 
> Instead of a quick hack to fix this, we should defer until we have the
> real solution in place (allocating much less contiguous space).
> 
> This wasn't found sooner because we didn't not have any systems
> supporting more than a 2GB GTT.
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

I've just slurped in the remaining patchs from this series (with the
exception of the backlight stuff, since that's taken care of already).
-Daniel
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 5a3cc31..f69bdc7 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1239,6 +1239,11 @@ static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
>  	bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
>  	if (bdw_gmch_ctl)
>  		bdw_gmch_ctl = 1 << bdw_gmch_ctl;
> +	if (bdw_gmch_ctl > 4) {
> +		WARN_ON(!i915_preliminary_hw_support);
> +		return 4<<20;
> +	}
> +
>  	return bdw_gmch_ctl << 20;
>  }
>  
> -- 
> 1.8.4.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch