From: Dave Jiang <dave.jiang@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Dan Williams <dan.j.williams@intel.com>,
Dave Jiang <dave.jiang@intel.com>,
dave@stgolabs.net, jonathan.cameron@huawei.com,
alison.schofield@intel.com, ira.weiny@intel.com,
rrichter@amd.com, ming.li@zohomail.com
Subject: [PATCH v2 00/10] cxl: Delay HB port and switch dport probing until endpoint dev probe
Date: Tue, 6 May 2025 17:43:00 -0700 [thread overview]
Message-ID: <20250507004310.3536991-1-dave.jiang@intel.com> (raw)
This series attempts to delay the setup of dports and Host Bridge (HB) register
until when the endpoint device (memdev) is being probed. At this point,
the CXL link is established and all the devices along the CXL link path up to
the Root Port (RP) should be active.
And hopefully this help a bit with Robert's issue raised in the "Inactive
downstream port handling" series [1]. Testing would be appreicated. Thank you!
[1]: https://lore.kernel.org/linux-cxl/67c8a0cc23ec_24b64294f6@dwillia2-xfh.jf.intel.com.notmuch/
Dave Jiang (10):
cxl/region: Add decoder check to check_commit_order()
cxl: Saperate out CXL dport->id vs actual dport hardware id
cxl: Rename find_dport() to provide better function intent
cxl: Remove adding of port_num via devm_cxl_add_dport()
cxl: Defer hardware dport->port_id assignment and registers probing
cxl/test: Add workaround for cxl_test for cxl_core calling mocked functions
cxl: Change sslbis handler to only handle single dport
cxl: Add helper to detect top of CXL device topology
cxl: Create an xarray to tie a host bridge to the cxl_root
cxl: Move enumeration of hostbridge ports to the memdev probe path
drivers/cxl/acpi.c | 143 ++++++-----
drivers/cxl/core/cdat.c | 23 +-
drivers/cxl/core/core.h | 4 +
drivers/cxl/core/hdm.c | 45 ++--
drivers/cxl/core/pci.c | 60 ++++-
drivers/cxl/core/port.c | 353 +++++++++++++++++++++++----
drivers/cxl/core/region.c | 7 +-
drivers/cxl/cxl.h | 50 +++-
drivers/cxl/port.c | 20 +-
tools/testing/cxl/Kbuild | 4 +-
tools/testing/cxl/cxl_core_exports.c | 31 +++
tools/testing/cxl/exports.h | 17 ++
tools/testing/cxl/test/cxl.c | 5 +-
tools/testing/cxl/test/mock.c | 40 +--
14 files changed, 611 insertions(+), 191 deletions(-)
create mode 100644 tools/testing/cxl/exports.h
base-commit: b4432656b36e5cc1d50a1f2dc15357543add530e
--
2.49.0
next reply other threads:[~2025-05-07 0:43 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-07 0:43 Dave Jiang [this message]
2025-05-07 0:43 ` [PATCH v2 01/10] cxl/region: Add decoder check to check_commit_order() Dave Jiang
2025-05-08 19:54 ` Alison Schofield
2025-05-09 0:55 ` Li Ming
2025-05-13 4:46 ` Gregory Price
2025-05-20 11:14 ` Jonathan Cameron
2025-05-20 16:13 ` Dave Jiang
2025-05-07 0:43 ` [PATCH v2 02/10] cxl: Saperate out CXL dport->id vs actual dport hardware id Dave Jiang
2025-05-08 20:08 ` Alison Schofield
2025-05-15 16:35 ` Dave Jiang
2025-05-09 0:51 ` Li Ming
2025-05-15 16:33 ` Dave Jiang
2025-05-09 9:14 ` Alejandro Lucero Palau
2025-05-15 16:35 ` Dave Jiang
2025-05-13 5:04 ` Gregory Price
2025-05-15 16:38 ` Dave Jiang
2025-05-20 11:19 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 03/10] cxl: Rename find_dport() to provide better function intent Dave Jiang
2025-05-09 0:55 ` Li Ming
2025-05-09 9:20 ` Alejandro Lucero Palau
2025-05-15 17:04 ` Dave Jiang
2025-05-19 16:33 ` Dave Jiang
2025-05-20 11:21 ` Jonathan Cameron
2025-05-13 5:07 ` Gregory Price
2025-05-07 0:43 ` [PATCH v2 04/10] cxl: Remove adding of port_num via devm_cxl_add_dport() Dave Jiang
2025-05-09 0:56 ` Li Ming
2025-05-13 5:13 ` Gregory Price
2025-05-20 11:23 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 05/10] cxl: Defer hardware dport->port_id assignment and registers probing Dave Jiang
2025-05-08 4:50 ` Li Ming
2025-05-13 15:43 ` Gregory Price
2025-05-15 22:03 ` Dave Jiang
2025-05-20 11:26 ` Jonathan Cameron
2025-05-20 16:33 ` Dave Jiang
2025-05-20 12:27 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 06/10] cxl/test: Add workaround for cxl_test for cxl_core calling mocked functions Dave Jiang
2025-05-20 12:31 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 07/10] cxl: Change sslbis handler to only handle single dport Dave Jiang
2025-05-13 15:48 ` Gregory Price
2025-05-20 12:32 ` Jonathan Cameron
2025-05-20 21:53 ` Dave Jiang
2025-05-07 0:43 ` [PATCH v2 08/10] cxl: Add helper to detect top of CXL device topology Dave Jiang
2025-05-13 15:49 ` Gregory Price
2025-05-13 16:12 ` Dave Jiang
2025-05-15 17:03 ` Gregory Price
2025-05-16 15:47 ` Dave Jiang
2025-05-20 12:34 ` Jonathan Cameron
2025-05-20 21:55 ` Dave Jiang
2025-05-07 0:43 ` [PATCH v2 09/10] cxl: Create an xarray to tie a host bridge to the cxl_root Dave Jiang
2025-05-13 16:01 ` Gregory Price
2025-05-20 12:53 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 10/10] cxl: Move enumeration of hostbridge ports to the memdev probe path Dave Jiang
2025-05-20 13:11 ` Jonathan Cameron
2025-05-20 21:59 ` Dave Jiang
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