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From: Gregory Price <gourry@gourry.net>
To: Dave Jiang <dave.jiang@intel.com>
Cc: linux-cxl@vger.kernel.org,
	Dan Williams <dan.j.williams@intel.com>,
	dave@stgolabs.net, jonathan.cameron@huawei.com,
	alison.schofield@intel.com, ira.weiny@intel.com,
	rrichter@amd.com, ming.li@zohomail.com
Subject: Re: [PATCH v2 05/10] cxl: Defer hardware dport->port_id assignment and registers probing
Date: Tue, 13 May 2025 11:43:34 -0400	[thread overview]
Message-ID: <aCNopruv5rUV2PBr@gourry-fedora-PF4VCD3F> (raw)
In-Reply-To: <20250507004310.3536991-6-dave.jiang@intel.com>

On Tue, May 06, 2025 at 05:43:05PM -0700, Dave Jiang wrote:
> Current implementation only enumerates the dports during the port probe.
> Without an endpoint connected, the dport may not be active during port
> probe. This scheme may prevent a valid hardware dport id to be retrieved
> and MMIO registers to be read when an endpoint is hot-plugged. Move the hw
> dport id assignment and the register probing to behind memdev probe so the
> endpoint is guaranteed to be connected.
> 
> The detection of duplicate dport for add_dport() is removed. The port_id
> is not read from the hw at this point any longer. The port->id will always
> be unique since it's retrieved from an ida. The dup detection thus become
> irrelevant.
> 
> The decoders must also be updated since previously it's all done when all
> the dports are setup and now every time a dport is setup per endpoint, the
> switch target listing need to be updated with new dport.
> 

I'm finding the changes a little difficult to follow, can you lay out
the expected order of operations before and after?

Specifically there's two new guard() calls, can you explain under what
conditions those can be contended?

~Gregory

> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 70173d23139c..04e18a102d26 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
... snip ...
> +static int update_switch_decoder(struct device *dev, void *data)
> +{
> +	struct cxl_dport *dport = data;
> +	struct cxl_switch_decoder *cxlsd;
> +	struct cxl_decoder *cxld;
> +	int i;
> +
> +	if (!is_switch_decoder(dev))
> +		return 0;
> +
> +	cxlsd = to_cxl_switch_decoder(dev);
> +	cxld = &cxlsd->cxld;
> +	guard(rwsem_write)(&cxl_region_rwsem);
> +	for (i = 0; i < cxld->interleave_ways; i++) {
> +		if (cxlsd->target_map[i] == dport->port_num) {
> +			cxlsd->target[i] = dport;
> +			return 0;
> +		}
> +	}
... snip ...
> @@ -1695,6 +1798,19 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
>  				"found already registered port %s:%s\n",
>  				dev_name(&port->dev),
>  				dev_name(port->uport_dev));
> +
> +			/*
> +			 * Attempt to do single pass dport setup by checking here
> +			 * instead of doing it during port creation. Otherwise
> +			 * it still needs to check here for dports that are
> +			 * being probed with a port already created.
> +			 */
> +			scoped_guard(device, &port->dev) {
> +				rc = cxl_switch_port_dport_setup(port, dport_dev);
> +				if (rc)
> +					return rc;
> +			}
> +
... snip ...
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index a35fc5552845..4d840a6ef802 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
... snip ...
>  	/* Cache the data early to ensure is_visible() works */
> @@ -69,24 +68,7 @@ static int cxl_switch_port_probe(struct cxl_port *port)
>  	if (rc < 0)
>  		return rc;
>  
... snip ...
> -	return -ENXIO;
> +	return 0;
>  }

	return devm_cxl_port_enumerate_dports(port);


~Gregory

  parent reply	other threads:[~2025-05-13 15:43 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-07  0:43 [PATCH v2 00/10] cxl: Delay HB port and switch dport probing until endpoint dev probe Dave Jiang
2025-05-07  0:43 ` [PATCH v2 01/10] cxl/region: Add decoder check to check_commit_order() Dave Jiang
2025-05-08 19:54   ` Alison Schofield
2025-05-09  0:55   ` Li Ming
2025-05-13  4:46   ` Gregory Price
2025-05-20 11:14   ` Jonathan Cameron
2025-05-20 16:13     ` Dave Jiang
2025-05-07  0:43 ` [PATCH v2 02/10] cxl: Saperate out CXL dport->id vs actual dport hardware id Dave Jiang
2025-05-08 20:08   ` Alison Schofield
2025-05-15 16:35     ` Dave Jiang
2025-05-09  0:51   ` Li Ming
2025-05-15 16:33     ` Dave Jiang
2025-05-09  9:14   ` Alejandro Lucero Palau
2025-05-15 16:35     ` Dave Jiang
2025-05-13  5:04   ` Gregory Price
2025-05-15 16:38     ` Dave Jiang
2025-05-20 11:19   ` Jonathan Cameron
2025-05-07  0:43 ` [PATCH v2 03/10] cxl: Rename find_dport() to provide better function intent Dave Jiang
2025-05-09  0:55   ` Li Ming
2025-05-09  9:20   ` Alejandro Lucero Palau
2025-05-15 17:04     ` Dave Jiang
2025-05-19 16:33     ` Dave Jiang
2025-05-20 11:21       ` Jonathan Cameron
2025-05-13  5:07   ` Gregory Price
2025-05-07  0:43 ` [PATCH v2 04/10] cxl: Remove adding of port_num via devm_cxl_add_dport() Dave Jiang
2025-05-09  0:56   ` Li Ming
2025-05-13  5:13   ` Gregory Price
2025-05-20 11:23   ` Jonathan Cameron
2025-05-07  0:43 ` [PATCH v2 05/10] cxl: Defer hardware dport->port_id assignment and registers probing Dave Jiang
2025-05-08  4:50   ` Li Ming
2025-05-13 15:43   ` Gregory Price [this message]
2025-05-15 22:03     ` Dave Jiang
2025-05-20 11:26       ` Jonathan Cameron
2025-05-20 16:33         ` Dave Jiang
2025-05-20 12:27   ` Jonathan Cameron
2025-05-07  0:43 ` [PATCH v2 06/10] cxl/test: Add workaround for cxl_test for cxl_core calling mocked functions Dave Jiang
2025-05-20 12:31   ` Jonathan Cameron
2025-05-07  0:43 ` [PATCH v2 07/10] cxl: Change sslbis handler to only handle single dport Dave Jiang
2025-05-13 15:48   ` Gregory Price
2025-05-20 12:32   ` Jonathan Cameron
2025-05-20 21:53     ` Dave Jiang
2025-05-07  0:43 ` [PATCH v2 08/10] cxl: Add helper to detect top of CXL device topology Dave Jiang
2025-05-13 15:49   ` Gregory Price
2025-05-13 16:12     ` Dave Jiang
2025-05-15 17:03       ` Gregory Price
2025-05-16 15:47         ` Dave Jiang
2025-05-20 12:34   ` Jonathan Cameron
2025-05-20 21:55     ` Dave Jiang
2025-05-07  0:43 ` [PATCH v2 09/10] cxl: Create an xarray to tie a host bridge to the cxl_root Dave Jiang
2025-05-13 16:01   ` Gregory Price
2025-05-20 12:53   ` Jonathan Cameron
2025-05-07  0:43 ` [PATCH v2 10/10] cxl: Move enumeration of hostbridge ports to the memdev probe path Dave Jiang
2025-05-20 13:11   ` Jonathan Cameron
2025-05-20 21:59     ` Dave Jiang

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