Re: [PATCH v2 08/10] cxl: Add helper to detect top of CXL device topology

[Dave Jiang <dave.jiang@intel.com>]

On 5/15/25 10:03 AM, Gregory Price wrote:
> On Tue, May 13, 2025 at 09:12:00AM -0700, Dave Jiang wrote:
>>
>>
>> On 5/13/25 8:49 AM, Gregory Price wrote:
>>> On Tue, May 06, 2025 at 05:43:08PM -0700, Dave Jiang wrote:
>>>> Add a helper to replace the open code detection of CXL device hierarchy
>>>> root. The helper will be used for delayed hostbridge port creation later
>>>> on.
>>>>
>>>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>>>
>>> ignorant terminology question: what's the different between the
>>> "cxl hierarchy head" and "cxl root"?
>>
>> I struggle to find the correct terminology between the head of the PCI (or platform device for cxl_test) hierarchy vs the CXL one we constructed for the 'cxl_port' hierarchy. I'm open to suggestions to use better words to distinguish that. 
> 
> Is there an actual difference or they actually the same "device" - just
> abstracted differently?

One is ACPI1700:nn which is an ACPI device. The other is the PCIe root port and considered a pci_bridge device. So top of two different hierarchies. But what trips me up is cxl_test gets in the mix and this is the top of the platform device hierarchy. So finding a proper word to describe the top of that side is difficult. Otherwise I could just say pci_root or something. But I'm avoiding using the keyword "pci" in core/port.c. 

> 
> ~Gregory