Re: [PATCH v2 08/10] cxl: Add helper to detect top of CXL device topology

[Dave Jiang <dave.jiang@intel.com>]

On 5/20/25 5:34 AM, Jonathan Cameron wrote:
> On Tue, 6 May 2025 17:43:08 -0700
> Dave Jiang <dave.jiang@intel.com> wrote:
> 
>> Add a helper to replace the open code detection of CXL device hierarchy
>> root. The helper will be used for delayed hostbridge port creation later
>> on.
>>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> 
> Another one that I think can be yanked out ahead of the
> main series so we can focus on the more substantial stuff.

Yeah I'll move this to the beginning.
> 
> Reviewed-by: Jonathan Cameron <Jonsathan.Cameron@huawei.com>
> 
>> ---
>>  drivers/cxl/core/port.c | 15 ++++++++++-----
>>  1 file changed, 10 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
>> index e212bc2faada..259b217e812f 100644
>> --- a/drivers/cxl/core/port.c
>> +++ b/drivers/cxl/core/port.c
>> @@ -39,6 +39,15 @@ DECLARE_RWSEM(cxl_region_rwsem);
>>  static DEFINE_IDA(cxl_port_ida);
>>  static DEFINE_XARRAY(cxl_root_buses);
>>  
>> +/*
>> + * The terminal device in PCI is NULL and @platform_bus
>> + * for platform devices (for cxl_test)
>> + */
>> +static bool is_cxl_hierarchy_head(struct device *dev)
>> +{
>> +	return (!dev || dev == &platform_bus);
>> +}
>> +
>>  int cxl_num_decoders_committed(struct cxl_port *port)
>>  {
>>  	lockdep_assert_held(&cxl_region_rwsem);
>> @@ -1774,11 +1783,7 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
>>  		struct device *uport_dev;
>>  		struct cxl_dport *dport;
>>  
>> -		/*
>> -		 * The terminal "grandparent" in PCI is NULL and @platform_bus
>> -		 * for platform devices
>> -		 */
>> -		if (!dport_dev || dport_dev == &platform_bus)
>> +		if (is_cxl_hierarchy_head(dport_dev))
>>  			return 0;
>>  
>>  		uport_dev = dport_dev->parent;
> 
>