Re: [PATCH v2 10/10] cxl: Move enumeration of hostbridge ports to the memdev probe path

[Jonathan Cameron <Jonathan.Cameron@huawei.com>]

On Tue, 6 May 2025 17:43:10 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> Current enuemration scheme in cxl_acpi module creates the ports under the
> root port by enumerating the hostbridges after the dports under the root
> port is created. However error messages "cxl portN: Couldn't locate the
> CXL.cache and CXL.mem capability array header" is observed when certain
> platform has PCIe hotplug option turned on in BIOS. If the cxl_acpi module
> probe is running before the CXL link between the endpoint device and the
> RP is established, then the platform may not have exposed DVSEC ID 3 and/or
> DVSEC ID 7 blocks which will trigger the error message.

I think we should call out that this bit (unlike port numbers) is valid
under the CXL spec.  Whilst I think that statement in the spec is something
I'd rather wasn't there we should reflect this one isn't a hardware bug
work around (unlike port number which I think is :)


> 
> Setup an association in cxl_port to tie the host bridge device to the
> associated cxl_root. The cxl_root provides a callback that's setup
> by the cxl_acpi probe function in order to create a port per host bridge
> that was previously done during cxl_acpi probe. Add the calling of the
> callback in devm_cxl_enumerate_ports(). The observed behavior is that
> ports that are not connected to endpoint device(s) are no longer
> enumerated. This should also remove any excessive noise of port probe
> failing on those inactive ports.
> 
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>

This is a fairly fiddly change but it looks reasonable.

Just trivial style comments inline.

J
> ---
>  drivers/cxl/acpi.c      | 136 ++++++++++++++++++++++++----------------
>  drivers/cxl/core/port.c |  58 +++++++++++++++++
>  drivers/cxl/cxl.h       |   2 +
>  3 files changed, 141 insertions(+), 55 deletions(-)
> 
> diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> index 6f8630e50800..1db4d308b4b7 100644
> --- a/drivers/cxl/acpi.c
> +++ b/drivers/cxl/acpi.c
> @@ -298,8 +298,79 @@ static int cxl_acpi_qos_class(struct cxl_root *cxl_root,
>  	return cxl_acpi_evaluate_qtg_dsm(handle, coord, entries, qos_class);
>  }
>  
> +/* Note, @dev is used by mock_acpi_table_parse_cedt() */
> +struct cxl_chbs_context {
> +	struct device *dev;
> +	unsigned long long uid;
> +	resource_size_t base;
> +	u32 cxl_version;
> +	int nr_versions;
> +	u32 saved_version;
> +};
> +
> +static int cxl_get_chbs(struct device *dev, struct acpi_device *hb,
> +			struct cxl_chbs_context *ctx);
> +
> +/*
> + * A host bridge is a dport to a CFMWS decode and it is a uport to the

decoder maybe?

> + * dport (PCIe Root Ports) in the host bridge.
> + */
> +static int cxl_acpi_setup_hostbridge_uport(struct cxl_root *cxl_root,

Pity this doesn't sit in similar place to original add_host_bridge_uport
as we'd get a much nicer diff if it could.
I suppose it would be a bit too ugly to preceded this patch with
a code move patch just for that diff.  Ah well. I'll cope ;)

> +					   struct device *bridge_dev)
> +{
> +	struct cxl_port *root_port = &cxl_root->port;
> +	struct device *host = root_port->dev.parent;
> +	struct acpi_device *hb = ACPI_COMPANION(bridge_dev);
> +	resource_size_t component_reg_phys;
> +	struct acpi_pci_root *pci_root;
> +	struct cxl_chbs_context ctx;
> +	struct cxl_dport *dport;
> +	struct cxl_port *port;
> +	int rc;
> +
> +	pci_root = acpi_pci_find_root(hb->handle);
> +	dport = cxl_find_dport_by_dev(root_port, bridge_dev);
> +	if (!dport) {
> +		dev_dbg(host, "Host bridge expected and not found\n");
> +		return -ENODEV;
> +	}
> +
> +	if (dport->rch) {
> +		dev_info(bridge_dev, "host supports CXL (restricted)\n");
> +		return 0;
> +	}
> +
> +	rc = cxl_get_chbs(&hb->dev, hb, &ctx);
> +	if (rc)
> +		return rc;
> +
> +	if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) {
> +		dev_warn(bridge_dev,
> +			 "CXL CHBS version mismatch, skip port registration\n");
> +		return 0;
> +	}
> +
> +	component_reg_phys = ctx.base;
> +	if (component_reg_phys != CXL_RESOURCE_NONE)
> +		dev_dbg(&hb->dev, "CHBRC found for UID %lld: %pa\n",
> +			ctx.uid, &component_reg_phys);
> +
> +	rc = devm_cxl_register_pci_bus(host, bridge_dev, pci_root->bus);
> +	if (rc && rc != -EBUSY)
> +		return rc;
> +
> +	port = devm_cxl_add_port(host, bridge_dev, component_reg_phys, dport);
> +	if (IS_ERR(port))
> +		return PTR_ERR(port);
> +
> +	dev_info(bridge_dev, "host supports CXL\n");
> +
> +	return 0;
> +}

> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index a5a673d789f3..bbecbb04b6be 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -1808,6 +1808,60 @@ static int cxl_switch_port_dport_setup(struct cxl_port *port,
>  	return 0;
>  }
>  
> +static int get_hostbridge_port_devices(struct cxl_memdev *cxlmd,
> +				       struct device **uport_dev,
> +				       struct device **dport_dev)
> +{
> +	struct device *dev = &cxlmd->dev;
> +	struct device *iter;
> +
> +	for (iter = dev; iter; iter = grandparent(iter)) {
> +		struct device *ddev = grandparent(iter);
> +		struct device *udev;
> +
> +		udev = ddev->parent;

Odd to have ddev set at declaration and udev set here.
Pick a style - either is fine.

> +		if (is_cxl_hierarchy_head(udev->parent)) {
> +			*uport_dev = udev;
> +			*dport_dev = ddev;
> +			return 0;
> +		}
> +	}
> +
> +	return -ENODEV;
> +}
> +
> +static int cxl_hostbridge_port_setup(struct cxl_memdev *cxlmd)
> +{
> +	struct device *uport_dev, *dport_dev;
> +	struct cxl_dport *dport;
> +	struct cxl_port *port;
> +	int rc;
> +
> +	rc = get_hostbridge_port_devices(cxlmd, &uport_dev, &dport_dev);
> +	if (rc)
> +		return -ENODEV;
> +
> +	struct cxl_root *cxl_root __free(put_cxl_root) = cxl_udev_to_root(uport_dev);
> +	if (!cxl_root)
> +		return -ENODEV;
> +
> +	guard(device)(&cxl_root->port.dev);

> +	port = find_cxl_port(dport_dev, &dport);

I vaguely wonder if a __free() make sense on this. It'll autofree the NULL
much later than needed but maybe it's cleaner code?

> +	if (port) {
> +		put_device(&port->dev);
> +		return 0;
> +	}
> +
> +	if (!cxl_root->ops || !cxl_root->ops->setup_hostbridge_uport)
> +		return -EOPNOTSUPP;
> +
> +	rc = cxl_root->ops->setup_hostbridge_uport(cxl_root, uport_dev);
> +	if (rc)
> +		return rc;
> +
> +	return 0;

return cxl_root->ops....

> +}