From: Dave Jiang <dave.jiang@intel.com>
To: Gregory Price <gourry@gourry.net>
Cc: linux-cxl@vger.kernel.org,
Dan Williams <dan.j.williams@intel.com>,
dave@stgolabs.net, jonathan.cameron@huawei.com,
alison.schofield@intel.com, ira.weiny@intel.com,
rrichter@amd.com, ming.li@zohomail.com
Subject: Re: [PATCH v2 02/10] cxl: Saperate out CXL dport->id vs actual dport hardware id
Date: Thu, 15 May 2025 09:38:46 -0700 [thread overview]
Message-ID: <cf0a7968-07fd-4a26-bb40-3d410f73408a@intel.com> (raw)
In-Reply-To: <aCLS3rQxkjxiDLDx@gourry-fedora-PF4VCD3F>
On 5/12/25 10:04 PM, Gregory Price wrote:
> On Tue, May 06, 2025 at 05:43:02PM -0700, Dave Jiang wrote:
>> In preparation to allow dport to be allocated without being active, make
>> dport->id to be Linux id that enumerates the dport objects per port.
>> Keep the hardware id under dport->port_num to maintain compatibility and
>> introduce a dport->id as the enumeration id.
>>
>
> This is more for the sake of clarity/documentation than anything else.
>
> dport->port_num is the `hardware id` - i.e. what we'd find in an ACPI
> table or something. This number may not necessarily be unique
>
> dport->port_id is now a Linux ID that is unique to the device.
Yes. dport->id is guaranteed to be unique. While dport->port_num theoretically should be, but if a port is not active, it may have some bogus number in the register that clash with existing active port_num. I think Robert may have ran into this issue.
DJ
>
> For example, on my existing test system, i have this
>
> [/sys/bus/cxl/devices]# ls port1/dport*
> dport0 dport113 dport2
> [/sys/bus/cxl/devices]# ls port2/dport*
> dport113 dport2
> [/sys/bus/cxl/devices]# ls port3/dport*
> dport0
>
> I should now expect the following:
>
> [/sys/bus/cxl/devices]# ls port1/dport*
> dport0 dport1 dport2
> [/sys/bus/cxl/devices]# ls port2/dport*
> dport0 dport1
> [/sys/bus/cxl/devices]# ls port3/dport*
> dport0
>
>
> This should also apply to the root, whose dports were previously
> dictated by the host bridge numbers defined in the CHBS/DSDT.
>
> [/sys/bus/cxl/devices/root0]# ls
> dport0 dport1 dport4 dport5
>
> turns into
>
> [/sys/bus/cxl/devices/root0]# ls
> dport0 dport1 dport2 dport3
>
>
> and my decoder0.0 target list ends up similarly changed
>
> from
> [/sys/bus/cxl/devices/root0/decoder0.0]# cat target_list
> 5,4
>
> to
>
> [/sys/bus/cxl/devices/root0/decoder0.0]# cat target_list
> 3,2
>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>
> If this is all correct, I like this.
>
> Reviewed-by: Gregory Price <gourry@gourry.net>
>
> ~Gregory
next prev parent reply other threads:[~2025-05-15 16:38 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-07 0:43 [PATCH v2 00/10] cxl: Delay HB port and switch dport probing until endpoint dev probe Dave Jiang
2025-05-07 0:43 ` [PATCH v2 01/10] cxl/region: Add decoder check to check_commit_order() Dave Jiang
2025-05-08 19:54 ` Alison Schofield
2025-05-09 0:55 ` Li Ming
2025-05-13 4:46 ` Gregory Price
2025-05-20 11:14 ` Jonathan Cameron
2025-05-20 16:13 ` Dave Jiang
2025-05-07 0:43 ` [PATCH v2 02/10] cxl: Saperate out CXL dport->id vs actual dport hardware id Dave Jiang
2025-05-08 20:08 ` Alison Schofield
2025-05-15 16:35 ` Dave Jiang
2025-05-09 0:51 ` Li Ming
2025-05-15 16:33 ` Dave Jiang
2025-05-09 9:14 ` Alejandro Lucero Palau
2025-05-15 16:35 ` Dave Jiang
2025-05-13 5:04 ` Gregory Price
2025-05-15 16:38 ` Dave Jiang [this message]
2025-05-20 11:19 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 03/10] cxl: Rename find_dport() to provide better function intent Dave Jiang
2025-05-09 0:55 ` Li Ming
2025-05-09 9:20 ` Alejandro Lucero Palau
2025-05-15 17:04 ` Dave Jiang
2025-05-19 16:33 ` Dave Jiang
2025-05-20 11:21 ` Jonathan Cameron
2025-05-13 5:07 ` Gregory Price
2025-05-07 0:43 ` [PATCH v2 04/10] cxl: Remove adding of port_num via devm_cxl_add_dport() Dave Jiang
2025-05-09 0:56 ` Li Ming
2025-05-13 5:13 ` Gregory Price
2025-05-20 11:23 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 05/10] cxl: Defer hardware dport->port_id assignment and registers probing Dave Jiang
2025-05-08 4:50 ` Li Ming
2025-05-13 15:43 ` Gregory Price
2025-05-15 22:03 ` Dave Jiang
2025-05-20 11:26 ` Jonathan Cameron
2025-05-20 16:33 ` Dave Jiang
2025-05-20 12:27 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 06/10] cxl/test: Add workaround for cxl_test for cxl_core calling mocked functions Dave Jiang
2025-05-20 12:31 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 07/10] cxl: Change sslbis handler to only handle single dport Dave Jiang
2025-05-13 15:48 ` Gregory Price
2025-05-20 12:32 ` Jonathan Cameron
2025-05-20 21:53 ` Dave Jiang
2025-05-07 0:43 ` [PATCH v2 08/10] cxl: Add helper to detect top of CXL device topology Dave Jiang
2025-05-13 15:49 ` Gregory Price
2025-05-13 16:12 ` Dave Jiang
2025-05-15 17:03 ` Gregory Price
2025-05-16 15:47 ` Dave Jiang
2025-05-20 12:34 ` Jonathan Cameron
2025-05-20 21:55 ` Dave Jiang
2025-05-07 0:43 ` [PATCH v2 09/10] cxl: Create an xarray to tie a host bridge to the cxl_root Dave Jiang
2025-05-13 16:01 ` Gregory Price
2025-05-20 12:53 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 10/10] cxl: Move enumeration of hostbridge ports to the memdev probe path Dave Jiang
2025-05-20 13:11 ` Jonathan Cameron
2025-05-20 21:59 ` Dave Jiang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=cf0a7968-07fd-4a26-bb40-3d410f73408a@intel.com \
--to=dave.jiang@intel.com \
--cc=alison.schofield@intel.com \
--cc=dan.j.williams@intel.com \
--cc=dave@stgolabs.net \
--cc=gourry@gourry.net \
--cc=ira.weiny@intel.com \
--cc=jonathan.cameron@huawei.com \
--cc=linux-cxl@vger.kernel.org \
--cc=ming.li@zohomail.com \
--cc=rrichter@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox