From: Li Ming <ming.li@zohomail.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>,
dave@stgolabs.net, jonathan.cameron@huawei.com,
alison.schofield@intel.com, ira.weiny@intel.com,
rrichter@amd.com, linux-cxl@vger.kernel.org
Subject: Re: [PATCH v2 05/10] cxl: Defer hardware dport->port_id assignment and registers probing
Date: Thu, 8 May 2025 12:50:46 +0800 [thread overview]
Message-ID: <9aefbf37-c648-4662-a459-29eea2c9947d@zohomail.com> (raw)
In-Reply-To: <20250507004310.3536991-6-dave.jiang@intel.com>
On 5/7/2025 8:43 AM, Dave Jiang wrote:
> Current implementation only enumerates the dports during the port probe.
> Without an endpoint connected, the dport may not be active during port
> probe. This scheme may prevent a valid hardware dport id to be retrieved
> and MMIO registers to be read when an endpoint is hot-plugged. Move the hw
> dport id assignment and the register probing to behind memdev probe so the
> endpoint is guaranteed to be connected.
>
> The detection of duplicate dport for add_dport() is removed. The port_id
> is not read from the hw at this point any longer. The port->id will always
> be unique since it's retrieved from an ida. The dup detection thus become
> irrelevant.
>
> The decoders must also be updated since previously it's all done when all
> the dports are setup and now every time a dport is setup per endpoint, the
> switch target listing need to be updated with new dport.
>
> Link: https://lore.kernel.org/linux-cxl/20250305100123.3077031-1-rrichter@amd.com/
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
> v2:
> - Fix spelling error in commit message. (Ming)
> - Move probing to the specific dport. (Ming)
> - Add decoder update.
> - Return errors when setup dports. (Jonathan)
> - Add driver check before setup dport. (Dan)
> - Add comment on why location to do dport update. (Dan)
> ---
> drivers/cxl/core/core.h | 4 ++
> drivers/cxl/core/pci.c | 60 ++++++++++++----
> drivers/cxl/core/port.c | 152 +++++++++++++++++++++++++++++++++++-----
> drivers/cxl/cxl.h | 4 ++
> drivers/cxl/port.c | 20 +-----
> 5 files changed, 192 insertions(+), 48 deletions(-)
>
[snip]
>
> +static int port_probe_dport(struct cxl_port *port, struct device *dport_dev,
> + struct cxl_dport **probed_dport)
> +{
> + struct cxl_dport *dport;
> + unsigned long index;
> + int rc;
> +
> + device_lock_assert(&port->dev);
> + xa_for_each(&port->dports, index, dport) {
> + if (dport->dport_dev == dport_dev) {
> + rc = cxl_dport_setup(dport);
> + if (rc)
> + return rc;
> + *probed_dport = dport;
> + return 0;
> + }
> + }
> +
> + *probed_dport = NULL;
> +
> + return -ENODEV;
> +}
feels like the parameter struct cxl_dport **probed_dport is not needed, the function can return the struct cxl_dport on success, return errno on failure.
> +
> +static int update_switch_decoder(struct device *dev, void *data)
> +{
> + struct cxl_dport *dport = data;
> + struct cxl_switch_decoder *cxlsd;
> + struct cxl_decoder *cxld;
> + int i;
> +
> + if (!is_switch_decoder(dev))
> + return 0;
> +
> + cxlsd = to_cxl_switch_decoder(dev);
> + cxld = &cxlsd->cxld;
> + guard(rwsem_write)(&cxl_region_rwsem);
> + for (i = 0; i < cxld->interleave_ways; i++) {
> + if (cxlsd->target_map[i] == dport->port_num) {
> + cxlsd->target[i] = dport;
> + return 0;
> + }
> + }
> +
> + dev_dbg(dev, "Updating decoder target_map with %s and none found\n",
> + dev_name(dport->dport_dev));
> +
> + return 0;
> +}
> +
> +static int update_decoders_with_dport(struct cxl_port *port, struct cxl_dport *dport)
> +{
> + device_lock_assert(&port->dev);
> + return device_for_each_child(&port->dev, dport, update_switch_decoder);
> +}
> +
> +int devm_cxl_port_setup_decoders(struct cxl_port *port)
> +{
> + struct cxl_dport *dport;
> + struct cxl_hdm *cxlhdm;
> + unsigned long index;
> + int dports = 0;
> +
> + cxlhdm = devm_cxl_setup_hdm(port, NULL);
> + if (!IS_ERR(cxlhdm))
> + return devm_cxl_enumerate_decoders(cxlhdm, NULL);
> +
> + if (PTR_ERR(cxlhdm) != -ENODEV) {
> + dev_err(&port->dev, "Failed to map HDM decoder capability\n");
> + return PTR_ERR(cxlhdm);
> + }
> +
> + xa_for_each(&port->dports, index, dport)
> + dports++;
> +
> + if (dports == 1) {
> + dev_dbg(&port->dev, "Fallback to passthrough decoder\n");
> + return devm_cxl_add_passthrough_decoder(port);
> + }
> +
> + dev_err(&port->dev, "HDM decoder capability not found\n");
> + return -ENXIO;
> +}
> +EXPORT_SYMBOL_NS_GPL(devm_cxl_port_setup_decoders, "CXL");
> +
> +static int cxl_switch_port_dport_setup(struct cxl_port *port,
> + struct device *dport_dev)
> +{
> + struct cxl_dport *dport;
> + int rc;
> +
> + device_lock_assert(&port->dev);
> +
> + if (!port->dev.driver)
> + return -ENODEV;
> +
> + rc = port_probe_dport(port, dport_dev, &dport);
> + if (rc)
> + return rc;
> +
> + cxl_switch_parse_cdat(port);
> +
> + /* Make sure that no decoders have been allocated before proceeding. */
> + if (ida_is_empty(&port->decoder_ida))
> + rc = devm_cxl_port_setup_decoders(port);
> + else
> + rc = update_decoders_with_dport(port, dport);
> + if (rc)
> + return rc;
> +
> + return 0;
Can return rc directly here, no need to check rc before return 0.
Ming
[snip]
next prev parent reply other threads:[~2025-05-08 4:51 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-07 0:43 [PATCH v2 00/10] cxl: Delay HB port and switch dport probing until endpoint dev probe Dave Jiang
2025-05-07 0:43 ` [PATCH v2 01/10] cxl/region: Add decoder check to check_commit_order() Dave Jiang
2025-05-08 19:54 ` Alison Schofield
2025-05-09 0:55 ` Li Ming
2025-05-13 4:46 ` Gregory Price
2025-05-20 11:14 ` Jonathan Cameron
2025-05-20 16:13 ` Dave Jiang
2025-05-07 0:43 ` [PATCH v2 02/10] cxl: Saperate out CXL dport->id vs actual dport hardware id Dave Jiang
2025-05-08 20:08 ` Alison Schofield
2025-05-15 16:35 ` Dave Jiang
2025-05-09 0:51 ` Li Ming
2025-05-15 16:33 ` Dave Jiang
2025-05-09 9:14 ` Alejandro Lucero Palau
2025-05-15 16:35 ` Dave Jiang
2025-05-13 5:04 ` Gregory Price
2025-05-15 16:38 ` Dave Jiang
2025-05-20 11:19 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 03/10] cxl: Rename find_dport() to provide better function intent Dave Jiang
2025-05-09 0:55 ` Li Ming
2025-05-09 9:20 ` Alejandro Lucero Palau
2025-05-15 17:04 ` Dave Jiang
2025-05-19 16:33 ` Dave Jiang
2025-05-20 11:21 ` Jonathan Cameron
2025-05-13 5:07 ` Gregory Price
2025-05-07 0:43 ` [PATCH v2 04/10] cxl: Remove adding of port_num via devm_cxl_add_dport() Dave Jiang
2025-05-09 0:56 ` Li Ming
2025-05-13 5:13 ` Gregory Price
2025-05-20 11:23 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 05/10] cxl: Defer hardware dport->port_id assignment and registers probing Dave Jiang
2025-05-08 4:50 ` Li Ming [this message]
2025-05-13 15:43 ` Gregory Price
2025-05-15 22:03 ` Dave Jiang
2025-05-20 11:26 ` Jonathan Cameron
2025-05-20 16:33 ` Dave Jiang
2025-05-20 12:27 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 06/10] cxl/test: Add workaround for cxl_test for cxl_core calling mocked functions Dave Jiang
2025-05-20 12:31 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 07/10] cxl: Change sslbis handler to only handle single dport Dave Jiang
2025-05-13 15:48 ` Gregory Price
2025-05-20 12:32 ` Jonathan Cameron
2025-05-20 21:53 ` Dave Jiang
2025-05-07 0:43 ` [PATCH v2 08/10] cxl: Add helper to detect top of CXL device topology Dave Jiang
2025-05-13 15:49 ` Gregory Price
2025-05-13 16:12 ` Dave Jiang
2025-05-15 17:03 ` Gregory Price
2025-05-16 15:47 ` Dave Jiang
2025-05-20 12:34 ` Jonathan Cameron
2025-05-20 21:55 ` Dave Jiang
2025-05-07 0:43 ` [PATCH v2 09/10] cxl: Create an xarray to tie a host bridge to the cxl_root Dave Jiang
2025-05-13 16:01 ` Gregory Price
2025-05-20 12:53 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 10/10] cxl: Move enumeration of hostbridge ports to the memdev probe path Dave Jiang
2025-05-20 13:11 ` Jonathan Cameron
2025-05-20 21:59 ` Dave Jiang
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