From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: Alejandro Lucero Palau <alucerop@amd.com>,
<linux-cxl@vger.kernel.org>,
Dan Williams <dan.j.williams@intel.com>, <dave@stgolabs.net>,
<alison.schofield@intel.com>, <ira.weiny@intel.com>,
<rrichter@amd.com>, <ming.li@zohomail.com>
Subject: Re: [PATCH v2 03/10] cxl: Rename find_dport() to provide better function intent
Date: Tue, 20 May 2025 12:21:41 +0100 [thread overview]
Message-ID: <20250520122141.0000419c@huawei.com> (raw)
In-Reply-To: <431bc155-de69-4e07-82f1-33c654b6d907@intel.com>
On Mon, 19 May 2025 09:33:26 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
> On 5/9/25 2:20 AM, Alejandro Lucero Palau wrote:
> >
> > On 5/7/25 01:43, Dave Jiang wrote:
> >> Rename find_dport() to find_dport_by_num() to indicate that the function
> >> is trying to match a dport by its hardware number index.
> >>
> >> Suggested-by: Dan Williams <dan.j.williams@intel.com>
> >> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> >> ---
> >> drivers/cxl/core/port.c | 12 ++++++------
> >> 1 file changed, 6 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> >> index e9c02e4d0d4c..1d7a4a2ef6ad 100644
> >> --- a/drivers/cxl/core/port.c
> >> +++ b/drivers/cxl/core/port.c
> >> @@ -1045,7 +1045,7 @@ void put_cxl_root(struct cxl_root *cxl_root)
> >> }
> >> EXPORT_SYMBOL_NS_GPL(put_cxl_root, "CXL");
> >> -static struct cxl_dport *find_dport(struct cxl_port *port, int port_num)
> >> +static struct cxl_dport *find_dport_by_num(struct cxl_port *port, int port_num)
> >> {
> >> struct cxl_dport *dport;
> >> unsigned long index;
> >> @@ -1063,7 +1063,7 @@ static int add_dport(struct cxl_port *port, struct cxl_dport *dport)
> >> int rc;
> >> device_lock_assert(&port->dev);
> >> - dup = find_dport(port, dport->port_num);
> >> + dup = find_dport_by_num(port, dport->port_num);
> >> if (dup) {
> >> dev_err(&port->dev,
> >> "unable to add dport%d-%s non-unique port num (%s)\n",
> >> @@ -1275,13 +1275,13 @@ EXPORT_SYMBOL_NS_GPL(devm_cxl_add_dport, "CXL");
> >> * devm_cxl_add_rch_dport - append RCH downstream port data to a cxl_port
> >> * @port: the cxl_port that references this dport
> >> * @dport_dev: firmware or PCI device representing the dport
> >> - * @port_id: identifier for this dport in a decoder's target list
> >> + * @port_num: identifier for this dport in a decoder's target list
> >
> >
> > Not sure this change should be in this patch. It makes more sense to me in the previous one.
> >
> >
> > Also, maybe adding some reference for easily seeing where the identifier comes from:
> >
> > + * @port_num: hardware identifier for this dport in a decoder's target list
>
> In the process of doing that, I realized that this entire comment line gets dropped in a later patch because we remove the port_num parameter. So probably no need to change since it goes away entirely.
>
Even though it's only a comment, if you are changing the name in
the function let's avoid the trivial issue of the kernel-doc
warning that will show up. Make sure those are kept inline.
I'll assume you'll tidy this up one way or another - rest of patch is fine
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> DJ
>
> >
> >
> >> * @rcrb: mandatory location of a Root Complex Register Block
> >> *
> >> * See CXL 3.0 9.11.8 CXL Devices Attached to an RCH
> >> */
> >> struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port,
> >> - struct device *dport_dev, int port_id,
> >> + struct device *dport_dev, int port_num,
> >> resource_size_t rcrb)
> >> {
> >> struct cxl_dport *dport;
> >> @@ -1291,7 +1291,7 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port,
> >> return ERR_PTR(-EINVAL);
> >> }
> >> - dport = __devm_cxl_add_dport(port, dport_dev, port_id,
> >> + dport = __devm_cxl_add_dport(port, dport_dev, port_num,
> >> CXL_RESOURCE_NONE, rcrb);
> >> if (IS_ERR(dport)) {
> >> dev_dbg(dport_dev, "failed to add RCH dport to %s: %ld\n",
> >> @@ -1764,7 +1764,7 @@ static int decoder_populate_targets(struct cxl_switch_decoder *cxlsd,
> >> guard(rwsem_write)(&cxl_region_rwsem);
> >> for (i = 0; i < cxlsd->cxld.interleave_ways; i++) {
> >> - struct cxl_dport *dport = find_dport(port, target_map[i]);
> >> + struct cxl_dport *dport = find_dport_by_num(port, target_map[i]);
> >> if (!dport)
> >> return -ENXIO;
>
>
next prev parent reply other threads:[~2025-05-20 11:21 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-07 0:43 [PATCH v2 00/10] cxl: Delay HB port and switch dport probing until endpoint dev probe Dave Jiang
2025-05-07 0:43 ` [PATCH v2 01/10] cxl/region: Add decoder check to check_commit_order() Dave Jiang
2025-05-08 19:54 ` Alison Schofield
2025-05-09 0:55 ` Li Ming
2025-05-13 4:46 ` Gregory Price
2025-05-20 11:14 ` Jonathan Cameron
2025-05-20 16:13 ` Dave Jiang
2025-05-07 0:43 ` [PATCH v2 02/10] cxl: Saperate out CXL dport->id vs actual dport hardware id Dave Jiang
2025-05-08 20:08 ` Alison Schofield
2025-05-15 16:35 ` Dave Jiang
2025-05-09 0:51 ` Li Ming
2025-05-15 16:33 ` Dave Jiang
2025-05-09 9:14 ` Alejandro Lucero Palau
2025-05-15 16:35 ` Dave Jiang
2025-05-13 5:04 ` Gregory Price
2025-05-15 16:38 ` Dave Jiang
2025-05-20 11:19 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 03/10] cxl: Rename find_dport() to provide better function intent Dave Jiang
2025-05-09 0:55 ` Li Ming
2025-05-09 9:20 ` Alejandro Lucero Palau
2025-05-15 17:04 ` Dave Jiang
2025-05-19 16:33 ` Dave Jiang
2025-05-20 11:21 ` Jonathan Cameron [this message]
2025-05-13 5:07 ` Gregory Price
2025-05-07 0:43 ` [PATCH v2 04/10] cxl: Remove adding of port_num via devm_cxl_add_dport() Dave Jiang
2025-05-09 0:56 ` Li Ming
2025-05-13 5:13 ` Gregory Price
2025-05-20 11:23 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 05/10] cxl: Defer hardware dport->port_id assignment and registers probing Dave Jiang
2025-05-08 4:50 ` Li Ming
2025-05-13 15:43 ` Gregory Price
2025-05-15 22:03 ` Dave Jiang
2025-05-20 11:26 ` Jonathan Cameron
2025-05-20 16:33 ` Dave Jiang
2025-05-20 12:27 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 06/10] cxl/test: Add workaround for cxl_test for cxl_core calling mocked functions Dave Jiang
2025-05-20 12:31 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 07/10] cxl: Change sslbis handler to only handle single dport Dave Jiang
2025-05-13 15:48 ` Gregory Price
2025-05-20 12:32 ` Jonathan Cameron
2025-05-20 21:53 ` Dave Jiang
2025-05-07 0:43 ` [PATCH v2 08/10] cxl: Add helper to detect top of CXL device topology Dave Jiang
2025-05-13 15:49 ` Gregory Price
2025-05-13 16:12 ` Dave Jiang
2025-05-15 17:03 ` Gregory Price
2025-05-16 15:47 ` Dave Jiang
2025-05-20 12:34 ` Jonathan Cameron
2025-05-20 21:55 ` Dave Jiang
2025-05-07 0:43 ` [PATCH v2 09/10] cxl: Create an xarray to tie a host bridge to the cxl_root Dave Jiang
2025-05-13 16:01 ` Gregory Price
2025-05-20 12:53 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 10/10] cxl: Move enumeration of hostbridge ports to the memdev probe path Dave Jiang
2025-05-20 13:11 ` Jonathan Cameron
2025-05-20 21:59 ` Dave Jiang
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