From: Gregory Price <gourry@gourry.net>
To: Dave Jiang <dave.jiang@intel.com>
Cc: linux-cxl@vger.kernel.org,
Dan Williams <dan.j.williams@intel.com>,
dave@stgolabs.net, jonathan.cameron@huawei.com,
alison.schofield@intel.com, ira.weiny@intel.com,
rrichter@amd.com, ming.li@zohomail.com
Subject: Re: [PATCH v2 09/10] cxl: Create an xarray to tie a host bridge to the cxl_root
Date: Tue, 13 May 2025 12:01:03 -0400 [thread overview]
Message-ID: <aCNsvxuftgUlFvoG@gourry-fedora-PF4VCD3F> (raw)
In-Reply-To: <20250507004310.3536991-10-dave.jiang@intel.com>
On Tue, May 06, 2025 at 05:43:09PM -0700, Dave Jiang wrote:
> Add helper functions to setup association of a host bridge device to a
> related cxl_root. Functions are in preparation to support the moving
> of host bridge ports creation from cxl_acpi to cxl_memdev probe path.
>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
mostly wording/naming nits.
I think "udev" is a bad naming choice, but i don't know what to replace
it with. Most of the scenarios below are host-bridge-uport specifical,
so maybe like "hbup" (actually no, hbup is ugly, but you get the point).
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 259b217e812f..a5a673d789f3 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
>
> +/**
> + * cxl_udev_to_root - Retrieve cxl_root tied to the host bridge device
> + * @uport_dev: upstream port device that is the host bridge
"The host bridge's uport device connect to the root" ?
maybe instead of uport_dev, maybe hb_uport_dev? If this interface is
only intended to be used specifically with hb_uport. This is a nit,
ignore it if you want.
> + *
> + * Return cxl_root on success or NULL on failure
> + *
> + * A reference is taken on the port device. Caller needs to call put_device()
> + * when done.
> + */
> +struct cxl_root *cxl_udev_to_root(struct device *uport_dev)
udev_to_root implies you can call this with any uport_dev.
hb_uport_to_root?
Functionality is fine.
> +{
> + struct cxl_root *root;
> +
> + root = xa_load(&cxl_root_ports, (unsigned long)uport_dev);
> + if (!root)
> + return NULL;
> +
> + get_device(&root->port.dev);
> +
> + return root;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_udev_to_root, "CXL");
> +
> +/**
> + * devm_cxl_register_udev_root_port - Tie a hostbridge device to a root port
Similar naming questions as above.
At this point i'm a bit convinced "udev" is not what we want.
> + * @host: device that hosts the memory for the xarray entries
> + * @uport_dev: host bridge device that serves as the xarray index
> + * @root: cxl_root that serves as the xarray entry data
> + *
> + * Return 0 on success or -errno on failure.
> + */
> +int devm_cxl_register_udev_root_port(struct device *host,
> + struct device *uport_dev,
> + struct cxl_root *root)
> +{
> + int rc;
> +
> + rc = xa_insert(&cxl_root_ports, (unsigned long)uport_dev, root,
> + GFP_KERNEL);
> + if (rc)
> + return rc;
> +
> + return devm_add_action_or_reset(host, unregister_udev_root_ports,
> + uport_dev);
> +}
> +EXPORT_SYMBOL_NS_GPL(devm_cxl_register_udev_root_port, "CXL");
> +
> bool dev_is_cxl_root_child(struct device *dev)
> {
> struct cxl_port *port, *parent;
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 22f1a9542077..e0cba91803cc 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -736,6 +736,10 @@ struct pci_bus;
> int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev,
> struct pci_bus *bus);
> struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port);
> +int devm_cxl_register_udev_root_port(struct device *host,
> + struct device *uport_dev,
> + struct cxl_root *root);
> +struct cxl_root *cxl_udev_to_root(struct device *uport_dev);
> struct cxl_port *devm_cxl_add_port(struct device *host,
> struct device *uport_dev,
> resource_size_t component_reg_phys,
> --
> 2.49.0
>
next prev parent reply other threads:[~2025-05-13 16:01 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-07 0:43 [PATCH v2 00/10] cxl: Delay HB port and switch dport probing until endpoint dev probe Dave Jiang
2025-05-07 0:43 ` [PATCH v2 01/10] cxl/region: Add decoder check to check_commit_order() Dave Jiang
2025-05-08 19:54 ` Alison Schofield
2025-05-09 0:55 ` Li Ming
2025-05-13 4:46 ` Gregory Price
2025-05-20 11:14 ` Jonathan Cameron
2025-05-20 16:13 ` Dave Jiang
2025-05-07 0:43 ` [PATCH v2 02/10] cxl: Saperate out CXL dport->id vs actual dport hardware id Dave Jiang
2025-05-08 20:08 ` Alison Schofield
2025-05-15 16:35 ` Dave Jiang
2025-05-09 0:51 ` Li Ming
2025-05-15 16:33 ` Dave Jiang
2025-05-09 9:14 ` Alejandro Lucero Palau
2025-05-15 16:35 ` Dave Jiang
2025-05-13 5:04 ` Gregory Price
2025-05-15 16:38 ` Dave Jiang
2025-05-20 11:19 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 03/10] cxl: Rename find_dport() to provide better function intent Dave Jiang
2025-05-09 0:55 ` Li Ming
2025-05-09 9:20 ` Alejandro Lucero Palau
2025-05-15 17:04 ` Dave Jiang
2025-05-19 16:33 ` Dave Jiang
2025-05-20 11:21 ` Jonathan Cameron
2025-05-13 5:07 ` Gregory Price
2025-05-07 0:43 ` [PATCH v2 04/10] cxl: Remove adding of port_num via devm_cxl_add_dport() Dave Jiang
2025-05-09 0:56 ` Li Ming
2025-05-13 5:13 ` Gregory Price
2025-05-20 11:23 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 05/10] cxl: Defer hardware dport->port_id assignment and registers probing Dave Jiang
2025-05-08 4:50 ` Li Ming
2025-05-13 15:43 ` Gregory Price
2025-05-15 22:03 ` Dave Jiang
2025-05-20 11:26 ` Jonathan Cameron
2025-05-20 16:33 ` Dave Jiang
2025-05-20 12:27 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 06/10] cxl/test: Add workaround for cxl_test for cxl_core calling mocked functions Dave Jiang
2025-05-20 12:31 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 07/10] cxl: Change sslbis handler to only handle single dport Dave Jiang
2025-05-13 15:48 ` Gregory Price
2025-05-20 12:32 ` Jonathan Cameron
2025-05-20 21:53 ` Dave Jiang
2025-05-07 0:43 ` [PATCH v2 08/10] cxl: Add helper to detect top of CXL device topology Dave Jiang
2025-05-13 15:49 ` Gregory Price
2025-05-13 16:12 ` Dave Jiang
2025-05-15 17:03 ` Gregory Price
2025-05-16 15:47 ` Dave Jiang
2025-05-20 12:34 ` Jonathan Cameron
2025-05-20 21:55 ` Dave Jiang
2025-05-07 0:43 ` [PATCH v2 09/10] cxl: Create an xarray to tie a host bridge to the cxl_root Dave Jiang
2025-05-13 16:01 ` Gregory Price [this message]
2025-05-20 12:53 ` Jonathan Cameron
2025-05-07 0:43 ` [PATCH v2 10/10] cxl: Move enumeration of hostbridge ports to the memdev probe path Dave Jiang
2025-05-20 13:11 ` Jonathan Cameron
2025-05-20 21:59 ` Dave Jiang
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