Re: [PATCH 19/34] arm64: dts: qcom: kodiak: Fix PCIe wake GPIO polarity

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Undocumented functional change (adding missing wake-gpios property).
--

commit f9eaa8a25d673bb044fadcfbda30d55434544bbe
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

arm64: dts: qcom: kodiak: Fix PCIe wake GPIO polarity

This commit fixes the PCIe wake-gpios polarity across several boards by
changing the active state from high to low. This is intended to match the
active-low requirement defined in the PCIe Base Specification.

> diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
> index 5bb33a8a98304..509fc4941a029 100644
> --- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
> +++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
[ ... ]
> @@ -579,6 +579,7 @@ &pcie1_phy {
>  
>  &pcie1_port0 {
>  	reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
> +	wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;

[Severity: Medium]
The commit message focuses on changing the polarity of existing wake-gpios
properties, but this addition introduces a brand new wake-gpios property to
pcie1_port0 that was completely missing before.

Is this functional addition intentional? If so, could this be documented in
the commit message so that it accurately reflects all the scope changes
introduced by the patch?

>  };
>  
>  &pmk8350_adc_tm {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260910-root_port-v1-0-90a252ddbbfa@oss.qualcomm.com?part=19