Re: [PATCH 31/34] arm64: dts: qcom: sm8650: Move PCIe phy and GPIOs to root port node

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Removing `phys` and `phy-names` from the Root Complex node breaks backwards compatibility with older kernels.
- [Low] Duplicate `&pcie1_port0` node definition in `sm8650-ayaneo-pocket-s2.dts`.
--

commit 833589d45fdeff1baf13bf57dca340bf7b4c39dc
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

arm64: dts: qcom: sm8650: Move PCIe phy and GPIOs to root port node

This commit moves the PCIe phy references and the perst/wake GPIO properties
from the RC controller node to the root port node. It also renames the
perst-gpios property to reset-gpios.

> diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
> index 668c183bc1777..9fb53fd8c3f5e 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts

[ ... ]

> @@ -1108,15 +1108,17 @@ &pcie0_phy {
>  };
>  
>  &pcie1 {
> -	wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
> -	perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
> -
>  	pinctrl-0 = <&pcie1_default_state>;
>  	pinctrl-names = "default";
>  
>  	status = "okay";
>  };
>  
> +&pcie1_port0 {
> +	reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
> +	wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
> +};
> +
>  &pcie1_port0 {
>  	/* Renesas μPD720201 PCIe USB3.0 HOST CONTROLLER */
>  	usb-controller@0 {

[Severity: Low]
Does this unintentionally duplicate the &pcie1_port0 node definition in
sm8650-ayaneo-pocket-s2.dts?

Since there is already a &pcie1_port0 block directly below it, could these
reset-gpios and wake-gpios properties be placed into that existing block
instead to improve readability?

> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index b679fd8afb7d5..39ecf4686c4b8 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi

[ ... ]

> @@ -3700,9 +3700,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>  			num-lanes = <2>;
>  			bus-range = <0 0xff>;
>  
> -			phys = <&pcie0_phy>;
> -			phy-names = "pciephy";
> -
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>,

[Severity: Medium]
Will removing the phys and phy-names properties from the pcie0 Root Complex
node break backwards compatibility with older kernels?

Older kernels booting with this updated Device Tree might fail to initialize
the PCIe PHY because they only look for these properties in the parent Root
Complex node, which could lead to a complete loss of PCIe functionality.

[ ... ]

> @@ -3893,9 +3892,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>  			num-lanes = <2>;
>  			bus-range = <0 0xff>;
>  
> -			phys = <&pcie1_phy>;
> -			phy-names = "pciephy";
> -
>  			dma-coherent;
>  
>  			#address-cells = <3>;

[Severity: Medium]
Is backward compatibility broken for older kernels on the pcie1 Root Complex
node as well by removing these PHY references?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260910-root_port-v1-0-90a252ddbbfa@oss.qualcomm.com?part=31