Re: [PATCH 23/34] arm64: dts: qcom: sar2130p: Move PCIe phy and GPIOs to root port node

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The commit message falsely claims that the `phy-names` property is moved to the root port nodes, but the implementation entirely deletes it.
--

commit 4afbaa887d3731fc2a6a1eaf2a71527f5f0835ef
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

arm64: dts: qcom: sar2130p: Move PCIe phy and GPIOs to root port node

This commit moves the PCIe phy reference and the perst/wake GPIO properties
from the RC controller node to the root port node (pcie@0). The commit
message indicates that both phys and phy-names are being moved to allow
board-level overrides.

> diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
> index a2d93fd682997..678ecda1c99a3 100644
> --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
> @@ -1337,9 +1337,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>  
>  			power-domains = <&gcc PCIE_0_GDSC>;
>  
> -			phys = <&pcie0_phy>;
> -			phy-names = "pciephy";
> -
>  			status = "disabled";
>  
>  			pcieport0: pcie@0 {
> @@ -1347,6 +1344,8 @@ pcieport0: pcie@0 {
>  				reg = <0x0 0x0 0x0 0x0 0x0>;
>  				bus-range = <0x01 0xff>;
>  
> +				phys = <&pcie0_phy>;
> +

[Severity: Medium]
The commit message states that both phys and phy-names are moved from the
controller to pcieport0. However, only the phys property is added here.
Was phy-names intentionally omitted, or should it be included to match the
commit message?

>  				#address-cells = <3>;
>  				#size-cells = <2>;
>  				ranges;

[ ... ]

> @@ -1464,16 +1463,15 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>  
>  			power-domains = <&gcc PCIE_1_GDSC>;
>  
> -			phys = <&pcie1_phy>;
> -			phy-names = "pciephy";
> -
>  			status = "disabled";
>  
> -			pcie@0 {
> +			pcie1_port0: pcie@0 {
>  				device_type = "pci";
>  				reg = <0x0 0x0 0x0 0x0 0x0>;
>  				bus-range = <0x01 0xff>;
>  
> +				phys = <&pcie1_phy>;
> +

[Severity: Medium]
Similarly for pcie1_port0, the phy-names property was removed from the
controller but not added here. Should phy-names also be added to this node
to remain consistent with the commit description?

>  				#address-cells = <3>;
>  				#size-cells = <2>;
>  				ranges;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260910-root_port-v1-0-90a252ddbbfa@oss.qualcomm.com?part=23