[PATCH 00/23] drm/xe: Add Xe3p support

[PATCH 00/23] drm/xe: Add Xe3p support

[Lucas De Marchi]

This begins the support for the Xe3p arch - it contains generic support
for graphics version 35 and the Xe3p_xpc IP, the Xe3p_LPM IP for media
and support for Nova Lake S (NVL-S), that uses a mix of IPs - the
display side for NVL-S will be submitted separately.

Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
Balasubramani Vivekanandan (4):
      drm/xe/xe3p_lpm: Add special check in Media GT for Main GAMCTRL
      drm/xe/xe3p_lpm: Stop reading the CTC_MODE register
      drm/xe/xe3p_lpm: Skip disabling NOA on unsupported IPs
      drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition

Brian Welty (1):
      drm/xe/xe3p_lpm: Configure MAIN_GAMCTRL_QUEUE_SELECT

Dnyaneshwar Bhadane (1):
      drm/xe/nvls: Attach MOCS table for NVL-S

Fei Yang (1):
      drm/xe/xe3p_xpc: Add L3 bank mask

Harish Chegondi (1):
      drm/xe/xe3p: Add xe3p EU stall data format

Matt Roper (8):
      drm/xe/xe3p_lpm: Handle MCR steering
      drm/xe/xe3p: Stop programming RCU_MODE's fixed slice mode setting
      drm/xe/xe3p: Determine service copy availability from fuse
      drm/xe/nvl: Define NVL-S platform
      drm/xe/nvls: Define GuC firmware for NVL-S
      drm/xe/xe3p_xpc: Add MCR steering
      drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs
      drm/xe/xe3p_xpc: Setup PAT table

S A Muqthyar Ahmed (1):
      drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx

Shekhar Chauhan (2):
      drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05
      drm/xe/xe3p_lpm: Add support for media IP versions 35.00 & 35.03

Tejas Upadhyay (3):
      drm/xe/xe3p: Skip TD flush
      drm/xe/xe3p: Enable L2 flush optimization feature
      drm/xe/xe3p: Flush userptr/shrinker bo cachelines manually

Wang Xin (1):
      drm/xe: Dump CURRENT_LRCA and CSMQDEBUG registers

 drivers/gpu/drm/xe/regs/xe_engine_regs.h |  5 ++
 drivers/gpu/drm/xe/regs/xe_gt_regs.h     | 12 ++++
 drivers/gpu/drm/xe/regs/xe_irq_regs.h    |  1 +
 drivers/gpu/drm/xe/xe_bo.c               |  3 +-
 drivers/gpu/drm/xe/xe_device.c           | 28 ++++++++++
 drivers/gpu/drm/xe/xe_device.h           |  1 +
 drivers/gpu/drm/xe/xe_eu_stall.c         | 23 ++++++++
 drivers/gpu/drm/xe/xe_gt.h               |  6 ++
 drivers/gpu/drm/xe/xe_gt_clock.c         |  4 ++
 drivers/gpu/drm/xe/xe_gt_mcr.c           | 61 ++++++++++++++++++--
 drivers/gpu/drm/xe/xe_gt_topology.c      |  6 +-
 drivers/gpu/drm/xe/xe_gt_types.h         | 15 +++++
 drivers/gpu/drm/xe/xe_guc.c              | 49 ++++++++++++++++
 drivers/gpu/drm/xe/xe_guc.h              |  1 +
 drivers/gpu/drm/xe/xe_guc_ads.c          |  6 +-
 drivers/gpu/drm/xe/xe_guc_capture.c      | 53 +++++++++++++++++-
 drivers/gpu/drm/xe/xe_guc_fwif.h         |  2 +
 drivers/gpu/drm/xe/xe_hw_engine.c        | 50 ++++++++++++++---
 drivers/gpu/drm/xe/xe_irq.c              |  4 ++
 drivers/gpu/drm/xe/xe_mocs.c             |  1 +
 drivers/gpu/drm/xe/xe_oa.c               |  3 +-
 drivers/gpu/drm/xe/xe_pat.c              | 96 +++++++++++++++++++++++++++++++-
 drivers/gpu/drm/xe/xe_pci.c              | 23 ++++++++
 drivers/gpu/drm/xe/xe_platform_types.h   |  1 +
 drivers/gpu/drm/xe/xe_rtp.c              |  6 ++
 drivers/gpu/drm/xe/xe_rtp.h              | 10 ++++
 drivers/gpu/drm/xe/xe_tuning.c           |  9 ++-
 drivers/gpu/drm/xe/xe_uc_fw.c            |  1 +
 drivers/gpu/drm/xe/xe_userptr.c          |  3 +-
 drivers/gpu/drm/xe/xe_wa.c               |  6 +-
 drivers/gpu/drm/xe/xe_wa_oob.rules       |  7 ++-
 include/drm/intel/pciids.h               |  9 +++
 32 files changed, 477 insertions(+), 28 deletions(-)

base-commit: c917f7d11493984be9f381ca0a7667bd3e587ada
change-id: 20251013-xe3p-81bb749e9de0

Lucas De Marchi

[PATCH 01/23] drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05

[Lucas De Marchi]

From: Shekhar Chauhan <shekhar.chauhan@intel.com>

Add graphics IP versions 30.04 & 30.05 and initial workarounds for these
IP versions.

BSpec: 74201
Cc: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c        | 2 ++
 drivers/gpu/drm/xe/xe_wa.c         | 6 +++---
 drivers/gpu/drm/xe/xe_wa_oob.rules | 7 +++++--
 3 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 944c698808ace..c1e89689953b7 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -149,6 +149,8 @@ static const struct xe_ip graphics_ips[] = {
 	{ 3000, "Xe3_LPG", &graphics_xe2 },
 	{ 3001, "Xe3_LPG", &graphics_xe2 },
 	{ 3003, "Xe3_LPG", &graphics_xe2 },
+	{ 3004, "Xe3_LPG", &graphics_xe2 },
+	{ 3005, "Xe3_LPG", &graphics_xe2 },
 };
 
 /* Pre-GMDID Media IPs */
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index c60159a130014..24b6d4bb0b962 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -684,7 +684,7 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 	},
 	{ XE_RTP_NAME("13012615864"),
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), OR,
-		       GRAPHICS_VERSION(3003),
+		       GRAPHICS_VERSION_RANGE(3003, 3005),
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
 	},
@@ -695,7 +695,7 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
 	},
 	{ XE_RTP_NAME("14021402888"),
-	  XE_RTP_RULES(GRAPHICS_VERSION(3003), FUNC(xe_rtp_match_first_render_or_compute)),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3003, 3005), FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
 	},
 	{ XE_RTP_NAME("18041344222"),
@@ -913,7 +913,7 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 			     DIS_AUTOSTRIP))
 	},
 	{ XE_RTP_NAME("22021007897"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3003), ENGINE_CLASS(RENDER)),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
 	},
 };
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index f3a6d5d239cec..9aff2e56fd3e4 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -34,14 +34,17 @@
 13011645652	GRAPHICS_VERSION(2004)
 		GRAPHICS_VERSION_RANGE(3000, 3001)
 		GRAPHICS_VERSION(3003)
+		GRAPHICS_VERSION_RANGE(3004, 3005)
 14022293748	GRAPHICS_VERSION_RANGE(2001, 2002)
 		GRAPHICS_VERSION(2004)
 		GRAPHICS_VERSION_RANGE(3000, 3001)
 		GRAPHICS_VERSION(3003)
+		GRAPHICS_VERSION_RANGE(3004, 3005)
 22019794406	GRAPHICS_VERSION_RANGE(2001, 2002)
 		GRAPHICS_VERSION(2004)
 		GRAPHICS_VERSION_RANGE(3000, 3001)
 		GRAPHICS_VERSION(3003)
+		GRAPHICS_VERSION_RANGE(3004, 3005)
 22019338487	MEDIA_VERSION(2000)
 		GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_not_sriov_vf)
 		MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), FUNC(xe_rtp_match_not_sriov_vf)
@@ -63,11 +66,11 @@
 16023105232	GRAPHICS_VERSION_RANGE(2001, 3001)
 		MEDIA_VERSION_RANGE(1301, 3000)
 		MEDIA_VERSION(3002)
-		GRAPHICS_VERSION(3003)
+		GRAPHICS_VERSION_RANGE(3003, 3005)
 16026508708	GRAPHICS_VERSION_RANGE(1200, 3001)
 		MEDIA_VERSION_RANGE(1300, 3000)
 		MEDIA_VERSION(3002)
-		GRAPHICS_VERSION(3003)
+		GRAPHICS_VERSION_RANGE(3003, 3005)
 14020001231	GRAPHICS_VERSION_RANGE(2001,2004), FUNC(xe_rtp_match_psmi_enabled)
 		MEDIA_VERSION(2000), FUNC(xe_rtp_match_psmi_enabled)
 		MEDIA_VERSION(3000), FUNC(xe_rtp_match_psmi_enabled)

-- 
2.51.0

[PATCH 02/23] drm/xe/xe3p_lpm: Add support for media IP versions 35.00 & 35.03

[Lucas De Marchi]

From: Shekhar Chauhan <shekhar.chauhan@intel.com>

Xe3p_LPM is very similar to Xe3_LPM on the kmd interface, so it can use
the same descriptor structure. Add both 35.00 and 35.03 IP versions.

BSpec: 74201, 74202, 77977
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index c1e89689953b7..8480e53990031 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -164,6 +164,8 @@ static const struct xe_ip media_ips[] = {
 	{ 2000, "Xe2_LPM", &media_xelpmp },
 	{ 3000, "Xe3_LPM", &media_xelpmp },
 	{ 3002, "Xe3_LPM", &media_xelpmp },
+	{ 3500, "Xe3p_LPM", &media_xelpmp },
+	{ 3503, "Xe3p_LPM", &media_xelpmp },
 };
 
 static const struct xe_device_desc tgl_desc = {

-- 
2.51.0

[PATCH 03/23] drm/xe/xe3p_lpm: Configure MAIN_GAMCTRL_QUEUE_SELECT

[Lucas De Marchi]

From: Brian Welty <brian.welty@intel.com>

Starting from Xe3p, there are two different copies of some of the GAM
registers:  the traditional MCR variant at their old locations, and a
new unicast copy known as "main_gamctrl."  The Xe driver doesn't use
these registers directly, but we need to instruct the GuC on which set
it should use.  Since the new, unicast registers are preferred (since
they avoid the need for unnecessary MCR synchronization), set a new GuC
feature flag, GUC_CTL_MAIN_GAMCTRL_QUEUES to convey this decision.  A
new helper function, xe_guc_using_main_gamctrl_queues(), is added for
use in the 3 independent places that need to handle configuration of the
new reporting queues.

The mmio write to enable the main gamctl is only done during the general
GuC upload.  The gamctrl registers are not accessed by the GuC during
hwconfig load.

Last, the ADS blob for communicating the queue addresses contains both a
DPA and GGTT offset. The GuC documentation states that DPA is now MBZ
when using the MAIN_GAMCTRL queues.

Signed-off-by: Brian Welty <brian.welty@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_regs.h |  3 +++
 drivers/gpu/drm/xe/xe_gt.h           |  6 ++++++
 drivers/gpu/drm/xe/xe_guc.c          | 27 +++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_guc.h          |  1 +
 drivers/gpu/drm/xe/xe_guc_ads.c      |  6 +++++-
 drivers/gpu/drm/xe/xe_guc_fwif.h     |  1 +
 6 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 51f2a03847f9d..47e13a3fb9072 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -545,6 +545,9 @@
 #define SARB_CHICKEN1				XE_REG_MCR(0xe90c)
 #define   COMP_CKN_IN				REG_GENMASK(30, 29)
 
+#define MAIN_GAMCTRL_MODE			XE_REG(0xef00)
+#define   MAIN_GAMCTRL_QUEUE_SELECT		REG_BIT(0)
+
 #define RCU_MODE				XE_REG(0x14800, XE_REG_OPTION_MASKED)
 #define   RCU_MODE_FIXED_SLICE_CCS_MODE		REG_BIT(1)
 #define   RCU_MODE_CCS_ENABLE			REG_BIT(0)
diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h
index 5df2ffe3ff838..9d710049da455 100644
--- a/drivers/gpu/drm/xe/xe_gt.h
+++ b/drivers/gpu/drm/xe/xe_gt.h
@@ -22,6 +22,12 @@
 
 #define CCS_MASK(gt) (((gt)->info.engine_mask & XE_HW_ENGINE_CCS_MASK) >> XE_HW_ENGINE_CCS0)
 
+#define GT_VER(gt) ({ \
+	typeof(gt) gt_ = (gt); \
+	struct xe_device *xe = gt_to_xe(gt_); \
+	xe_gt_is_media_type(gt_) ? MEDIA_VER(xe) : GRAPHICS_VER(xe); \
+})
+
 extern struct fault_attr gt_reset_failure;
 static inline bool xe_fault_inject_gt_reset(void)
 {
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index d94490979adc0..37e3735f34e63 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -91,6 +91,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
 	if (xe_configfs_get_psmi_enabled(to_pci_dev(xe->drm.dev)))
 		flags |= GUC_CTL_ENABLE_PSMI_LOGGING;
 
+	if (xe_guc_using_main_gamctrl_queues(guc))
+		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
+
 	return flags;
 }
 
@@ -1255,8 +1258,13 @@ int xe_guc_min_load_for_hwconfig(struct xe_guc *guc)
 
 int xe_guc_upload(struct xe_guc *guc)
 {
+	struct xe_gt *gt = guc_to_gt(guc);
+
 	xe_guc_ads_populate(&guc->ads);
 
+	if (xe_guc_using_main_gamctrl_queues(guc))
+		xe_mmio_write32(&gt->mmio, MAIN_GAMCTRL_MODE, MAIN_GAMCTRL_QUEUE_SELECT);
+
 	return __xe_guc_upload(guc);
 }
 
@@ -1657,6 +1665,25 @@ void xe_guc_declare_wedged(struct xe_guc *guc)
 	xe_guc_submit_wedge(guc);
 }
 
+/**
+ * xe_guc_using_main_gamctrl_queues() - Detect which reporting queues to use.
+ * @guc: The GuC object
+ *
+ * For Xe3p and beyond, we want to program the hardware to use the
+ * "Main GAMCTRL queue" rather than the legacy queue before we upload
+ * the GuC firmware.  This will allow the GuC to use a new set of
+ * registers for pagefault handling and avoid some unnecessary
+ * complications with MCR register range handling.
+ *
+ * Return: true if can use new main gamctrl queues.
+ */
+bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc)
+{
+	struct xe_gt *gt = guc_to_gt(guc);
+
+	return GT_VER(gt) >= 35;
+}
+
 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
 #include "tests/xe_guc_g2g_test.c"
 #endif
diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h
index 1cca05967e621..e2d4c5f44ae34 100644
--- a/drivers/gpu/drm/xe/xe_guc.h
+++ b/drivers/gpu/drm/xe/xe_guc.h
@@ -52,6 +52,7 @@ void xe_guc_stop_prepare(struct xe_guc *guc);
 void xe_guc_stop(struct xe_guc *guc);
 int xe_guc_start(struct xe_guc *guc);
 void xe_guc_declare_wedged(struct xe_guc *guc);
+bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc);
 
 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
 int xe_guc_g2g_test_notification(struct xe_guc *guc, u32 *payload, u32 len);
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 22ac2a8b74c80..bcb85a1bf26d9 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -820,16 +820,20 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
 static void guc_um_init_params(struct xe_guc_ads *ads)
 {
 	u32 um_queue_offset = guc_ads_um_queues_offset(ads);
+	struct xe_guc *guc = ads_to_guc(ads);
 	u64 base_dpa;
 	u32 base_ggtt;
+	bool with_dpa;
 	int i;
 
+	with_dpa = !xe_guc_using_main_gamctrl_queues(guc);
+
 	base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset;
 	base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset;
 
 	for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) {
 		ads_blob_write(ads, um_init_params.queue_params[i].base_dpa,
-			       base_dpa + (i * GUC_UM_QUEUE_SIZE));
+			       with_dpa ? (base_dpa + (i * GUC_UM_QUEUE_SIZE)) : 0);
 		ads_blob_write(ads, um_init_params.queue_params[i].base_ggtt_address,
 			       base_ggtt + (i * GUC_UM_QUEUE_SIZE));
 		ads_blob_write(ads, um_init_params.queue_params[i].size_in_bytes,
diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
index 50c4c2406132e..c90dd266e9cf9 100644
--- a/drivers/gpu/drm/xe/xe_guc_fwif.h
+++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
@@ -113,6 +113,7 @@ struct guc_update_exec_queue_policy {
 #define   GUC_CTL_ENABLE_SLPC		BIT(2)
 #define   GUC_CTL_ENABLE_LITE_RESTORE	BIT(4)
 #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
+#define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
 #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
 
 #define GUC_CTL_DEBUG			3

-- 
2.51.0

[PATCH 04/23] drm/xe/xe3p_lpm: Add special check in Media GT for Main GAMCTRL

[Lucas De Marchi]

From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

For Xe3p arch some subunits of an IP may be different. The GMD_ID
register returns the Xe3p arch and dedicates the reserved field to mark
possible subunit differences. Generally this is an under-the-hood
implementation detail that drivers don't need to worry about, but the
new Main_GAMCTRL may be enabled or not depending on those.

Those reserved bits are described for Xe3p as: "If Zero, No special case
to be handled. If Non-Zero, special case to be handled by Software
agent.". That special case is defined per Arch. So if media version is
35, also check the additional reserved bits. To avoid confusion with the
usual meaning of "reserved", define them as GMD_ID_SUBIP_FLAG_MASK.

Bspec: 74201
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_regs.h |  6 ++++++
 drivers/gpu/drm/xe/xe_guc.c          | 19 +++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 47e13a3fb9072..937dc341abe5e 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -37,6 +37,12 @@
 #define GMD_ID					XE_REG(0xd8c)
 #define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
 #define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
+/*
+ * Spec defines these bits as "Reserved", but then make them assume some
+ * meaning that depends on the ARCH. To avoid any confusion, call them
+ * SUBIP_FLAG_MASK.
+ */
+#define   GMD_ID_SUBIP_FLAG_MASK		REG_GENMASK(13, 6)
 #define   GMD_ID_REVID				REG_GENMASK(5, 0)
 
 #define FORCEWAKE_ACK_GSC			XE_REG(0xdf8)
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 37e3735f34e63..ecc3e091b89e6 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -1681,6 +1681,25 @@ bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc)
 {
 	struct xe_gt *gt = guc_to_gt(guc);
 
+	/*
+	 * For Xe3p media gt (35), the GuC and the CS subunits may be still Xe3
+	 * that lacks the Main GAMCTRL support. Reserved bits from the GMD_ID
+	 * inform the IP version of the subunits.
+	 */
+	if (xe_gt_is_media_type(gt) && MEDIA_VER(gt_to_xe(gt)) == 35) {
+		u32 val = xe_mmio_read32(&gt->mmio, GMD_ID);
+		u32 subip = REG_FIELD_GET(GMD_ID_SUBIP_FLAG_MASK, val);
+
+		if (!subip)
+			return true;
+
+		xe_gt_WARN(gt, subip != 1,
+			   "GMD_ID has unknown value in the SUBIP_FLAG field - 0x%x\n",
+			   subip);
+
+		return false;
+	}
+
 	return GT_VER(gt) >= 35;
 }
 

-- 
2.51.0

[PATCH 05/23] drm/xe/xe3p_lpm: Stop reading the CTC_MODE register

[Lucas De Marchi]

From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

CTC_MODE register is removed by Xe3p.  Stop reading that register on
Xe3p and later platforms.

Bspec: 62395
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_gt_clock.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
index 4f011d1573c65..26052710be8a7 100644
--- a/drivers/gpu/drm/xe/xe_gt_clock.c
+++ b/drivers/gpu/drm/xe/xe_gt_clock.c
@@ -57,6 +57,10 @@ static void read_crystal_clock(struct xe_gt *gt, u32 rpm_config_reg, u32 *freq,
 
 static void check_ctc_mode(struct xe_gt *gt)
 {
+	/* CTC_MODE register is removed by Xe3p */
+	if (GT_VER(gt) >= 35)
+		return;
+
 	/*
 	 * CTC_MODE[0] = 1 is definitely not supported for Xe2 and later
 	 * platforms.  In theory it could be a valid setting for pre-Xe2

-- 
2.51.0

[PATCH 06/23] drm/xe/xe3p_lpm: Skip disabling NOA on unsupported IPs

[Lucas De Marchi]

From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

IP version 35 has removed "NOA Enable Signal" bit from RPM_CONFIG1
register. Skip clearing that bit on unsupported IPs.

Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_oa.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index a4894eb0d7f3f..f901ba52b4032 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -837,7 +837,8 @@ static void xe_oa_disable_metric_set(struct xe_oa_stream *stream)
 		xe_oa_configure_oa_context(stream, false);
 
 	/* Make sure we disable noa to save power. */
-	xe_mmio_rmw32(mmio, RPM_CONFIG1, GT_NOA_ENABLE, 0);
+	if (GT_VER(stream->gt) < 35)
+		xe_mmio_rmw32(mmio, RPM_CONFIG1, GT_NOA_ENABLE, 0);
 
 	sqcnt1 = SQCNT1_PMON_ENABLE |
 		 (HAS_OA_BPC_REPORTING(stream->oa->xe) ? SQCNT1_OABPC : 0);

-- 
2.51.0

[PATCH 07/23] drm/xe/xe3p_lpm: Handle MCR steering

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Xe3p_LPM's MCR steering has the same ranges and behavior as Xe3_LPM.
However one register range that was reserved on Xe3_LPM has now become a
unicast range (0x384200-0x38427F), so we need to stop consolidating the
adjacent MCR ranges into a single table entry in the table.  With this
change to the Xe3_LPM table, we can continue to use the same table for
both IP families.

While we're touching this table, take the opportunity to fix a
whitespace mistake and clarify that one of the other consolidated range
entries includes a reserved range.

Bspec: 76445
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_gt_mcr.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index 8fb1cae917244..e1a2b38fc2a86 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -236,12 +236,13 @@ static const struct xe_mmio_range xe2lpm_instance0_steering_table[] = {
 };
 
 static const struct xe_mmio_range xe3lpm_instance0_steering_table[] = {
-	{ 0x384000, 0x3847DF },         /* GAM, rsvd, GAM */
+	{ 0x384000, 0x3841FF },         /* GAM */
+	{ 0x384400, 0x3847DF },         /* GAM */
 	{ 0x384900, 0x384AFF },         /* GAM */
 	{ 0x389560, 0x3895FF },         /* MEDIAINF */
 	{ 0x38B600, 0x38B8FF },         /* L3BANK */
 	{ 0x38C800, 0x38D07F },         /* GAM, MEDIAINF */
-	{ 0x38D0D0, 0x38F0FF },		/* MEDIAINF, GAM */
+	{ 0x38D0D0, 0x38F0FF },         /* MEDIAINF, rsvd, GAM */
 	{ 0x393C00, 0x393C7F },         /* MEDIAINF */
 	{},
 };

-- 
2.51.0

[PATCH 08/23] drm/xe/xe3p: Stop programming RCU_MODE's fixed slice mode setting

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Since the hardware load balancing is no longer supported, the
programming in RCU_MODE is no longer necessary.

Bspec: 60382
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 1cf623b4a5bcc..5544d91c21e8e 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -349,6 +349,13 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
 static bool xe_hw_engine_match_fixed_cslice_mode(const struct xe_gt *gt,
 						 const struct xe_hw_engine *hwe)
 {
+	/*
+	 * Xe3p no longer supports load balance mode, so "fixed cslice" mode
+	 * is automatic and no RCU_MODE programming is required.
+	 */
+	if (GRAPHICS_VER(gt_to_xe(gt)) >= 35)
+		return false;
+
 	return xe_gt_ccs_mode_enabled(gt) &&
 	       xe_rtp_match_first_render_or_compute(gt, hwe);
 }

-- 
2.51.0

[PATCH 09/23] drm/xe/xe3p: Determine service copy availability from fuse

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Xe3p introduces a dedicated SERVICE_COPY_ENABLE fuse register to reflect
the availability of the service copy engines (BCS1-BCS8).

Bspec: 74624
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_regs.h |  3 +++
 drivers/gpu/drm/xe/xe_hw_engine.c    | 43 ++++++++++++++++++++++++++++--------
 2 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 937dc341abe5e..b73efde21119f 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -245,6 +245,9 @@
 #define XE2_GT_GEOMETRY_DSS_1			XE_REG(0x9150)
 #define XE2_GT_GEOMETRY_DSS_2			XE_REG(0x9154)
 
+#define SERVICE_COPY_ENABLE			XE_REG(0x9170)
+#define   FUSE_SERVICE_COPY_ENABLE_MASK		REG_GENMASK(7, 0)
+
 #define GDRST					XE_REG(0x941c)
 #define   GRDOM_GUC				REG_BIT(3)
 #define   GRDOM_FULL				REG_BIT(0)
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 5544d91c21e8e..275d522d301a3 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -716,27 +716,52 @@ static void read_media_fuses(struct xe_gt *gt)
 	}
 }
 
+static u32 infer_svccopy_from_meml3(struct xe_gt *gt)
+{
+	u32 meml3 = REG_FIELD_GET(MEML3_EN_MASK,
+				  xe_mmio_read32(&gt->mmio, MIRROR_FUSE3));
+	u32 svccopy_mask = 0;
+
+	/*
+	 * Each of the four meml3 bits determines the fusing of two service
+	 * copy engines.
+	 */
+	for (int i = 0; i < 4; i++)
+		svccopy_mask |= (meml3 & BIT(i)) ? 0b11 << 2 * i : 0;
+
+	return svccopy_mask;
+}
+
+static u32 read_svccopy_fuses(struct xe_gt *gt)
+{
+	return REG_FIELD_GET(FUSE_SERVICE_COPY_ENABLE_MASK,
+			     xe_mmio_read32(&gt->mmio, SERVICE_COPY_ENABLE));
+}
+
 static void read_copy_fuses(struct xe_gt *gt)
 {
 	struct xe_device *xe = gt_to_xe(gt);
 	u32 bcs_mask;
 
-	if (GRAPHICS_VERx100(xe) < 1260 || GRAPHICS_VERx100(xe) >= 1270)
-		return;
-
 	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
 
-	bcs_mask = xe_mmio_read32(&gt->mmio, MIRROR_FUSE3);
-	bcs_mask = REG_FIELD_GET(MEML3_EN_MASK, bcs_mask);
+	if (GRAPHICS_VER(xe) >= 35)
+		bcs_mask = read_svccopy_fuses(gt);
+	else if (GRAPHICS_VERx100(xe) == 1260)
+		bcs_mask = infer_svccopy_from_meml3(gt);
+	else
+		return;
 
-	/* BCS0 is always present; only BCS1-BCS8 may be fused off */
-	for (int i = XE_HW_ENGINE_BCS1, j = 0; i <= XE_HW_ENGINE_BCS8; ++i, ++j) {
+	/* Only BCS1-BCS8 may be fused off */
+	bcs_mask <<= XE_HW_ENGINE_BCS1;
+	for (int i = XE_HW_ENGINE_BCS1; i <= XE_HW_ENGINE_BCS8; ++i) {
 		if (!(gt->info.engine_mask & BIT(i)))
 			continue;
 
-		if (!(BIT(j / 2) & bcs_mask)) {
+		if (!(bcs_mask & BIT(i))) {
 			gt->info.engine_mask &= ~BIT(i);
-			xe_gt_info(gt, "bcs%u fused off\n", j);
+			xe_gt_info(gt, "bcs%u fused off\n",
+				   i - XE_HW_ENGINE_BCS0);
 		}
 	}
 }

-- 
2.51.0

[PATCH 10/23] drm/xe/xe3p: Skip TD flush

[Lucas De Marchi]

From: Tejas Upadhyay <tejas.upadhyay@intel.com>

Xe3p has HW ability to do transient display flush so the xe driver can
enable this HW feature by default and skip the software TD flush.

Bspec: 60002
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_device.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 6f8f72fd1b133..7efa8da9e1069 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -1103,6 +1103,14 @@ void xe_device_td_flush(struct xe_device *xe)
 {
 	struct xe_gt *root_gt;
 
+	/*
+	 * From Xe3p onward the HW takes care of flush of TD entries also along
+	 * with flushing XA entries, which will be at the usual sync points,
+	 * like at the end of submission, so no manual flush is needed here.
+	 */
+	if (GRAPHICS_VER(xe) >= 35)
+		return;
+
 	if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20)
 		return;
 

-- 
2.51.0

[PATCH 11/23] drm/xe/xe3p: Enable L2 flush optimization feature

[Lucas De Marchi]

From: Tejas Upadhyay <tejas.upadhyay@intel.com>

When set, the L2 flush optimization feature will control whether L2 is
in Persistent or Transient mode through monitoring of media activity.

To enable L2 flush optimization include new feature flag
GUC_CTL_ENABLE_L2FLUSH_OPT is used when media gt type is detected.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_guc.c      | 3 +++
 drivers/gpu/drm/xe/xe_guc_fwif.h | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index ecc3e091b89e6..3296f28803593 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -94,6 +94,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
 	if (xe_guc_using_main_gamctrl_queues(guc))
 		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
 
+	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) && xe_gt_is_media_type(guc_to_gt(guc)))
+		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
+
 	return flags;
 }
 
diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
index c90dd266e9cf9..c42572306158d 100644
--- a/drivers/gpu/drm/xe/xe_guc_fwif.h
+++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
@@ -115,6 +115,7 @@ struct guc_update_exec_queue_policy {
 #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
 #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
 #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
+#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
 
 #define GUC_CTL_DEBUG			3
 #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)

-- 
2.51.0

[PATCH 12/23] drm/xe/xe3p: Flush userptr/shrinker bo cachelines manually

[Lucas De Marchi]

From: Tejas Upadhyay <tejas.upadhyay@intel.com>

Starting with Xe3p, HW will flush cachelines marked with XA only when
media is off. We have few cases where kernel will have non-XA cachelines
which needs manual flush as we postpone the invalidation.

Flush asap from correctness POV to ensure non accelerated CPU copy to
swap/shmem file will see coherent view of memory, but also from security
POV where later flush can't corrupt the next user of those pages.

Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
[ TODO: xe_device_needs_cache_flush() seems a bad name that doesn't
  really review the context - it may need to be renamed/localized ]
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_bo.c      |  3 ++-
 drivers/gpu/drm/xe/xe_device.c  | 20 ++++++++++++++++++++
 drivers/gpu/drm/xe/xe_device.h  |  1 +
 drivers/gpu/drm/xe/xe_userptr.c |  3 ++-
 4 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index 7b65020818738..05bc61d9e37cf 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -673,7 +673,8 @@ static int xe_bo_trigger_rebind(struct xe_device *xe, struct xe_bo *bo,
 
 		if (!xe_vm_in_fault_mode(vm)) {
 			drm_gpuvm_bo_evict(vm_bo, true);
-			continue;
+			if (!xe_device_needs_cache_flush(xe))
+				continue;
 		}
 
 		if (!idle) {
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 7efa8da9e1069..168a45fe36838 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -1081,6 +1081,26 @@ void xe_device_l2_flush(struct xe_device *xe)
 	xe_force_wake_put(gt_to_fw(gt), fw_ref);
 }
 
+/**
+ * xe_device_needs_cache_flush - Whether the cache needs to be flushed
+ * @xe: The device to check.
+ *
+ * Return: true if the device needs cache flush, false otherwise.
+ */
+bool xe_device_needs_cache_flush(struct xe_device *xe)
+{
+	/*
+	 * Xe3p will flush cachelines marked with XA only when media is off. We
+	 * have few cases where kernel will have non-XA cachelines which needs
+	 * manual flush and this is one of them as we postpone the
+	 * invalidation. Flush asap from correctness POV to ensure non
+	 * accelerated CPU copy to swap/shmem file will see coherent view of
+	 * memory, but also from security POV where later flush can't corrupt
+	 * the next user of those pages.
+	 */
+	return GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe);
+}
+
 /**
  * xe_device_td_flush() - Flush transient L3 cache entries
  * @xe: The device
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index 32cc6323b7f64..15e67db44b56c 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -179,6 +179,7 @@ void xe_device_snapshot_print(struct xe_device *xe, struct drm_printer *p);
 u64 xe_device_canonicalize_addr(struct xe_device *xe, u64 address);
 u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64 address);
 
+bool xe_device_needs_cache_flush(struct xe_device *xe);
 void xe_device_td_flush(struct xe_device *xe);
 void xe_device_l2_flush(struct xe_device *xe);
 
diff --git a/drivers/gpu/drm/xe/xe_userptr.c b/drivers/gpu/drm/xe/xe_userptr.c
index f16e92cd80904..86ce1c3ef41aa 100644
--- a/drivers/gpu/drm/xe/xe_userptr.c
+++ b/drivers/gpu/drm/xe/xe_userptr.c
@@ -112,7 +112,8 @@ static void __vma_userptr_invalidate(struct xe_vm *vm, struct xe_userptr_vma *uv
 				    false, MAX_SCHEDULE_TIMEOUT);
 	XE_WARN_ON(err <= 0);
 
-	if (xe_vm_in_fault_mode(vm) && userptr->initial_bind) {
+	if ((xe_vm_in_fault_mode(vm) || xe_device_needs_cache_flush(vm->xe)) &&
+	    userptr->initial_bind) {
 		err = xe_vm_invalidate_vma(vma);
 		XE_WARN_ON(err);
 	}

-- 
2.51.0

[PATCH 13/23] drm/xe: Dump CURRENT_LRCA and CSMQDEBUG registers

[Lucas De Marchi]

From: Wang Xin <x.wang@intel.com>

Add CURRENT_LRCA and CSMQDEBUG to register dump to help debugging.

Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Wang Xin <x.wang@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_engine_regs.h |  5 +++
 drivers/gpu/drm/xe/xe_guc_capture.c      | 53 +++++++++++++++++++++++++++++++-
 2 files changed, 57 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index f4c3e1187a00a..7b6ec0cf78c85 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -141,6 +141,9 @@
 #define   INHIBIT_SWITCH_UNTIL_PREEMPTED	REG_BIT(31)
 #define   IDLE_DELAY				REG_GENMASK(20, 0)
 
+#define RING_CURRENT_LRCA(base)			XE_REG((base) + 0x240)
+#define   CURRENT_LRCA_VALID			REG_BIT(0)
+
 #define RING_CONTEXT_CONTROL(base)		XE_REG((base) + 0x244, XE_REG_OPTION_MASKED)
 #define	  CTX_CTRL_PXP_ENABLE			REG_BIT(10)
 #define	  CTX_CTRL_OAC_CONTEXT_ENABLE		REG_BIT(8)
@@ -153,6 +156,8 @@
 #define   GFX_DISABLE_LEGACY_MODE		REG_BIT(3)
 #define   GFX_MSIX_INTERRUPT_ENABLE		REG_BIT(13)
 
+#define RING_CSMQDEBUG(base)			XE_REG((base) + 0x2b0)
+
 #define RING_TIMESTAMP(base)			XE_REG((base) + 0x358)
 
 #define RING_TIMESTAMP_UDW(base)		XE_REG((base) + 0x358 + 4)
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
index 243dad3e24185..265aa7b7614ce 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.c
+++ b/drivers/gpu/drm/xe/xe_guc_capture.c
@@ -122,6 +122,7 @@ struct __guc_capture_parsed_output {
 	{ RING_IPEHR(0),		REG_32BIT,	0,	0,	0,	"IPEHR"}, \
 	{ RING_INSTDONE(0),		REG_32BIT,	0,	0,	0,	"RING_INSTDONE"}, \
 	{ INDIRECT_RING_STATE(0),	REG_32BIT,	0,	0,	0,	"INDIRECT_RING_STATE"}, \
+	{ RING_CURRENT_LRCA(0),		REG_32BIT,	0,	0,	0,	"CURRENT_LRCA"}, \
 	{ RING_ACTHD(0),		REG_64BIT_LOW_DW, 0,	0,	0,	NULL}, \
 	{ RING_ACTHD_UDW(0),		REG_64BIT_HI_DW, 0,	0,	0,	"ACTHD"}, \
 	{ RING_BBADDR(0),		REG_64BIT_LOW_DW, 0,	0,	0,	NULL}, \
@@ -149,6 +150,9 @@ struct __guc_capture_parsed_output {
 	{ SFC_DONE(2),			0,	0,	0,	0,	"SFC_DONE[2]"}, \
 	{ SFC_DONE(3),			0,	0,	0,	0,	"SFC_DONE[3]"}
 
+#define XE3P_BASE_ENGINE_INSTANCE \
+	{ RING_CSMQDEBUG(0),		REG_32BIT,	0,	0,	0,	"CSMQDEBUG"}
+
 /* XE_LP Global */
 static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = {
 	COMMON_XELP_BASE_GLOBAL,
@@ -195,6 +199,36 @@ static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = {
 	COMMON_BASE_ENGINE_INSTANCE,
 };
 
+/* Render / Compute Per-Engine-Instance */
+static const struct __guc_mmio_reg_descr xe3p_rc_inst_regs[] = {
+	COMMON_BASE_ENGINE_INSTANCE,
+	XE3P_BASE_ENGINE_INSTANCE,
+};
+
+/* Media Decode/Encode Per-Engine-Instance */
+static const struct __guc_mmio_reg_descr xe3p_vd_inst_regs[] = {
+	COMMON_BASE_ENGINE_INSTANCE,
+	XE3P_BASE_ENGINE_INSTANCE,
+};
+
+/* Video Enhancement Per-Engine-Instance */
+static const struct __guc_mmio_reg_descr xe3p_vec_inst_regs[] = {
+	COMMON_BASE_ENGINE_INSTANCE,
+	XE3P_BASE_ENGINE_INSTANCE,
+};
+
+/* Blitter Per-Engine-Instance */
+static const struct __guc_mmio_reg_descr xe3p_blt_inst_regs[] = {
+	COMMON_BASE_ENGINE_INSTANCE,
+	XE3P_BASE_ENGINE_INSTANCE,
+};
+
+/* XE3P - GSC Per-Engine-Instance */
+static const struct __guc_mmio_reg_descr xe3p_gsc_inst_regs[] = {
+	COMMON_BASE_ENGINE_INSTANCE,
+	XE3P_BASE_ENGINE_INSTANCE,
+};
+
 /*
  * Empty list to prevent warnings about unknown class/instance types
  * as not all class/instance types have entries on all platforms.
@@ -245,6 +279,21 @@ static const struct __guc_mmio_reg_descr_group xe_hpg_lists[] = {
 	{}
 };
 
+ /* List of lists for graphic product version >= 3500 */
+static const struct __guc_mmio_reg_descr_group xe3p_lists[] = {
+	MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0),
+	MAKE_REGLIST(xe_hpg_rc_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
+	MAKE_REGLIST(xe3p_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
+	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO),
+	MAKE_REGLIST(xe3p_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO),
+	MAKE_REGLIST(xe_vec_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
+	MAKE_REGLIST(xe3p_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
+	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER),
+	MAKE_REGLIST(xe3p_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
+	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
+	MAKE_REGLIST(xe3p_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
+	{}
+};
 static const char * const capture_list_type_names[] = {
 	"Global",
 	"Class",
@@ -292,7 +341,9 @@ guc_capture_remove_stale_matches_from_list(struct xe_guc_state_capture *gc,
 static const struct __guc_mmio_reg_descr_group *
 guc_capture_get_device_reglist(struct xe_device *xe)
 {
-	if (GRAPHICS_VERx100(xe) >= 1255)
+	if (GRAPHICS_VERx100(xe) >= 3500)
+		return xe3p_lists;
+	else if (GRAPHICS_VERx100(xe) >= 1255)
 		return xe_hpg_lists;
 	else
 		return xe_lp_lists;

-- 
2.51.0

[PATCH 14/23] drm/xe/nvl: Define NVL-S platform

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Provide the basic platform definitions and PCI IDs for NVL-S.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c            | 9 +++++++++
 drivers/gpu/drm/xe/xe_platform_types.h | 1 +
 include/drm/intel/pciids.h             | 9 +++++++++
 3 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 8480e53990031..aa8359a4c5594 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -354,6 +354,14 @@ static const struct xe_device_desc ptl_desc = {
 	.needs_shared_vf_gt_wq = true,
 };
 
+static const struct xe_device_desc nvls_desc = {
+	PLATFORM(NOVALAKE_S),
+	.dma_mask_size = 46,
+	.has_display = true,
+	.max_gt_per_tile = 2,
+	.require_force_probe = true,
+};
+
 #undef PLATFORM
 __diag_pop();
 
@@ -382,6 +390,7 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
 	INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
 	INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
+	INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
 	{ }
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
index d08574c4cdb8b..f5140a244daf3 100644
--- a/drivers/gpu/drm/xe/xe_platform_types.h
+++ b/drivers/gpu/drm/xe/xe_platform_types.h
@@ -24,6 +24,7 @@ enum xe_platform {
 	XE_LUNARLAKE,
 	XE_BATTLEMAGE,
 	XE_PANTHERLAKE,
+	XE_NOVALAKE_S,
 };
 
 enum xe_subplatform {
diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
index 69d4ae92d822a..00dd007f538ff 100644
--- a/include/drm/intel/pciids.h
+++ b/include/drm/intel/pciids.h
@@ -884,4 +884,13 @@
 	MACRO__(0xFD80, ## __VA_ARGS__), \
 	MACRO__(0xFD81, ## __VA_ARGS__)
 
+/* NVL-S */
+#define INTEL_NVLS_IDS(MACRO__, ...) \
+	MACRO__(0xD740, ## __VA_ARGS__), \
+	MACRO__(0xD741, ## __VA_ARGS__), \
+	MACRO__(0xD742, ## __VA_ARGS__), \
+	MACRO__(0xD743, ## __VA_ARGS__), \
+	MACRO__(0xD744, ## __VA_ARGS__), \
+	MACRO__(0xD745, ## __VA_ARGS__)
+
 #endif /* __PCIIDS_H__ */

-- 
2.51.0

[PATCH 15/23] drm/xe/nvls: Define GuC firmware for NVL-S

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Although NVL-S has a similar Xe3 to PTL/WCL, it requires a unique GuC
firmware.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_uc_fw.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index 6056ecd0b92f5..e589c7e38f125 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -115,6 +115,7 @@ struct fw_blobs_by_type {
 #define XE_GT_TYPE_ANY XE_GT_TYPE_UNINITIALIZED
 
 #define XE_GUC_FIRMWARE_DEFS(fw_def, mmp_ver, major_ver)					\
+	fw_def(NOVALAKE_S,	GT_TYPE_ANY,	mmp_ver(xe,	guc,	nvl,	70, 49, 4))	\
 	fw_def(PANTHERLAKE,	GT_TYPE_ANY,	major_ver(xe,	guc,	ptl,	70, 49, 4))	\
 	fw_def(BATTLEMAGE,	GT_TYPE_ANY,	major_ver(xe,	guc,	bmg,	70, 49, 4))	\
 	fw_def(LUNARLAKE,	GT_TYPE_ANY,	major_ver(xe,	guc,	lnl,	70, 45, 2))	\

-- 
2.51.0

[PATCH 16/23] drm/xe/nvls: Attach MOCS table for NVL-S

[Lucas De Marchi]

From: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>

The MOCS table for NVL-S is the same of Xe2.

Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_mocs.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
index 7b68c22ff7bbc..e8ec4114302e5 100644
--- a/drivers/gpu/drm/xe/xe_mocs.c
+++ b/drivers/gpu/drm/xe/xe_mocs.c
@@ -576,6 +576,7 @@ static unsigned int get_mocs_settings(struct xe_device *xe,
 	memset(info, 0, sizeof(struct xe_mocs_info));
 
 	switch (xe->info.platform) {
+	case XE_NOVALAKE_S:
 	case XE_PANTHERLAKE:
 	case XE_LUNARLAKE:
 	case XE_BATTLEMAGE:

-- 
2.51.0

[PATCH 17/23] drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition

[Lucas De Marchi]

From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Add support for graphics IP Xe3p_XPC having IP version 35.11.

Bspec: 77979, 77975
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index aa8359a4c5594..83e5e0c314a42 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -119,6 +119,15 @@ static const struct xe_graphics_desc graphics_xe2 = {
 	XE2_GFX_FEATURES,
 };
 
+static const struct xe_graphics_desc graphics_xe3p_xpc = {
+	XE2_GFX_FEATURES,
+	.hw_engine_mask =
+		GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) |
+		GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0),
+	.va_bits = 57,
+	.has_flat_ccs = false,
+};
+
 static const struct xe_media_desc media_xem = {
 	.hw_engine_mask =
 		GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
@@ -151,6 +160,7 @@ static const struct xe_ip graphics_ips[] = {
 	{ 3003, "Xe3_LPG", &graphics_xe2 },
 	{ 3004, "Xe3_LPG", &graphics_xe2 },
 	{ 3005, "Xe3_LPG", &graphics_xe2 },
+	{ 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
 };
 
 /* Pre-GMDID Media IPs */

-- 
2.51.0

[PATCH 18/23] drm/xe/xe3p_xpc: Add L3 bank mask

[Lucas De Marchi]

From: Fei Yang <fei.yang@intel.com>

Expose L3 bank mask through topology query interface.

Bspec: 74110
Signed-off-by: Fei Yang <fei.yang@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_gt_topology.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
index 80ef3a6e0a3b5..14af073783ad3 100644
--- a/drivers/gpu/drm/xe/xe_gt_topology.c
+++ b/drivers/gpu/drm/xe/xe_gt_topology.c
@@ -148,7 +148,11 @@ load_l3_bank_mask(struct xe_gt *gt, xe_l3_bank_mask_t l3_bank_mask)
 	if (!xe_gt_topology_report_l3(gt))
 		return;
 
-	if (GRAPHICS_VER(xe) >= 30) {
+	if (GRAPHICS_VERx100(xe) == 3511) {
+		u32 fuse_val = xe_mmio_read32(mmio, MIRROR_L3BANK_ENABLE);
+
+		bitmap_from_arr32(l3_bank_mask, &fuse_val, 32);
+	} else if (GRAPHICS_VER(xe) >= 30) {
 		xe_l3_bank_mask_t per_node = {};
 		u32 meml3_en = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, fuse3);
 		u32 mirror_l3bank_enable = xe_mmio_read32(mmio, MIRROR_L3BANK_ENABLE);

-- 
2.51.0

[PATCH 19/23] drm/xe/xe3p_xpc: Add MCR steering

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Xe3p_XPC's steering has a few changes from Xe3.  Aside from
minor changes to the XeCore (the new name for what used to be "DSS") and
INSTANCE0 tables, different rules apply to different subranges of type
"GAM."  Certain GAM subranges require steering to grp/instance (0,0)
(and thus use the INSTANCE0 table), while others require special
steering to (1,0) instead.  Similarly, there are multiple classes of
"PSMI" steering, with some requiring steering to (0,0) while others
require (19,0).

FIXME: There's an "L3BANK" range listed in the bspec that needs
clarification.

Bspec: 74418
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_gt_mcr.c   | 56 ++++++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/xe/xe_gt_types.h | 15 +++++++++++
 2 files changed, 69 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index e1a2b38fc2a86..e5506ec28e147 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -169,6 +169,15 @@ static const struct xe_mmio_range xelpg_dss_steering_table[] = {
 	{},
 };
 
+static const struct xe_mmio_range xe3p_xpc_xecore_steering_table[] = {
+	{ 0x008140, 0x00817F },         /* SLICE, XeCore, SLICE */
+	{ 0x009480, 0x00955F },         /* SLICE, XeCore */
+	{ 0x00D800, 0x00D87F },		/* SLICE */
+	{ 0x00DC00, 0x00E9FF },         /* SLICE, rsvd, XeCore, rsvd, XeCore, rsvd, XeCore */
+	{ 0x013000, 0x0135FF },         /* XeCore, SLICE */
+	{},
+};
+
 static const struct xe_mmio_range xelpmp_oaddrm_steering_table[] = {
 	{ 0x393200, 0x39323F },
 	{ 0x393400, 0x3934FF },
@@ -247,6 +256,30 @@ static const struct xe_mmio_range xe3lpm_instance0_steering_table[] = {
 	{},
 };
 
+/*
+ * Different "GAM" ranges have different rules; GAMWKRS, STLB, and GAMREQSTRM
+ * range subtypes need to be steered to (1,0), while all other GAM subtypes
+ * are steered to (0,0) and are included in the "INSTANCE0" table farther
+ * down.
+ */
+static const struct xe_mmio_range xe3p_xpc_gam_grp1_steering_table[] = {
+	{ 0x004000, 0x004AFF },		/* GAMREQSTRM, rsvd, STLB, GAMWKRS, GAMREQSTRM */
+	{ 0x00F100, 0x00FFFF },		/* GAMWKRS */
+	{},
+};
+
+static const struct xe_mmio_range xe3p_xpc_psmi_grp19_steering_table[] = {
+	{ 0x00B500, 0x00B5FF },
+	{},
+};
+
+static const struct xe_mmio_range xe3p_xpc_instance0_steering_table[] = {
+	{ 0x00B600, 0x00B6FF },		/* PSMI0 */
+	{ 0x00C800, 0x00CFFF },		/* GAMCTRL */
+	{ 0x00F000, 0x00F0FF },		/* GAMCTRL */
+	{},
+};
+
 static void init_steering_l3bank(struct xe_gt *gt)
 {
 	struct xe_mmio *mmio = &gt->mmio;
@@ -419,6 +452,18 @@ static void init_steering_sqidi_psmi(struct xe_gt *gt)
 	gt->steering[SQIDI_PSMI].instance_target = select & 0x1;
 }
 
+static void init_steering_psmi(struct xe_gt *gt)
+{
+	gt->steering[PSMI19].group_target = 19;
+	gt->steering[PSMI19].instance_target = 0;
+}
+
+static void init_steering_gam1(struct xe_gt *gt)
+{
+	gt->steering[GAM1].group_target = 1;
+	gt->steering[GAM1].instance_target = 0;
+}
+
 static const struct {
 	const char *name;
 	void (*init)(struct xe_gt *gt);
@@ -426,9 +471,11 @@ static const struct {
 	[L3BANK] =	{ "L3BANK",	init_steering_l3bank },
 	[MSLICE] =	{ "MSLICE",	init_steering_mslice },
 	[LNCF] =	{ "LNCF",	NULL }, /* initialized by mslice init */
-	[DSS] =		{ "DSS",	init_steering_dss },
+	[DSS] =		{ "DSS / XeCore", init_steering_dss },
 	[OADDRM] =	{ "OADDRM / GPMXMT", init_steering_oaddrm },
 	[SQIDI_PSMI] =  { "SQIDI_PSMI", init_steering_sqidi_psmi },
+	[PSMI19] =	{ "PSMI[19]",	init_steering_psmi },
+	[GAM1] =	{ "GAMWKRS / STLB / GAMREQSTRM", init_steering_gam1 },
 	[INSTANCE0] =	{ "INSTANCE 0",	NULL },
 	[IMPLICIT_STEERING] = { "IMPLICIT", NULL },
 };
@@ -467,7 +514,12 @@ void xe_gt_mcr_init_early(struct xe_gt *gt)
 			gt->steering[OADDRM].ranges = xelpmp_oaddrm_steering_table;
 		}
 	} else {
-		if (GRAPHICS_VER(xe) >= 20) {
+		if (GRAPHICS_VERx100(xe) == 3511) {
+			gt->steering[DSS].ranges = xe3p_xpc_xecore_steering_table;
+			gt->steering[GAM1].ranges = xe3p_xpc_gam_grp1_steering_table;
+			gt->steering[INSTANCE0].ranges = xe3p_xpc_instance0_steering_table;
+			gt->steering[PSMI19].ranges = xe3p_xpc_psmi_grp19_steering_table;
+		} else if (GRAPHICS_VER(xe) >= 20) {
 			gt->steering[DSS].ranges = xe2lpg_dss_steering_table;
 			gt->steering[SQIDI_PSMI].ranges = xe2lpg_sqidi_psmi_steering_table;
 			gt->steering[INSTANCE0].ranges = xe2lpg_instance0_steering_table;
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index 8b5f604d7883a..d93faa1eedef8 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -72,6 +72,21 @@ enum xe_steering_type {
 	OADDRM,
 	SQIDI_PSMI,
 
+	/*
+	 * The bspec lists multiple ranges as "PSMI," but the different
+	 * ranges with that label have different grpid steering values so we
+	 * treat them independently in code.  Note that the ranges with grpid=0
+	 * are included in the INSTANCE0 group above.
+	 */
+	PSMI19,
+
+	/*
+	 * Although most GAM ranges must be steered to (0,0) and thus use the
+	 * INSTANCE0 type farther down, some platforms have special rules
+	 * for specific subtypes that require steering to (1,0) instead.
+	 */
+	GAM1,
+
 	/*
 	 * On some platforms there are multiple types of MCR registers that
 	 * will always return a non-terminated value at instance (0, 0).  We'll

-- 
2.51.0

[PATCH 20/23] drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx

[Lucas De Marchi]

From: S A Muqthyar Ahmed <syed.abdul.muqthyar.ahmed@intel.com>

Current implementation of compute walker has dependency on GPU/SW Stack
which requires SW/UMD to wait for event from KMD to indicate
PIPE_CONTROL interrup was done. This created latency on SW stack.

This feature adds support to generate completion interrupt from GPGPU
walker which does not support MSIx and avoid software using Pipe control
drain/idle latency.

Suggested-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: S A Muqthyar Ahmed <syed.abdul.muqthyar.ahmed@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
 drivers/gpu/drm/xe/xe_irq.c           | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
index 7c2a3a1401424..9c46b5fb81412 100644
--- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
@@ -82,6 +82,7 @@
 #define   GSC_ER_COMPLETE			REG_BIT(5)
 #define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)
 #define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
+#define   GT_COMPUTE_WALKER_INTERRUPT		REG_BIT(2)
 #define   GT_RENDER_USER_INTERRUPT		REG_BIT(0)
 
 /* irqs for OTHER_KCR_INSTANCE */
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index af519414a4297..e01b158895342 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -150,6 +150,10 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
 	if (xe_device_uc_enabled(xe)) {
 		irqs = GT_RENDER_USER_INTERRUPT |
 			GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
+
+		/* Enable Compute Walker Interrupt for non-MSIX platforms */
+		if (GRAPHICS_VERx100(xe) >= 3511 && !xe_device_has_msix(xe))
+			irqs |= GT_COMPUTE_WALKER_INTERRUPT;
 	} else {
 		irqs = GT_RENDER_USER_INTERRUPT |
 		       GT_CS_MASTER_ERROR_INTERRUPT |

-- 
2.51.0

[PATCH 21/23] drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

The compression overfetch tuning settings only apply to platforms that
support FlatCCS.  In Xe3p_XPC (and any future IPs that also lack
compression) some of the registers being adjusted by this tuning will
not exist or may have been repurposed for something else, so we should
take care not to try to program them.

Note that our xe_rtp_match_has_flatccs() function will also return false
on platforms that do have FlatCCS in the hardware design, but have
compression manually disabled in the BIOS.  On such platforms the
registers still exist (and it would be fine to continue programming
them), but they would have no effect, so skipping that tuning is also
safe.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_rtp.c    |  6 ++++++
 drivers/gpu/drm/xe/xe_rtp.h    | 10 ++++++++++
 drivers/gpu/drm/xe/xe_tuning.c |  9 ++++++---
 3 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
index b5f430d59f805..22a879270c1ec 100644
--- a/drivers/gpu/drm/xe/xe_rtp.c
+++ b/drivers/gpu/drm/xe/xe_rtp.c
@@ -376,3 +376,9 @@ bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,
 {
 	return xe_gt_has_discontiguous_dss_groups(gt);
 }
+
+bool xe_rtp_match_has_flat_ccs(const struct xe_gt *gt,
+			      const struct xe_hw_engine *hwe)
+{
+	return gt_to_xe(gt)->info.has_flat_ccs;
+}
diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
index ac12ddf6cde6d..92f0d16110dd5 100644
--- a/drivers/gpu/drm/xe/xe_rtp.h
+++ b/drivers/gpu/drm/xe/xe_rtp.h
@@ -483,4 +483,14 @@ bool xe_rtp_match_psmi_enabled(const struct xe_gt *gt,
 bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,
 						  const struct xe_hw_engine *hwe);
 
+/**
+ * xe_rtp_match_has_flat_ccs - Match when platform has FlatCCS compression
+ * @gt: GT structure
+ * @hwe: Engine instance
+ *
+ * Returns: true if platform has FlatCCS compression, false otherwise
+ */
+bool xe_rtp_match_has_flat_ccs(const struct xe_gt *gt,
+			       const struct xe_hw_engine *hwe);
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index fd58ea5e78bf6..7c140d8cb1e07 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -40,7 +40,8 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
 				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
 	},
 	{ XE_RTP_NAME("Tuning: Compression Overfetch"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
+		       FUNC(xe_rtp_match_has_flat_ccs)),
 	  XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
 			 SET(CCCHKNREG1, L3CMPCTRL))
 	},
@@ -58,12 +59,14 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
 	  XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3, COMPPWOVERFETCHEN))
 	},
 	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
+		       FUNC(xe_rtp_match_has_flat_ccs)),
 	  XE_RTP_ACTIONS(SET(L3SQCREG2,
 			     COMPMEMRD256BOVRFETCHEN))
 	},
 	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only - media"),
-	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
+	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED),
+		       FUNC(xe_rtp_match_has_flat_ccs)),
 	  XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
 			     COMPMEMRD256BOVRFETCHEN))
 	},

-- 
2.51.0

[PATCH 22/23] drm/xe/xe3p_xpc: Setup PAT table

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

Xe3p_XPC IP requires a new PAT table; note that this table has one fewer
column than the Xe2/Xe3 tables since compression is not supported.
There's also no "WT" entry (which we wouldn't have used on a platform
without display anyway).

Bspec: 71582
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_pat.c | 96 ++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 95 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index 6e48ff84ad0a0..7649b554942aa 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -154,6 +154,41 @@ static const struct xe_pat_table_entry xe2_pat_table[] = {
 static const struct xe_pat_table_entry xe2_pat_ats = XE2_PAT( 0, 0, 0, 0, 3, 3 );
 static const struct xe_pat_table_entry xe2_pat_pta = XE2_PAT( 0, 0, 0, 0, 3, 0 );
 
+/*
+ * Xe3p_XPC PAT table uses the same layout as Xe2/Xe3, except that there's no
+ * option for compression.  Also note that the "L3" and "L4" register fields
+ * actually control L2 and L3 cache respectively on this platform.
+ */
+#define XE3P_XPC_PAT(no_promote, l3clos, l3_policy, l4_policy, __coh_mode) \
+	XE2_PAT(no_promote, 0, l3clos, l3_policy, l4_policy, __coh_mode)
+
+static const struct xe_pat_table_entry xe3p_xpc_pat_ats = XE3P_XPC_PAT( 0, 0, 0, 0, 3 );
+static const struct xe_pat_table_entry xe3p_xpc_pat_pta = XE3P_XPC_PAT( 0, 0, 0, 0, 0 );
+
+static const struct xe_pat_table_entry xe3p_xpc_pat_table[] = {
+	[ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ),
+	[ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ),
+	[ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ),
+	[ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ),
+	[ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ),
+	[ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ),
+	[ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ),
+	[ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ),
+	[ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ),
+	[ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ),
+	[10] = XE3P_XPC_PAT( 0, 0, 0, 3, 3 ),
+	/* 11..22 are reserved; leave set to all 0's */
+	[23] = XE3P_XPC_PAT( 0, 1, 0, 0, 0 ),
+	[24] = XE3P_XPC_PAT( 0, 1, 0, 0, 2 ),
+	[25] = XE3P_XPC_PAT( 0, 1, 0, 0, 3 ),
+	[26] = XE3P_XPC_PAT( 0, 2, 0, 0, 0 ),
+	[27] = XE3P_XPC_PAT( 0, 2, 0, 0, 2 ),
+	[28] = XE3P_XPC_PAT( 0, 2, 0, 0, 3 ),
+	[29] = XE3P_XPC_PAT( 0, 3, 0, 0, 0 ),
+	[30] = XE3P_XPC_PAT( 0, 3, 0, 0, 2 ),
+	[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),
+};
+
 u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index)
 {
 	WARN_ON(pat_index >= xe->pat.n_entries);
@@ -380,9 +415,68 @@ static const struct xe_pat_ops xe2_pat_ops = {
 	.dump = xe2_dump,
 };
 
+static int xe3p_xpc_dump(struct xe_gt *gt, struct drm_printer *p)
+{
+	struct xe_device *xe = gt_to_xe(gt);
+	unsigned int fw_ref;
+	u32 pat;
+	int i;
+
+	fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
+	if (!fw_ref)
+		return -ETIMEDOUT;
+
+	drm_printf(p, "PAT table:\n");
+
+	for (i = 0; i < xe->pat.n_entries; i++) {
+		pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));
+
+		drm_printf(p, "PAT[%2d] = [ %u, %u, %u, %u, %u ]  (%#8x)\n", i,
+			   !!(pat & XE2_NO_PROMOTE),
+			   REG_FIELD_GET(XE2_L3_CLOS, pat),
+			   REG_FIELD_GET(XE2_L3_POLICY, pat),
+			   REG_FIELD_GET(XE2_L4_POLICY, pat),
+			   REG_FIELD_GET(XE2_COH_MODE, pat),
+			   pat);
+	}
+
+	/*
+	 * Also print PTA_MODE, which describes how the hardware accesses
+	 * PPGTT entries.
+	 */
+	pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA));
+
+	drm_printf(p, "Page Table Access:\n");
+	drm_printf(p, "PTA_MODE= [ %u, %u, %u, %u, %u ]  (%#8x)\n",
+		   !!(pat & XE2_NO_PROMOTE),
+		   REG_FIELD_GET(XE2_L3_CLOS, pat),
+		   REG_FIELD_GET(XE2_L3_POLICY, pat),
+		   REG_FIELD_GET(XE2_L4_POLICY, pat),
+		   REG_FIELD_GET(XE2_COH_MODE, pat),
+		   pat);
+
+	xe_force_wake_put(gt_to_fw(gt), fw_ref);
+	return 0;
+}
+
+static const struct xe_pat_ops xe3p_xpc_pat_ops = {
+	.program_graphics = program_pat_mcr,
+	.program_media = program_pat,
+	.dump = xe3p_xpc_dump,
+};
+
 void xe_pat_init_early(struct xe_device *xe)
 {
-	if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
+	if (GRAPHICS_VERx100(xe) == 3511) {
+		xe->pat.ops = &xe3p_xpc_pat_ops;
+		xe->pat.table = xe3p_xpc_pat_table;
+		xe->pat.pat_ats = &xe3p_xpc_pat_ats;
+		xe->pat.pat_pta = &xe3p_xpc_pat_pta;
+		xe->pat.n_entries = ARRAY_SIZE(xe3p_xpc_pat_table);
+		xe->pat.idx[XE_CACHE_NONE] = 3;
+		xe->pat.idx[XE_CACHE_WT] = 3;	/* N/A (no display); use UC */
+		xe->pat.idx[XE_CACHE_WB] = 2;
+	} else if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
 		xe->pat.ops = &xe2_pat_ops;
 		xe->pat.table = xe2_pat_table;
 		xe->pat.pat_ats = &xe2_pat_ats;

-- 
2.51.0

[PATCH 23/23] drm/xe/xe3p: Add xe3p EU stall data format

[Lucas De Marchi]

From: Harish Chegondi <harish.chegondi@intel.com>

Starting with Xe3p, IP address in EU stall data is increases to 61 bits.

Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_eu_stall.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
index f5cfdf29fde34..2bc6b593ff172 100644
--- a/drivers/gpu/drm/xe/xe_eu_stall.c
+++ b/drivers/gpu/drm/xe/xe_eu_stall.c
@@ -124,6 +124,27 @@ struct xe_eu_stall_data_xe2 {
 	__u64 unused[6];
 } __packed;
 
+/*
+ * EU stall data format for Xe3p arch GPUs.
+ */
+struct xe_eu_stall_data_xe3p {
+	__u64 ip_addr:61;	  /* Bits 0  to 60  */
+	__u64 tdr_count:8;	  /* Bits 61 to 68  */
+	__u64 other_count:8;	  /* Bits 69 to 76  */
+	__u64 control_count:8;	  /* Bits 77 to 84  */
+	__u64 pipestall_count:8;  /* Bits 85 to 92  */
+	__u64 send_count:8;	  /* Bits 93 to 100 */
+	__u64 dist_acc_count:8;   /* Bits 101 to 108 */
+	__u64 sbid_count:8;	  /* Bits 109 to 116 */
+	__u64 sync_count:8;	  /* Bits 117 to 124 */
+	__u64 inst_fetch_count:8; /* Bits 125 to 132 */
+	__u64 active_count:8;	  /* Bits 133 to 140 */
+	__u64 ex_id:3;		  /* Bits 141 to 143 */
+	__u64 end_flag:1;	  /* Bit  144 */
+	__u64 unused_bits:47;
+	__u64 unused[5];
+} __packed;
+
 const u64 eu_stall_sampling_rates[] = {251, 251 * 2, 251 * 3, 251 * 4, 251 * 5, 251 * 6, 251 * 7};
 
 /**
@@ -169,6 +190,8 @@ size_t xe_eu_stall_data_record_size(struct xe_device *xe)
 
 	if (xe->info.platform == XE_PVC)
 		record_size = sizeof(struct xe_eu_stall_data_pvc);
+	else if (GRAPHICS_VER(xe) >= 35)
+		record_size = sizeof(struct xe_eu_stall_data_xe3p);
 	else if (GRAPHICS_VER(xe) >= 20)
 		record_size = sizeof(struct xe_eu_stall_data_xe2);
 

-- 
2.51.0

✗ CI.checkpatch: warning for drm/xe: Add Xe3p support

[Patchwork]

== Series Details ==

Series: drm/xe: Add Xe3p support
URL   : https://patchwork.freedesktop.org/series/155866/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
fbd08a78c3a3bb17964db2a326514c69c1dca660
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit fd8bc35abbfa6f3960c9366a516c9b8611cb822c
Author: Harish Chegondi <harish.chegondi@intel.com>
Date:   Mon Oct 13 20:24:55 2025 -0700

    drm/xe/xe3p: Add xe3p EU stall data format
    
    Starting with Xe3p, IP address in EU stall data is increases to 61 bits.
    
    Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
    Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
    Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+ /mt/dim checkpatch c917f7d11493984be9f381ca0a7667bd3e587ada drm-intel
e4dc57b8acaa drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05
-:46: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#46: FILE: drivers/gpu/drm/xe/xe_wa.c:698:
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3003, 3005), FUNC(xe_rtp_match_first_render_or_compute)),

total: 0 errors, 1 warnings, 0 checks, 62 lines checked
28da2adfdb2a drm/xe/xe3p_lpm: Add support for media IP versions 35.00 & 35.03
7c039973bd65 drm/xe/xe3p_lpm: Configure MAIN_GAMCTRL_QUEUE_SELECT
f30f780eeb7b drm/xe/xe3p_lpm: Add special check in Media GT for Main GAMCTRL
075fc1a523e1 drm/xe/xe3p_lpm: Stop reading the CTC_MODE register
53adff75d0eb drm/xe/xe3p_lpm: Skip disabling NOA on unsupported IPs
ad2b7408d4c4 drm/xe/xe3p_lpm: Handle MCR steering
1024935e0655 drm/xe/xe3p: Stop programming RCU_MODE's fixed slice mode setting
8014535b7fb1 drm/xe/xe3p: Determine service copy availability from fuse
3a5ce27e4041 drm/xe/xe3p: Skip TD flush
f81700a35eaf drm/xe/xe3p: Enable L2 flush optimization feature
74d12f42e7e4 drm/xe/xe3p: Flush userptr/shrinker bo cachelines manually
c71b2b3bd222 drm/xe: Dump CURRENT_LRCA and CSMQDEBUG registers
9ca0a0e9cd51 drm/xe/nvl: Define NVL-S platform
-:59: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#59: FILE: include/drm/intel/pciids.h:888:
+#define INTEL_NVLS_IDS(MACRO__, ...) \
+	MACRO__(0xD740, ## __VA_ARGS__), \
+	MACRO__(0xD741, ## __VA_ARGS__), \
+	MACRO__(0xD742, ## __VA_ARGS__), \
+	MACRO__(0xD743, ## __VA_ARGS__), \
+	MACRO__(0xD744, ## __VA_ARGS__), \
+	MACRO__(0xD745, ## __VA_ARGS__)

BUT SEE:

   do {} while (0) advice is over-stated in a few situations:

   The more obvious case is macros, like MODULE_PARM_DESC, invoked at
   file-scope, where C disallows code (it must be in functions).  See
   $exceptions if you have one to add by name.

   More troublesome is declarative macros used at top of new scope,
   like DECLARE_PER_CPU.  These might just compile with a do-while-0
   wrapper, but would be incorrect.  Most of these are handled by
   detecting struct,union,etc declaration primitives in $exceptions.

   Theres also macros called inside an if (block), which "return" an
   expression.  These cannot do-while, and need a ({}) wrapper.

   Enjoy this qualification while we work to improve our heuristics.

-:59: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'MACRO__' - possible side-effects?
#59: FILE: include/drm/intel/pciids.h:888:
+#define INTEL_NVLS_IDS(MACRO__, ...) \
+	MACRO__(0xD740, ## __VA_ARGS__), \
+	MACRO__(0xD741, ## __VA_ARGS__), \
+	MACRO__(0xD742, ## __VA_ARGS__), \
+	MACRO__(0xD743, ## __VA_ARGS__), \
+	MACRO__(0xD744, ## __VA_ARGS__), \
+	MACRO__(0xD745, ## __VA_ARGS__)

total: 1 errors, 0 warnings, 1 checks, 41 lines checked
bdba729d0a2a drm/xe/nvls: Define GuC firmware for NVL-S
29ad48fc7722 drm/xe/nvls: Attach MOCS table for NVL-S
14a24644d423 drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition
7eb51f6706c4 drm/xe/xe3p_xpc: Add L3 bank mask
1fb93893a954 drm/xe/xe3p_xpc: Add MCR steering
a098f6e31d13 drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx
-:8: WARNING:TYPO_SPELLING: 'interrup' may be misspelled - perhaps 'interrupt'?
#8: 
PIPE_CONTROL interrup was done. This created latency on SW stack.
             ^^^^^^^^

total: 0 errors, 1 warnings, 0 checks, 17 lines checked
e19928035d13 drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs
-:33: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#33: FILE: drivers/gpu/drm/xe/xe_rtp.c:381:
+bool xe_rtp_match_has_flat_ccs(const struct xe_gt *gt,
+			      const struct xe_hw_engine *hwe)

total: 0 errors, 0 warnings, 1 checks, 48 lines checked
b5b5435b3ac9 drm/xe/xe3p_xpc: Setup PAT table
-:31: ERROR:SPACING: space prohibited after that open parenthesis '('
#31: FILE: drivers/gpu/drm/xe/xe_pat.c:165:
+static const struct xe_pat_table_entry xe3p_xpc_pat_ats = XE3P_XPC_PAT( 0, 0, 0, 0, 3 );

-:31: ERROR:SPACING: space prohibited before that close parenthesis ')'
#31: FILE: drivers/gpu/drm/xe/xe_pat.c:165:
+static const struct xe_pat_table_entry xe3p_xpc_pat_ats = XE3P_XPC_PAT( 0, 0, 0, 0, 3 );

-:32: ERROR:SPACING: space prohibited after that open parenthesis '('
#32: FILE: drivers/gpu/drm/xe/xe_pat.c:166:
+static const struct xe_pat_table_entry xe3p_xpc_pat_pta = XE3P_XPC_PAT( 0, 0, 0, 0, 0 );

-:32: ERROR:SPACING: space prohibited before that close parenthesis ')'
#32: FILE: drivers/gpu/drm/xe/xe_pat.c:166:
+static const struct xe_pat_table_entry xe3p_xpc_pat_pta = XE3P_XPC_PAT( 0, 0, 0, 0, 0 );

-:35: ERROR:SPACING: space prohibited after that open square bracket '['
#35: FILE: drivers/gpu/drm/xe/xe_pat.c:169:
+	[ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ),

-:35: ERROR:SPACING: space prohibited after that open parenthesis '('
#35: FILE: drivers/gpu/drm/xe/xe_pat.c:169:
+	[ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ),

-:35: ERROR:SPACING: space prohibited before that close parenthesis ')'
#35: FILE: drivers/gpu/drm/xe/xe_pat.c:169:
+	[ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ),

-:36: ERROR:SPACING: space prohibited after that open square bracket '['
#36: FILE: drivers/gpu/drm/xe/xe_pat.c:170:
+	[ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ),

-:36: ERROR:SPACING: space prohibited after that open parenthesis '('
#36: FILE: drivers/gpu/drm/xe/xe_pat.c:170:
+	[ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ),

-:36: ERROR:SPACING: space prohibited before that close parenthesis ')'
#36: FILE: drivers/gpu/drm/xe/xe_pat.c:170:
+	[ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ),

-:37: ERROR:SPACING: space prohibited after that open square bracket '['
#37: FILE: drivers/gpu/drm/xe/xe_pat.c:171:
+	[ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ),

-:37: ERROR:SPACING: space prohibited after that open parenthesis '('
#37: FILE: drivers/gpu/drm/xe/xe_pat.c:171:
+	[ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ),

-:37: ERROR:SPACING: space prohibited before that close parenthesis ')'
#37: FILE: drivers/gpu/drm/xe/xe_pat.c:171:
+	[ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ),

-:38: ERROR:SPACING: space prohibited after that open square bracket '['
#38: FILE: drivers/gpu/drm/xe/xe_pat.c:172:
+	[ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ),

-:38: ERROR:SPACING: space prohibited after that open parenthesis '('
#38: FILE: drivers/gpu/drm/xe/xe_pat.c:172:
+	[ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ),

-:38: ERROR:SPACING: space prohibited before that close parenthesis ')'
#38: FILE: drivers/gpu/drm/xe/xe_pat.c:172:
+	[ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ),

-:39: ERROR:SPACING: space prohibited after that open square bracket '['
#39: FILE: drivers/gpu/drm/xe/xe_pat.c:173:
+	[ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ),

-:39: ERROR:SPACING: space prohibited after that open parenthesis '('
#39: FILE: drivers/gpu/drm/xe/xe_pat.c:173:
+	[ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ),

-:39: ERROR:SPACING: space prohibited before that close parenthesis ')'
#39: FILE: drivers/gpu/drm/xe/xe_pat.c:173:
+	[ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ),

-:40: ERROR:SPACING: space prohibited after that open square bracket '['
#40: FILE: drivers/gpu/drm/xe/xe_pat.c:174:
+	[ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ),

-:40: ERROR:SPACING: space prohibited after that open parenthesis '('
#40: FILE: drivers/gpu/drm/xe/xe_pat.c:174:
+	[ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ),

-:40: ERROR:SPACING: space prohibited before that close parenthesis ')'
#40: FILE: drivers/gpu/drm/xe/xe_pat.c:174:
+	[ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ),

-:41: ERROR:SPACING: space prohibited after that open square bracket '['
#41: FILE: drivers/gpu/drm/xe/xe_pat.c:175:
+	[ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ),

-:41: ERROR:SPACING: space prohibited after that open parenthesis '('
#41: FILE: drivers/gpu/drm/xe/xe_pat.c:175:
+	[ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ),

-:41: ERROR:SPACING: space prohibited before that close parenthesis ')'
#41: FILE: drivers/gpu/drm/xe/xe_pat.c:175:
+	[ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ),

-:42: ERROR:SPACING: space prohibited after that open square bracket '['
#42: FILE: drivers/gpu/drm/xe/xe_pat.c:176:
+	[ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ),

-:42: ERROR:SPACING: space prohibited after that open parenthesis '('
#42: FILE: drivers/gpu/drm/xe/xe_pat.c:176:
+	[ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ),

-:42: ERROR:SPACING: space prohibited before that close parenthesis ')'
#42: FILE: drivers/gpu/drm/xe/xe_pat.c:176:
+	[ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ),

-:43: ERROR:SPACING: space prohibited after that open square bracket '['
#43: FILE: drivers/gpu/drm/xe/xe_pat.c:177:
+	[ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ),

-:43: ERROR:SPACING: space prohibited after that open parenthesis '('
#43: FILE: drivers/gpu/drm/xe/xe_pat.c:177:
+	[ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ),

-:43: ERROR:SPACING: space prohibited before that close parenthesis ')'
#43: FILE: drivers/gpu/drm/xe/xe_pat.c:177:
+	[ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ),

-:44: ERROR:SPACING: space prohibited after that open square bracket '['
#44: FILE: drivers/gpu/drm/xe/xe_pat.c:178:
+	[ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ),

-:44: ERROR:SPACING: space prohibited after that open parenthesis '('
#44: FILE: drivers/gpu/drm/xe/xe_pat.c:178:
+	[ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ),

-:44: ERROR:SPACING: space prohibited before that close parenthesis ')'
#44: FILE: drivers/gpu/drm/xe/xe_pat.c:178:
+	[ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ),

-:45: ERROR:SPACING: space prohibited after that open parenthesis '('
#45: FILE: drivers/gpu/drm/xe/xe_pat.c:179:
+	[10] = XE3P_XPC_PAT( 0, 0, 0, 3, 3 ),

-:45: ERROR:SPACING: space prohibited before that close parenthesis ')'
#45: FILE: drivers/gpu/drm/xe/xe_pat.c:179:
+	[10] = XE3P_XPC_PAT( 0, 0, 0, 3, 3 ),

-:47: ERROR:SPACING: space prohibited after that open parenthesis '('
#47: FILE: drivers/gpu/drm/xe/xe_pat.c:181:
+	[23] = XE3P_XPC_PAT( 0, 1, 0, 0, 0 ),

-:47: ERROR:SPACING: space prohibited before that close parenthesis ')'
#47: FILE: drivers/gpu/drm/xe/xe_pat.c:181:
+	[23] = XE3P_XPC_PAT( 0, 1, 0, 0, 0 ),

-:48: ERROR:SPACING: space prohibited after that open parenthesis '('
#48: FILE: drivers/gpu/drm/xe/xe_pat.c:182:
+	[24] = XE3P_XPC_PAT( 0, 1, 0, 0, 2 ),

-:48: ERROR:SPACING: space prohibited before that close parenthesis ')'
#48: FILE: drivers/gpu/drm/xe/xe_pat.c:182:
+	[24] = XE3P_XPC_PAT( 0, 1, 0, 0, 2 ),

-:49: ERROR:SPACING: space prohibited after that open parenthesis '('
#49: FILE: drivers/gpu/drm/xe/xe_pat.c:183:
+	[25] = XE3P_XPC_PAT( 0, 1, 0, 0, 3 ),

-:49: ERROR:SPACING: space prohibited before that close parenthesis ')'
#49: FILE: drivers/gpu/drm/xe/xe_pat.c:183:
+	[25] = XE3P_XPC_PAT( 0, 1, 0, 0, 3 ),

-:50: ERROR:SPACING: space prohibited after that open parenthesis '('
#50: FILE: drivers/gpu/drm/xe/xe_pat.c:184:
+	[26] = XE3P_XPC_PAT( 0, 2, 0, 0, 0 ),

-:50: ERROR:SPACING: space prohibited before that close parenthesis ')'
#50: FILE: drivers/gpu/drm/xe/xe_pat.c:184:
+	[26] = XE3P_XPC_PAT( 0, 2, 0, 0, 0 ),

-:51: ERROR:SPACING: space prohibited after that open parenthesis '('
#51: FILE: drivers/gpu/drm/xe/xe_pat.c:185:
+	[27] = XE3P_XPC_PAT( 0, 2, 0, 0, 2 ),

-:51: ERROR:SPACING: space prohibited before that close parenthesis ')'
#51: FILE: drivers/gpu/drm/xe/xe_pat.c:185:
+	[27] = XE3P_XPC_PAT( 0, 2, 0, 0, 2 ),

-:52: ERROR:SPACING: space prohibited after that open parenthesis '('
#52: FILE: drivers/gpu/drm/xe/xe_pat.c:186:
+	[28] = XE3P_XPC_PAT( 0, 2, 0, 0, 3 ),

-:52: ERROR:SPACING: space prohibited before that close parenthesis ')'
#52: FILE: drivers/gpu/drm/xe/xe_pat.c:186:
+	[28] = XE3P_XPC_PAT( 0, 2, 0, 0, 3 ),

-:53: ERROR:SPACING: space prohibited after that open parenthesis '('
#53: FILE: drivers/gpu/drm/xe/xe_pat.c:187:
+	[29] = XE3P_XPC_PAT( 0, 3, 0, 0, 0 ),

-:53: ERROR:SPACING: space prohibited before that close parenthesis ')'
#53: FILE: drivers/gpu/drm/xe/xe_pat.c:187:
+	[29] = XE3P_XPC_PAT( 0, 3, 0, 0, 0 ),

-:54: ERROR:SPACING: space prohibited after that open parenthesis '('
#54: FILE: drivers/gpu/drm/xe/xe_pat.c:188:
+	[30] = XE3P_XPC_PAT( 0, 3, 0, 0, 2 ),

-:54: ERROR:SPACING: space prohibited before that close parenthesis ')'
#54: FILE: drivers/gpu/drm/xe/xe_pat.c:188:
+	[30] = XE3P_XPC_PAT( 0, 3, 0, 0, 2 ),

-:55: ERROR:SPACING: space prohibited after that open parenthesis '('
#55: FILE: drivers/gpu/drm/xe/xe_pat.c:189:
+	[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),

-:55: ERROR:SPACING: space prohibited before that close parenthesis ')'
#55: FILE: drivers/gpu/drm/xe/xe_pat.c:189:
+	[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),

total: 54 errors, 0 warnings, 0 checks, 110 lines checked
fd8bc35abbfa drm/xe/xe3p: Add xe3p EU stall data format

✓ CI.KUnit: success for drm/xe: Add Xe3p support

[Patchwork]

== Series Details ==

Series: drm/xe: Add Xe3p support
URL   : https://patchwork.freedesktop.org/series/155866/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[03:45:53] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[03:45:57] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[03:46:28] Starting KUnit Kernel (1/1)...
[03:46:28] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[03:46:28] ================== guc_buf (11 subtests) ===================
[03:46:28] [PASSED] test_smallest
[03:46:28] [PASSED] test_largest
[03:46:28] [PASSED] test_granular
[03:46:28] [PASSED] test_unique
[03:46:28] [PASSED] test_overlap
[03:46:28] [PASSED] test_reusable
[03:46:28] [PASSED] test_too_big
[03:46:28] [PASSED] test_flush
[03:46:28] [PASSED] test_lookup
[03:46:28] [PASSED] test_data
[03:46:28] [PASSED] test_class
[03:46:28] ===================== [PASSED] guc_buf =====================
[03:46:28] =================== guc_dbm (7 subtests) ===================
[03:46:28] [PASSED] test_empty
[03:46:28] [PASSED] test_default
[03:46:28] ======================== test_size  ========================
[03:46:28] [PASSED] 4
[03:46:28] [PASSED] 8
[03:46:28] [PASSED] 32
[03:46:28] [PASSED] 256
[03:46:28] ==================== [PASSED] test_size ====================
[03:46:28] ======================= test_reuse  ========================
[03:46:28] [PASSED] 4
[03:46:28] [PASSED] 8
[03:46:28] [PASSED] 32
[03:46:28] [PASSED] 256
[03:46:28] =================== [PASSED] test_reuse ====================
[03:46:28] =================== test_range_overlap  ====================
[03:46:28] [PASSED] 4
[03:46:28] [PASSED] 8
[03:46:28] [PASSED] 32
[03:46:28] [PASSED] 256
[03:46:28] =============== [PASSED] test_range_overlap ================
[03:46:28] =================== test_range_compact  ====================
[03:46:28] [PASSED] 4
[03:46:28] [PASSED] 8
[03:46:28] [PASSED] 32
[03:46:28] [PASSED] 256
[03:46:28] =============== [PASSED] test_range_compact ================
[03:46:28] ==================== test_range_spare  =====================
[03:46:28] [PASSED] 4
[03:46:28] [PASSED] 8
[03:46:28] [PASSED] 32
[03:46:28] [PASSED] 256
[03:46:28] ================ [PASSED] test_range_spare =================
[03:46:28] ===================== [PASSED] guc_dbm =====================
[03:46:28] =================== guc_idm (6 subtests) ===================
[03:46:28] [PASSED] bad_init
[03:46:28] [PASSED] no_init
[03:46:28] [PASSED] init_fini
[03:46:28] [PASSED] check_used
[03:46:28] [PASSED] check_quota
[03:46:28] [PASSED] check_all
[03:46:28] ===================== [PASSED] guc_idm =====================
[03:46:28] ================== no_relay (3 subtests) ===================
[03:46:28] [PASSED] xe_drops_guc2pf_if_not_ready
[03:46:28] [PASSED] xe_drops_guc2vf_if_not_ready
[03:46:28] [PASSED] xe_rejects_send_if_not_ready
[03:46:28] ==================== [PASSED] no_relay =====================
[03:46:28] ================== pf_relay (14 subtests) ==================
[03:46:28] [PASSED] pf_rejects_guc2pf_too_short
[03:46:28] [PASSED] pf_rejects_guc2pf_too_long
[03:46:28] [PASSED] pf_rejects_guc2pf_no_payload
[03:46:28] [PASSED] pf_fails_no_payload
[03:46:28] [PASSED] pf_fails_bad_origin
[03:46:28] [PASSED] pf_fails_bad_type
[03:46:28] [PASSED] pf_txn_reports_error
[03:46:28] [PASSED] pf_txn_sends_pf2guc
[03:46:28] [PASSED] pf_sends_pf2guc
[03:46:28] [SKIPPED] pf_loopback_nop
[03:46:28] [SKIPPED] pf_loopback_echo
[03:46:28] [SKIPPED] pf_loopback_fail
[03:46:28] [SKIPPED] pf_loopback_busy
[03:46:28] [SKIPPED] pf_loopback_retry
[03:46:28] ==================== [PASSED] pf_relay =====================
[03:46:28] ================== vf_relay (3 subtests) ===================
[03:46:28] [PASSED] vf_rejects_guc2vf_too_short
[03:46:28] [PASSED] vf_rejects_guc2vf_too_long
[03:46:28] [PASSED] vf_rejects_guc2vf_no_payload
[03:46:28] ==================== [PASSED] vf_relay =====================
[03:46:28] ===================== lmtt (1 subtest) =====================
[03:46:28] ======================== test_ops  =========================
[03:46:28] [PASSED] 2-level
[03:46:28] [PASSED] multi-level
[03:46:28] ==================== [PASSED] test_ops =====================
[03:46:28] ====================== [PASSED] lmtt =======================
[03:46:28] ================= pf_service (11 subtests) =================
[03:46:28] [PASSED] pf_negotiate_any
[03:46:28] [PASSED] pf_negotiate_base_match
[03:46:28] [PASSED] pf_negotiate_base_newer
[03:46:28] [PASSED] pf_negotiate_base_next
[03:46:28] [SKIPPED] pf_negotiate_base_older
[03:46:28] [PASSED] pf_negotiate_base_prev
[03:46:28] [PASSED] pf_negotiate_latest_match
[03:46:28] [PASSED] pf_negotiate_latest_newer
[03:46:28] [PASSED] pf_negotiate_latest_next
[03:46:28] [SKIPPED] pf_negotiate_latest_older
[03:46:28] [SKIPPED] pf_negotiate_latest_prev
[03:46:28] =================== [PASSED] pf_service ====================
[03:46:28] ================= xe_guc_g2g (2 subtests) ==================
[03:46:28] ============== xe_live_guc_g2g_kunit_default  ==============
[03:46:28] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[03:46:28] ============== xe_live_guc_g2g_kunit_allmem  ===============
[03:46:28] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[03:46:28] =================== [SKIPPED] xe_guc_g2g ===================
[03:46:28] =================== xe_mocs (2 subtests) ===================
[03:46:28] ================ xe_live_mocs_kernel_kunit  ================
[03:46:28] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[03:46:28] ================ xe_live_mocs_reset_kunit  =================
[03:46:28] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[03:46:28] ==================== [SKIPPED] xe_mocs =====================
[03:46:28] ================= xe_migrate (2 subtests) ==================
[03:46:28] ================= xe_migrate_sanity_kunit  =================
[03:46:28] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[03:46:28] ================== xe_validate_ccs_kunit  ==================
[03:46:28] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[03:46:28] =================== [SKIPPED] xe_migrate ===================
[03:46:28] ================== xe_dma_buf (1 subtest) ==================
[03:46:28] ==================== xe_dma_buf_kunit  =====================
[03:46:28] ================ [SKIPPED] xe_dma_buf_kunit ================
[03:46:28] =================== [SKIPPED] xe_dma_buf ===================
[03:46:28] ================= xe_bo_shrink (1 subtest) =================
[03:46:28] =================== xe_bo_shrink_kunit  ====================
[03:46:28] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[03:46:28] ================== [SKIPPED] xe_bo_shrink ==================
[03:46:28] ==================== xe_bo (2 subtests) ====================
[03:46:28] ================== xe_ccs_migrate_kunit  ===================
[03:46:28] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[03:46:28] ==================== xe_bo_evict_kunit  ====================
[03:46:28] =============== [SKIPPED] xe_bo_evict_kunit ================
[03:46:28] ===================== [SKIPPED] xe_bo ======================
[03:46:28] ==================== args (11 subtests) ====================
[03:46:28] [PASSED] count_args_test
[03:46:28] [PASSED] call_args_example
[03:46:28] [PASSED] call_args_test
[03:46:28] [PASSED] drop_first_arg_example
[03:46:28] [PASSED] drop_first_arg_test
[03:46:28] [PASSED] first_arg_example
[03:46:28] [PASSED] first_arg_test
[03:46:28] [PASSED] last_arg_example
[03:46:28] [PASSED] last_arg_test
[03:46:28] [PASSED] pick_arg_example
[03:46:28] [PASSED] sep_comma_example
[03:46:28] ====================== [PASSED] args =======================
[03:46:28] =================== xe_pci (3 subtests) ====================
[03:46:28] ==================== check_graphics_ip  ====================
[03:46:28] [PASSED] 12.00 Xe_LP
[03:46:28] [PASSED] 12.10 Xe_LP+
[03:46:28] [PASSED] 12.55 Xe_HPG
[03:46:28] [PASSED] 12.60 Xe_HPC
[03:46:28] [PASSED] 12.70 Xe_LPG
[03:46:28] [PASSED] 12.71 Xe_LPG
[03:46:28] [PASSED] 12.74 Xe_LPG+
[03:46:28] [PASSED] 20.01 Xe2_HPG
[03:46:28] [PASSED] 20.02 Xe2_HPG
[03:46:28] [PASSED] 20.04 Xe2_LPG
[03:46:28] [PASSED] 30.00 Xe3_LPG
[03:46:28] [PASSED] 30.01 Xe3_LPG
[03:46:28] [PASSED] 30.03 Xe3_LPG
[03:46:28] [PASSED] 30.04 Xe3_LPG
[03:46:28] [PASSED] 30.05 Xe3_LPG
[03:46:28] [PASSED] 35.11 Xe3p_XPC
[03:46:28] ================ [PASSED] check_graphics_ip ================
[03:46:28] ===================== check_media_ip  ======================
[03:46:28] [PASSED] 12.00 Xe_M
[03:46:28] [PASSED] 12.55 Xe_HPM
[03:46:28] [PASSED] 13.00 Xe_LPM+
[03:46:28] [PASSED] 13.01 Xe2_HPM
[03:46:28] [PASSED] 20.00 Xe2_LPM
[03:46:28] [PASSED] 30.00 Xe3_LPM
[03:46:28] [PASSED] 30.02 Xe3_LPM
[03:46:28] [PASSED] 35.00 Xe3p_LPM
[03:46:28] [PASSED] 35.03 Xe3p_LPM
[03:46:28] ================= [PASSED] check_media_ip ==================
[03:46:28] ================= check_platform_gt_count  =================
[03:46:28] [PASSED] 0x9A60 (TIGERLAKE)
[03:46:28] [PASSED] 0x9A68 (TIGERLAKE)
[03:46:28] [PASSED] 0x9A70 (TIGERLAKE)
[03:46:28] [PASSED] 0x9A40 (TIGERLAKE)
[03:46:28] [PASSED] 0x9A49 (TIGERLAKE)
[03:46:28] [PASSED] 0x9A59 (TIGERLAKE)
[03:46:28] [PASSED] 0x9A78 (TIGERLAKE)
[03:46:28] [PASSED] 0x9AC0 (TIGERLAKE)
[03:46:28] [PASSED] 0x9AC9 (TIGERLAKE)
[03:46:28] [PASSED] 0x9AD9 (TIGERLAKE)
[03:46:28] [PASSED] 0x9AF8 (TIGERLAKE)
[03:46:28] [PASSED] 0x4C80 (ROCKETLAKE)
[03:46:28] [PASSED] 0x4C8A (ROCKETLAKE)
[03:46:28] [PASSED] 0x4C8B (ROCKETLAKE)
[03:46:28] [PASSED] 0x4C8C (ROCKETLAKE)
[03:46:28] [PASSED] 0x4C90 (ROCKETLAKE)
[03:46:28] [PASSED] 0x4C9A (ROCKETLAKE)
[03:46:28] [PASSED] 0x4680 (ALDERLAKE_S)
[03:46:28] [PASSED] 0x4682 (ALDERLAKE_S)
[03:46:28] [PASSED] 0x4688 (ALDERLAKE_S)
[03:46:28] [PASSED] 0x468A (ALDERLAKE_S)
[03:46:28] [PASSED] 0x468B (ALDERLAKE_S)
[03:46:28] [PASSED] 0x4690 (ALDERLAKE_S)
[03:46:28] [PASSED] 0x4692 (ALDERLAKE_S)
[03:46:28] [PASSED] 0x4693 (ALDERLAKE_S)
[03:46:28] [PASSED] 0x46A0 (ALDERLAKE_P)
[03:46:28] [PASSED] 0x46A1 (ALDERLAKE_P)
[03:46:28] [PASSED] 0x46A2 (ALDERLAKE_P)
[03:46:28] [PASSED] 0x46A3 (ALDERLAKE_P)
[03:46:28] [PASSED] 0x46A6 (ALDERLAKE_P)
[03:46:28] [PASSED] 0x46A8 (ALDERLAKE_P)
[03:46:28] [PASSED] 0x46AA (ALDERLAKE_P)
[03:46:28] [PASSED] 0x462A (ALDERLAKE_P)
[03:46:28] [PASSED] 0x4626 (ALDERLAKE_P)
[03:46:28] [PASSED] 0x4628 (ALDERLAKE_P)
[03:46:28] [PASSED] 0x46B0 (ALDERLAKE_P)
[03:46:28] [PASSED] 0x46B1 (ALDERLAKE_P)
[03:46:28] [PASSED] 0x46B2 (ALDERLAKE_P)
[03:46:28] [PASSED] 0x46B3 (ALDERLAKE_P)
[03:46:28] [PASSED] 0x46C0 (ALDERLAKE_P)
[03:46:28] [PASSED] 0x46C1 (ALDERLAKE_P)
[03:46:28] [PASSED] 0x46C2 (ALDERLAKE_P)
[03:46:28] [PASSED] 0x46C3 (ALDERLAKE_P)
[03:46:28] [PASSED] 0x46D0 (ALDERLAKE_N)
[03:46:28] [PASSED] 0x46D1 (ALDERLAKE_N)
[03:46:28] [PASSED] 0x46D2 (ALDERLAKE_N)
[03:46:28] [PASSED] 0x46D3 (ALDERLAKE_N)
[03:46:28] [PASSED] 0x46D4 (ALDERLAKE_N)
[03:46:28] [PASSED] 0xA721 (ALDERLAKE_P)
[03:46:28] [PASSED] 0xA7A1 (ALDERLAKE_P)
[03:46:28] [PASSED] 0xA7A9 (ALDERLAKE_P)
[03:46:28] [PASSED] 0xA7AC (ALDERLAKE_P)
[03:46:28] [PASSED] 0xA7AD (ALDERLAKE_P)
[03:46:28] [PASSED] 0xA720 (ALDERLAKE_P)
[03:46:28] [PASSED] 0xA7A0 (ALDERLAKE_P)
[03:46:28] [PASSED] 0xA7A8 (ALDERLAKE_P)
[03:46:28] [PASSED] 0xA7AA (ALDERLAKE_P)
[03:46:28] [PASSED] 0xA7AB (ALDERLAKE_P)
[03:46:28] [PASSED] 0xA780 (ALDERLAKE_S)
[03:46:28] [PASSED] 0xA781 (ALDERLAKE_S)
[03:46:28] [PASSED] 0xA782 (ALDERLAKE_S)
[03:46:28] [PASSED] 0xA783 (ALDERLAKE_S)
[03:46:28] [PASSED] 0xA788 (ALDERLAKE_S)
[03:46:28] [PASSED] 0xA789 (ALDERLAKE_S)
[03:46:28] [PASSED] 0xA78A (ALDERLAKE_S)
[03:46:28] [PASSED] 0xA78B (ALDERLAKE_S)
[03:46:28] [PASSED] 0x4905 (DG1)
[03:46:28] [PASSED] 0x4906 (DG1)
[03:46:28] [PASSED] 0x4907 (DG1)
[03:46:28] [PASSED] 0x4908 (DG1)
[03:46:28] [PASSED] 0x4909 (DG1)
[03:46:28] [PASSED] 0x56C0 (DG2)
[03:46:28] [PASSED] 0x56C2 (DG2)
[03:46:28] [PASSED] 0x56C1 (DG2)
[03:46:28] [PASSED] 0x7D51 (METEORLAKE)
[03:46:28] [PASSED] 0x7DD1 (METEORLAKE)
[03:46:28] [PASSED] 0x7D41 (METEORLAKE)
[03:46:28] [PASSED] 0x7D67 (METEORLAKE)
[03:46:28] [PASSED] 0xB640 (METEORLAKE)
[03:46:28] [PASSED] 0x56A0 (DG2)
[03:46:28] [PASSED] 0x56A1 (DG2)
[03:46:28] [PASSED] 0x56A2 (DG2)
[03:46:28] [PASSED] 0x56BE (DG2)
[03:46:28] [PASSED] 0x56BF (DG2)
[03:46:28] [PASSED] 0x5690 (DG2)
[03:46:28] [PASSED] 0x5691 (DG2)
[03:46:28] [PASSED] 0x5692 (DG2)
[03:46:28] [PASSED] 0x56A5 (DG2)
[03:46:28] [PASSED] 0x56A6 (DG2)
[03:46:28] [PASSED] 0x56B0 (DG2)
[03:46:28] [PASSED] 0x56B1 (DG2)
[03:46:28] [PASSED] 0x56BA (DG2)
[03:46:28] [PASSED] 0x56BB (DG2)
[03:46:28] [PASSED] 0x56BC (DG2)
[03:46:28] [PASSED] 0x56BD (DG2)
[03:46:28] [PASSED] 0x5693 (DG2)
[03:46:28] [PASSED] 0x5694 (DG2)
[03:46:28] [PASSED] 0x5695 (DG2)
[03:46:28] [PASSED] 0x56A3 (DG2)
[03:46:28] [PASSED] 0x56A4 (DG2)
[03:46:28] [PASSED] 0x56B2 (DG2)
[03:46:28] [PASSED] 0x56B3 (DG2)
[03:46:28] [PASSED] 0x5696 (DG2)
[03:46:28] [PASSED] 0x5697 (DG2)
[03:46:28] [PASSED] 0xB69 (PVC)
[03:46:28] [PASSED] 0xB6E (PVC)
[03:46:28] [PASSED] 0xBD4 (PVC)
[03:46:28] [PASSED] 0xBD5 (PVC)
[03:46:28] [PASSED] 0xBD6 (PVC)
[03:46:28] [PASSED] 0xBD7 (PVC)
[03:46:28] [PASSED] 0xBD8 (PVC)
[03:46:28] [PASSED] 0xBD9 (PVC)
[03:46:28] [PASSED] 0xBDA (PVC)
[03:46:28] [PASSED] 0xBDB (PVC)
[03:46:28] [PASSED] 0xBE0 (PVC)
[03:46:28] [PASSED] 0xBE1 (PVC)
[03:46:28] [PASSED] 0xBE5 (PVC)
[03:46:28] [PASSED] 0x7D40 (METEORLAKE)
[03:46:28] [PASSED] 0x7D45 (METEORLAKE)
[03:46:28] [PASSED] 0x7D55 (METEORLAKE)
[03:46:28] [PASSED] 0x7D60 (METEORLAKE)
[03:46:28] [PASSED] 0x7DD5 (METEORLAKE)
[03:46:28] [PASSED] 0x6420 (LUNARLAKE)
[03:46:28] [PASSED] 0x64A0 (LUNARLAKE)
[03:46:28] [PASSED] 0x64B0 (LUNARLAKE)
[03:46:28] [PASSED] 0xE202 (BATTLEMAGE)
[03:46:28] [PASSED] 0xE209 (BATTLEMAGE)
[03:46:28] [PASSED] 0xE20B (BATTLEMAGE)
[03:46:28] [PASSED] 0xE20C (BATTLEMAGE)
[03:46:28] [PASSED] 0xE20D (BATTLEMAGE)
[03:46:28] [PASSED] 0xE210 (BATTLEMAGE)
[03:46:28] [PASSED] 0xE211 (BATTLEMAGE)
[03:46:28] [PASSED] 0xE212 (BATTLEMAGE)
[03:46:28] [PASSED] 0xE216 (BATTLEMAGE)
[03:46:28] [PASSED] 0xE220 (BATTLEMAGE)
[03:46:28] [PASSED] 0xE221 (BATTLEMAGE)
[03:46:28] [PASSED] 0xE222 (BATTLEMAGE)
[03:46:28] [PASSED] 0xE223 (BATTLEMAGE)
[03:46:28] [PASSED] 0xB080 (PANTHERLAKE)
[03:46:28] [PASSED] 0xB081 (PANTHERLAKE)
[03:46:28] [PASSED] 0xB082 (PANTHERLAKE)
[03:46:28] [PASSED] 0xB083 (PANTHERLAKE)
[03:46:28] [PASSED] 0xB084 (PANTHERLAKE)
[03:46:28] [PASSED] 0xB085 (PANTHERLAKE)
[03:46:28] [PASSED] 0xB086 (PANTHERLAKE)
[03:46:28] [PASSED] 0xB087 (PANTHERLAKE)
[03:46:28] [PASSED] 0xB08F (PANTHERLAKE)
[03:46:28] [PASSED] 0xB090 (PANTHERLAKE)
[03:46:28] [PASSED] 0xB0A0 (PANTHERLAKE)
[03:46:28] [PASSED] 0xB0B0 (PANTHERLAKE)
[03:46:28] [PASSED] 0xFD80 (PANTHERLAKE)
[03:46:28] [PASSED] 0xFD81 (PANTHERLAKE)
[03:46:28] [PASSED] 0xD740 (NOVALAKE_S)
[03:46:28] [PASSED] 0xD741 (NOVALAKE_S)
[03:46:28] [PASSED] 0xD742 (NOVALAKE_S)
[03:46:28] [PASSED] 0xD743 (NOVALAKE_S)
[03:46:28] [PASSED] 0xD744 (NOVALAKE_S)
[03:46:28] [PASSED] 0xD745 (NOVALAKE_S)
[03:46:28] ============= [PASSED] check_platform_gt_count =============
[03:46:28] ===================== [PASSED] xe_pci ======================
[03:46:28] =================== xe_rtp (2 subtests) ====================
[03:46:28] =============== xe_rtp_process_to_sr_tests  ================
[03:46:28] [PASSED] coalesce-same-reg
[03:46:28] [PASSED] no-match-no-add
[03:46:28] [PASSED] match-or
[03:46:28] [PASSED] match-or-xfail
[03:46:28] [PASSED] no-match-no-add-multiple-rules
[03:46:28] [PASSED] two-regs-two-entries
[03:46:28] [PASSED] clr-one-set-other
[03:46:28] [PASSED] set-field
[03:46:28] [PASSED] conflict-duplicate
[03:46:28] [PASSED] conflict-not-disjoint
[03:46:28] [PASSED] conflict-reg-type
[03:46:28] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[03:46:28] ================== xe_rtp_process_tests  ===================
[03:46:28] [PASSED] active1
[03:46:28] [PASSED] active2
[03:46:28] [PASSED] active-inactive
[03:46:28] [PASSED] inactive-active
[03:46:28] [PASSED] inactive-1st_or_active-inactive
[03:46:28] [PASSED] inactive-2nd_or_active-inactive
[03:46:28] [PASSED] inactive-last_or_active-inactive
[03:46:28] [PASSED] inactive-no_or_active-inactive
stty: 'standard input': Inappropriate ioctl for device
[03:46:28] ============== [PASSED] xe_rtp_process_tests ===============
[03:46:28] ===================== [PASSED] xe_rtp ======================
[03:46:28] ==================== xe_wa (1 subtest) =====================
[03:46:28] ======================== xe_wa_gt  =========================
[03:46:28] [PASSED] TIGERLAKE B0
[03:46:28] [PASSED] DG1 A0
[03:46:28] [PASSED] DG1 B0
[03:46:28] [PASSED] ALDERLAKE_S A0
[03:46:28] [PASSED] ALDERLAKE_S B0
[03:46:28] [PASSED] ALDERLAKE_S C0
[03:46:28] [PASSED] ALDERLAKE_S D0
[03:46:28] [PASSED] ALDERLAKE_P A0
[03:46:28] [PASSED] ALDERLAKE_P B0
[03:46:28] [PASSED] ALDERLAKE_P C0
[03:46:28] [PASSED] ALDERLAKE_S RPLS D0
[03:46:28] [PASSED] ALDERLAKE_P RPLU E0
[03:46:28] [PASSED] DG2 G10 C0
[03:46:28] [PASSED] DG2 G11 B1
[03:46:28] [PASSED] DG2 G12 A1
[03:46:28] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[03:46:28] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[03:46:28] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[03:46:28] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[03:46:28] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[03:46:28] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[03:46:28] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[03:46:28] ==================== [PASSED] xe_wa_gt =====================
[03:46:28] ====================== [PASSED] xe_wa ======================
[03:46:28] ============================================================
[03:46:28] Testing complete. Ran 317 tests: passed: 299, skipped: 18
[03:46:28] Elapsed time: 35.114s total, 4.215s configuring, 30.532s building, 0.333s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[03:46:28] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[03:46:30] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[03:46:54] Starting KUnit Kernel (1/1)...
[03:46:54] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[03:46:55] ============ drm_test_pick_cmdline (2 subtests) ============
[03:46:55] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[03:46:55] =============== drm_test_pick_cmdline_named  ===============
[03:46:55] [PASSED] NTSC
[03:46:55] [PASSED] NTSC-J
[03:46:55] [PASSED] PAL
[03:46:55] [PASSED] PAL-M
[03:46:55] =========== [PASSED] drm_test_pick_cmdline_named ===========
[03:46:55] ============== [PASSED] drm_test_pick_cmdline ==============
[03:46:55] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[03:46:55] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[03:46:55] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[03:46:55] =========== drm_validate_clone_mode (2 subtests) ===========
[03:46:55] ============== drm_test_check_in_clone_mode  ===============
[03:46:55] [PASSED] in_clone_mode
[03:46:55] [PASSED] not_in_clone_mode
[03:46:55] ========== [PASSED] drm_test_check_in_clone_mode ===========
[03:46:55] =============== drm_test_check_valid_clones  ===============
[03:46:55] [PASSED] not_in_clone_mode
[03:46:55] [PASSED] valid_clone
[03:46:55] [PASSED] invalid_clone
[03:46:55] =========== [PASSED] drm_test_check_valid_clones ===========
[03:46:55] ============= [PASSED] drm_validate_clone_mode =============
[03:46:55] ============= drm_validate_modeset (1 subtest) =============
[03:46:55] [PASSED] drm_test_check_connector_changed_modeset
[03:46:55] ============== [PASSED] drm_validate_modeset ===============
[03:46:55] ====== drm_test_bridge_get_current_state (2 subtests) ======
[03:46:55] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[03:46:55] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[03:46:55] ======== [PASSED] drm_test_bridge_get_current_state ========
[03:46:55] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[03:46:55] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[03:46:55] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[03:46:55] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[03:46:55] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[03:46:55] ============== drm_bridge_alloc (2 subtests) ===============
[03:46:55] [PASSED] drm_test_drm_bridge_alloc_basic
[03:46:55] [PASSED] drm_test_drm_bridge_alloc_get_put
[03:46:55] ================ [PASSED] drm_bridge_alloc =================
[03:46:55] ================== drm_buddy (8 subtests) ==================
[03:46:55] [PASSED] drm_test_buddy_alloc_limit
[03:46:55] [PASSED] drm_test_buddy_alloc_optimistic
[03:46:55] [PASSED] drm_test_buddy_alloc_pessimistic
[03:46:55] [PASSED] drm_test_buddy_alloc_pathological
[03:46:55] [PASSED] drm_test_buddy_alloc_contiguous
[03:46:55] [PASSED] drm_test_buddy_alloc_clear
[03:46:55] [PASSED] drm_test_buddy_alloc_range_bias
[03:46:55] [PASSED] drm_test_buddy_fragmentation_performance
[03:46:55] ==================== [PASSED] drm_buddy ====================
[03:46:55] ============= drm_cmdline_parser (40 subtests) =============
[03:46:55] [PASSED] drm_test_cmdline_force_d_only
[03:46:55] [PASSED] drm_test_cmdline_force_D_only_dvi
[03:46:55] [PASSED] drm_test_cmdline_force_D_only_hdmi
[03:46:55] [PASSED] drm_test_cmdline_force_D_only_not_digital
[03:46:55] [PASSED] drm_test_cmdline_force_e_only
[03:46:55] [PASSED] drm_test_cmdline_res
[03:46:55] [PASSED] drm_test_cmdline_res_vesa
[03:46:55] [PASSED] drm_test_cmdline_res_vesa_rblank
[03:46:55] [PASSED] drm_test_cmdline_res_rblank
[03:46:55] [PASSED] drm_test_cmdline_res_bpp
[03:46:55] [PASSED] drm_test_cmdline_res_refresh
[03:46:55] [PASSED] drm_test_cmdline_res_bpp_refresh
[03:46:55] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[03:46:55] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[03:46:55] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[03:46:55] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[03:46:55] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[03:46:55] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[03:46:55] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[03:46:55] [PASSED] drm_test_cmdline_res_margins_force_on
[03:46:55] [PASSED] drm_test_cmdline_res_vesa_margins
[03:46:55] [PASSED] drm_test_cmdline_name
[03:46:55] [PASSED] drm_test_cmdline_name_bpp
[03:46:55] [PASSED] drm_test_cmdline_name_option
[03:46:55] [PASSED] drm_test_cmdline_name_bpp_option
[03:46:55] [PASSED] drm_test_cmdline_rotate_0
[03:46:55] [PASSED] drm_test_cmdline_rotate_90
[03:46:55] [PASSED] drm_test_cmdline_rotate_180
[03:46:55] [PASSED] drm_test_cmdline_rotate_270
[03:46:55] [PASSED] drm_test_cmdline_hmirror
[03:46:55] [PASSED] drm_test_cmdline_vmirror
[03:46:55] [PASSED] drm_test_cmdline_margin_options
[03:46:55] [PASSED] drm_test_cmdline_multiple_options
[03:46:55] [PASSED] drm_test_cmdline_bpp_extra_and_option
[03:46:55] [PASSED] drm_test_cmdline_extra_and_option
[03:46:55] [PASSED] drm_test_cmdline_freestanding_options
[03:46:55] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[03:46:55] [PASSED] drm_test_cmdline_panel_orientation
[03:46:55] ================ drm_test_cmdline_invalid  =================
[03:46:55] [PASSED] margin_only
[03:46:55] [PASSED] interlace_only
[03:46:55] [PASSED] res_missing_x
[03:46:55] [PASSED] res_missing_y
[03:46:55] [PASSED] res_bad_y
[03:46:55] [PASSED] res_missing_y_bpp
[03:46:55] [PASSED] res_bad_bpp
[03:46:55] [PASSED] res_bad_refresh
[03:46:55] [PASSED] res_bpp_refresh_force_on_off
[03:46:55] [PASSED] res_invalid_mode
[03:46:55] [PASSED] res_bpp_wrong_place_mode
[03:46:55] [PASSED] name_bpp_refresh
[03:46:55] [PASSED] name_refresh
[03:46:55] [PASSED] name_refresh_wrong_mode
[03:46:55] [PASSED] name_refresh_invalid_mode
[03:46:55] [PASSED] rotate_multiple
[03:46:55] [PASSED] rotate_invalid_val
[03:46:55] [PASSED] rotate_truncated
[03:46:55] [PASSED] invalid_option
[03:46:55] [PASSED] invalid_tv_option
[03:46:55] [PASSED] truncated_tv_option
[03:46:55] ============ [PASSED] drm_test_cmdline_invalid =============
[03:46:55] =============== drm_test_cmdline_tv_options  ===============
[03:46:55] [PASSED] NTSC
[03:46:55] [PASSED] NTSC_443
[03:46:55] [PASSED] NTSC_J
[03:46:55] [PASSED] PAL
[03:46:55] [PASSED] PAL_M
[03:46:55] [PASSED] PAL_N
[03:46:55] [PASSED] SECAM
[03:46:55] [PASSED] MONO_525
[03:46:55] [PASSED] MONO_625
[03:46:55] =========== [PASSED] drm_test_cmdline_tv_options ===========
[03:46:55] =============== [PASSED] drm_cmdline_parser ================
[03:46:55] ========== drmm_connector_hdmi_init (20 subtests) ==========
[03:46:55] [PASSED] drm_test_connector_hdmi_init_valid
[03:46:55] [PASSED] drm_test_connector_hdmi_init_bpc_8
[03:46:55] [PASSED] drm_test_connector_hdmi_init_bpc_10
[03:46:55] [PASSED] drm_test_connector_hdmi_init_bpc_12
[03:46:55] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[03:46:55] [PASSED] drm_test_connector_hdmi_init_bpc_null
[03:46:55] [PASSED] drm_test_connector_hdmi_init_formats_empty
[03:46:55] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[03:46:55] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[03:46:55] [PASSED] supported_formats=0x9 yuv420_allowed=1
[03:46:55] [PASSED] supported_formats=0x9 yuv420_allowed=0
[03:46:55] [PASSED] supported_formats=0x3 yuv420_allowed=1
[03:46:55] [PASSED] supported_formats=0x3 yuv420_allowed=0
[03:46:55] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[03:46:55] [PASSED] drm_test_connector_hdmi_init_null_ddc
[03:46:55] [PASSED] drm_test_connector_hdmi_init_null_product
[03:46:55] [PASSED] drm_test_connector_hdmi_init_null_vendor
[03:46:55] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[03:46:55] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[03:46:55] [PASSED] drm_test_connector_hdmi_init_product_valid
[03:46:55] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[03:46:55] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[03:46:55] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[03:46:55] ========= drm_test_connector_hdmi_init_type_valid  =========
[03:46:55] [PASSED] HDMI-A
[03:46:55] [PASSED] HDMI-B
[03:46:55] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[03:46:55] ======== drm_test_connector_hdmi_init_type_invalid  ========
[03:46:55] [PASSED] Unknown
[03:46:55] [PASSED] VGA
[03:46:55] [PASSED] DVI-I
[03:46:55] [PASSED] DVI-D
[03:46:55] [PASSED] DVI-A
[03:46:55] [PASSED] Composite
[03:46:55] [PASSED] SVIDEO
[03:46:55] [PASSED] LVDS
[03:46:55] [PASSED] Component
[03:46:55] [PASSED] DIN
[03:46:55] [PASSED] DP
[03:46:55] [PASSED] TV
[03:46:55] [PASSED] eDP
[03:46:55] [PASSED] Virtual
[03:46:55] [PASSED] DSI
[03:46:55] [PASSED] DPI
[03:46:55] [PASSED] Writeback
[03:46:55] [PASSED] SPI
[03:46:55] [PASSED] USB
[03:46:55] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[03:46:55] ============ [PASSED] drmm_connector_hdmi_init =============
[03:46:55] ============= drmm_connector_init (3 subtests) =============
[03:46:55] [PASSED] drm_test_drmm_connector_init
[03:46:55] [PASSED] drm_test_drmm_connector_init_null_ddc
[03:46:55] ========= drm_test_drmm_connector_init_type_valid  =========
[03:46:55] [PASSED] Unknown
[03:46:55] [PASSED] VGA
[03:46:55] [PASSED] DVI-I
[03:46:55] [PASSED] DVI-D
[03:46:55] [PASSED] DVI-A
[03:46:55] [PASSED] Composite
[03:46:55] [PASSED] SVIDEO
[03:46:55] [PASSED] LVDS
[03:46:55] [PASSED] Component
[03:46:55] [PASSED] DIN
[03:46:55] [PASSED] DP
[03:46:55] [PASSED] HDMI-A
[03:46:55] [PASSED] HDMI-B
[03:46:55] [PASSED] TV
[03:46:55] [PASSED] eDP
[03:46:55] [PASSED] Virtual
[03:46:55] [PASSED] DSI
[03:46:55] [PASSED] DPI
[03:46:55] [PASSED] Writeback
[03:46:55] [PASSED] SPI
[03:46:55] [PASSED] USB
[03:46:55] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[03:46:55] =============== [PASSED] drmm_connector_init ===============
[03:46:55] ========= drm_connector_dynamic_init (6 subtests) ==========
[03:46:55] [PASSED] drm_test_drm_connector_dynamic_init
[03:46:55] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[03:46:55] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[03:46:55] [PASSED] drm_test_drm_connector_dynamic_init_properties
[03:46:55] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[03:46:55] [PASSED] Unknown
[03:46:55] [PASSED] VGA
[03:46:55] [PASSED] DVI-I
[03:46:55] [PASSED] DVI-D
[03:46:55] [PASSED] DVI-A
[03:46:55] [PASSED] Composite
[03:46:55] [PASSED] SVIDEO
[03:46:55] [PASSED] LVDS
[03:46:55] [PASSED] Component
[03:46:55] [PASSED] DIN
[03:46:55] [PASSED] DP
[03:46:55] [PASSED] HDMI-A
[03:46:55] [PASSED] HDMI-B
[03:46:55] [PASSED] TV
[03:46:55] [PASSED] eDP
[03:46:55] [PASSED] Virtual
[03:46:55] [PASSED] DSI
[03:46:55] [PASSED] DPI
[03:46:55] [PASSED] Writeback
[03:46:55] [PASSED] SPI
[03:46:55] [PASSED] USB
[03:46:55] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[03:46:55] ======== drm_test_drm_connector_dynamic_init_name  =========
[03:46:55] [PASSED] Unknown
[03:46:55] [PASSED] VGA
[03:46:55] [PASSED] DVI-I
[03:46:55] [PASSED] DVI-D
[03:46:55] [PASSED] DVI-A
[03:46:55] [PASSED] Composite
[03:46:55] [PASSED] SVIDEO
[03:46:55] [PASSED] LVDS
[03:46:55] [PASSED] Component
[03:46:55] [PASSED] DIN
[03:46:55] [PASSED] DP
[03:46:55] [PASSED] HDMI-A
[03:46:55] [PASSED] HDMI-B
[03:46:55] [PASSED] TV
[03:46:55] [PASSED] eDP
[03:46:55] [PASSED] Virtual
[03:46:55] [PASSED] DSI
[03:46:55] [PASSED] DPI
[03:46:55] [PASSED] Writeback
[03:46:55] [PASSED] SPI
[03:46:55] [PASSED] USB
[03:46:55] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[03:46:55] =========== [PASSED] drm_connector_dynamic_init ============
[03:46:55] ==== drm_connector_dynamic_register_early (4 subtests) =====
[03:46:55] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[03:46:55] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[03:46:55] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[03:46:55] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[03:46:55] ====== [PASSED] drm_connector_dynamic_register_early =======
[03:46:55] ======= drm_connector_dynamic_register (7 subtests) ========
[03:46:55] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[03:46:55] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[03:46:55] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[03:46:55] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[03:46:55] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[03:46:55] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[03:46:55] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[03:46:55] ========= [PASSED] drm_connector_dynamic_register ==========
[03:46:55] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[03:46:55] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[03:46:55] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[03:46:55] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[03:46:55] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[03:46:55] ========== drm_test_get_tv_mode_from_name_valid  ===========
[03:46:55] [PASSED] NTSC
[03:46:55] [PASSED] NTSC-443
[03:46:55] [PASSED] NTSC-J
[03:46:55] [PASSED] PAL
[03:46:55] [PASSED] PAL-M
[03:46:55] [PASSED] PAL-N
[03:46:55] [PASSED] SECAM
[03:46:55] [PASSED] Mono
[03:46:55] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[03:46:55] [PASSED] drm_test_get_tv_mode_from_name_truncated
[03:46:55] ============ [PASSED] drm_get_tv_mode_from_name ============
[03:46:55] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[03:46:55] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[03:46:55] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[03:46:55] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[03:46:55] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[03:46:55] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[03:46:55] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[03:46:55] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[03:46:55] [PASSED] VIC 96
[03:46:55] [PASSED] VIC 97
[03:46:55] [PASSED] VIC 101
[03:46:55] [PASSED] VIC 102
[03:46:55] [PASSED] VIC 106
[03:46:55] [PASSED] VIC 107
[03:46:55] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[03:46:55] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[03:46:55] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[03:46:55] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[03:46:55] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[03:46:55] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[03:46:55] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[03:46:55] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[03:46:55] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[03:46:55] [PASSED] Automatic
[03:46:55] [PASSED] Full
[03:46:55] [PASSED] Limited 16:235
[03:46:55] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[03:46:55] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[03:46:55] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[03:46:55] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[03:46:55] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[03:46:55] [PASSED] RGB
[03:46:55] [PASSED] YUV 4:2:0
[03:46:55] [PASSED] YUV 4:2:2
[03:46:55] [PASSED] YUV 4:4:4
[03:46:55] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[03:46:55] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[03:46:55] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[03:46:55] ============= drm_damage_helper (21 subtests) ==============
[03:46:55] [PASSED] drm_test_damage_iter_no_damage
[03:46:55] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[03:46:55] [PASSED] drm_test_damage_iter_no_damage_src_moved
[03:46:55] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[03:46:55] [PASSED] drm_test_damage_iter_no_damage_not_visible
[03:46:55] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[03:46:55] [PASSED] drm_test_damage_iter_no_damage_no_fb
[03:46:55] [PASSED] drm_test_damage_iter_simple_damage
[03:46:55] [PASSED] drm_test_damage_iter_single_damage
[03:46:55] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[03:46:55] [PASSED] drm_test_damage_iter_single_damage_outside_src
[03:46:55] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[03:46:55] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[03:46:55] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[03:46:55] [PASSED] drm_test_damage_iter_single_damage_src_moved
[03:46:55] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[03:46:55] [PASSED] drm_test_damage_iter_damage
[03:46:55] [PASSED] drm_test_damage_iter_damage_one_intersect
[03:46:55] [PASSED] drm_test_damage_iter_damage_one_outside
[03:46:55] [PASSED] drm_test_damage_iter_damage_src_moved
[03:46:55] [PASSED] drm_test_damage_iter_damage_not_visible
[03:46:55] ================ [PASSED] drm_damage_helper ================
[03:46:55] ============== drm_dp_mst_helper (3 subtests) ==============
[03:46:55] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[03:46:55] [PASSED] Clock 154000 BPP 30 DSC disabled
[03:46:55] [PASSED] Clock 234000 BPP 30 DSC disabled
[03:46:55] [PASSED] Clock 297000 BPP 24 DSC disabled
[03:46:55] [PASSED] Clock 332880 BPP 24 DSC enabled
[03:46:55] [PASSED] Clock 324540 BPP 24 DSC enabled
[03:46:55] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[03:46:55] ============== drm_test_dp_mst_calc_pbn_div  ===============
[03:46:55] [PASSED] Link rate 2000000 lane count 4
[03:46:55] [PASSED] Link rate 2000000 lane count 2
[03:46:55] [PASSED] Link rate 2000000 lane count 1
[03:46:55] [PASSED] Link rate 1350000 lane count 4
[03:46:55] [PASSED] Link rate 1350000 lane count 2
[03:46:55] [PASSED] Link rate 1350000 lane count 1
[03:46:55] [PASSED] Link rate 1000000 lane count 4
[03:46:55] [PASSED] Link rate 1000000 lane count 2
[03:46:55] [PASSED] Link rate 1000000 lane count 1
[03:46:55] [PASSED] Link rate 810000 lane count 4
[03:46:55] [PASSED] Link rate 810000 lane count 2
[03:46:55] [PASSED] Link rate 810000 lane count 1
[03:46:55] [PASSED] Link rate 540000 lane count 4
[03:46:55] [PASSED] Link rate 540000 lane count 2
[03:46:55] [PASSED] Link rate 540000 lane count 1
[03:46:55] [PASSED] Link rate 270000 lane count 4
[03:46:55] [PASSED] Link rate 270000 lane count 2
[03:46:55] [PASSED] Link rate 270000 lane count 1
[03:46:55] [PASSED] Link rate 162000 lane count 4
[03:46:55] [PASSED] Link rate 162000 lane count 2
[03:46:55] [PASSED] Link rate 162000 lane count 1
[03:46:55] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[03:46:55] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[03:46:55] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[03:46:55] [PASSED] DP_POWER_UP_PHY with port number
[03:46:55] [PASSED] DP_POWER_DOWN_PHY with port number
[03:46:55] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[03:46:55] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[03:46:55] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[03:46:55] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[03:46:55] [PASSED] DP_QUERY_PAYLOAD with port number
[03:46:55] [PASSED] DP_QUERY_PAYLOAD with VCPI
[03:46:55] [PASSED] DP_REMOTE_DPCD_READ with port number
[03:46:55] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[03:46:55] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[03:46:55] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[03:46:55] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[03:46:55] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[03:46:55] [PASSED] DP_REMOTE_I2C_READ with port number
[03:46:55] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[03:46:55] [PASSED] DP_REMOTE_I2C_READ with transactions array
[03:46:55] [PASSED] DP_REMOTE_I2C_WRITE with port number
[03:46:55] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[03:46:55] [PASSED] DP_REMOTE_I2C_WRITE with data array
[03:46:55] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[03:46:55] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[03:46:55] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[03:46:55] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[03:46:55] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[03:46:55] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[03:46:55] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[03:46:55] ================ [PASSED] drm_dp_mst_helper ================
[03:46:55] ================== drm_exec (7 subtests) ===================
[03:46:55] [PASSED] sanitycheck
[03:46:55] [PASSED] test_lock
[03:46:55] [PASSED] test_lock_unlock
[03:46:55] [PASSED] test_duplicates
[03:46:55] [PASSED] test_prepare
[03:46:55] [PASSED] test_prepare_array
[03:46:55] [PASSED] test_multiple_loops
[03:46:55] ==================== [PASSED] drm_exec =====================
[03:46:55] =========== drm_format_helper_test (17 subtests) ===========
[03:46:55] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[03:46:55] [PASSED] single_pixel_source_buffer
[03:46:55] [PASSED] single_pixel_clip_rectangle
[03:46:55] [PASSED] well_known_colors
[03:46:55] [PASSED] destination_pitch
[03:46:55] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[03:46:55] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[03:46:55] [PASSED] single_pixel_source_buffer
[03:46:55] [PASSED] single_pixel_clip_rectangle
[03:46:55] [PASSED] well_known_colors
[03:46:55] [PASSED] destination_pitch
[03:46:55] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[03:46:55] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[03:46:55] [PASSED] single_pixel_source_buffer
[03:46:55] [PASSED] single_pixel_clip_rectangle
[03:46:55] [PASSED] well_known_colors
[03:46:55] [PASSED] destination_pitch
[03:46:55] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[03:46:55] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[03:46:55] [PASSED] single_pixel_source_buffer
[03:46:55] [PASSED] single_pixel_clip_rectangle
[03:46:55] [PASSED] well_known_colors
[03:46:55] [PASSED] destination_pitch
[03:46:55] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[03:46:55] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[03:46:55] [PASSED] single_pixel_source_buffer
[03:46:55] [PASSED] single_pixel_clip_rectangle
[03:46:55] [PASSED] well_known_colors
[03:46:55] [PASSED] destination_pitch
[03:46:55] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[03:46:55] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[03:46:55] [PASSED] single_pixel_source_buffer
[03:46:55] [PASSED] single_pixel_clip_rectangle
[03:46:55] [PASSED] well_known_colors
[03:46:55] [PASSED] destination_pitch
[03:46:55] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[03:46:55] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[03:46:55] [PASSED] single_pixel_source_buffer
[03:46:55] [PASSED] single_pixel_clip_rectangle
[03:46:55] [PASSED] well_known_colors
[03:46:55] [PASSED] destination_pitch
[03:46:55] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[03:46:55] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[03:46:55] [PASSED] single_pixel_source_buffer
[03:46:55] [PASSED] single_pixel_clip_rectangle
[03:46:55] [PASSED] well_known_colors
[03:46:55] [PASSED] destination_pitch
[03:46:55] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[03:46:55] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[03:46:55] [PASSED] single_pixel_source_buffer
[03:46:55] [PASSED] single_pixel_clip_rectangle
[03:46:55] [PASSED] well_known_colors
[03:46:55] [PASSED] destination_pitch
[03:46:55] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[03:46:55] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[03:46:55] [PASSED] single_pixel_source_buffer
[03:46:55] [PASSED] single_pixel_clip_rectangle
[03:46:55] [PASSED] well_known_colors
[03:46:55] [PASSED] destination_pitch
[03:46:55] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[03:46:55] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[03:46:55] [PASSED] single_pixel_source_buffer
[03:46:55] [PASSED] single_pixel_clip_rectangle
[03:46:55] [PASSED] well_known_colors
[03:46:55] [PASSED] destination_pitch
[03:46:55] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[03:46:55] ============== drm_test_fb_xrgb8888_to_mono  ===============
[03:46:55] [PASSED] single_pixel_source_buffer
[03:46:55] [PASSED] single_pixel_clip_rectangle
[03:46:55] [PASSED] well_known_colors
[03:46:55] [PASSED] destination_pitch
[03:46:55] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[03:46:55] ==================== drm_test_fb_swab  =====================
[03:46:55] [PASSED] single_pixel_source_buffer
[03:46:55] [PASSED] single_pixel_clip_rectangle
[03:46:55] [PASSED] well_known_colors
[03:46:55] [PASSED] destination_pitch
[03:46:55] ================ [PASSED] drm_test_fb_swab =================
[03:46:55] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[03:46:55] [PASSED] single_pixel_source_buffer
[03:46:55] [PASSED] single_pixel_clip_rectangle
[03:46:55] [PASSED] well_known_colors
[03:46:55] [PASSED] destination_pitch
[03:46:55] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[03:46:55] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[03:46:55] [PASSED] single_pixel_source_buffer
[03:46:55] [PASSED] single_pixel_clip_rectangle
[03:46:55] [PASSED] well_known_colors
[03:46:55] [PASSED] destination_pitch
[03:46:55] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[03:46:55] ================= drm_test_fb_clip_offset  =================
[03:46:55] [PASSED] pass through
[03:46:55] [PASSED] horizontal offset
[03:46:55] [PASSED] vertical offset
[03:46:55] [PASSED] horizontal and vertical offset
[03:46:55] [PASSED] horizontal offset (custom pitch)
[03:46:55] [PASSED] vertical offset (custom pitch)
[03:46:55] [PASSED] horizontal and vertical offset (custom pitch)
[03:46:55] ============= [PASSED] drm_test_fb_clip_offset =============
[03:46:55] =================== drm_test_fb_memcpy  ====================
[03:46:55] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[03:46:55] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[03:46:55] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[03:46:55] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[03:46:55] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[03:46:55] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[03:46:55] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[03:46:55] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[03:46:55] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[03:46:55] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[03:46:55] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[03:46:55] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[03:46:55] =============== [PASSED] drm_test_fb_memcpy ================
[03:46:55] ============= [PASSED] drm_format_helper_test ==============
[03:46:55] ================= drm_format (18 subtests) =================
[03:46:55] [PASSED] drm_test_format_block_width_invalid
[03:46:55] [PASSED] drm_test_format_block_width_one_plane
[03:46:55] [PASSED] drm_test_format_block_width_two_plane
[03:46:55] [PASSED] drm_test_format_block_width_three_plane
[03:46:55] [PASSED] drm_test_format_block_width_tiled
[03:46:55] [PASSED] drm_test_format_block_height_invalid
[03:46:55] [PASSED] drm_test_format_block_height_one_plane
[03:46:55] [PASSED] drm_test_format_block_height_two_plane
[03:46:55] [PASSED] drm_test_format_block_height_three_plane
[03:46:55] [PASSED] drm_test_format_block_height_tiled
[03:46:55] [PASSED] drm_test_format_min_pitch_invalid
[03:46:55] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[03:46:55] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[03:46:55] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[03:46:55] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[03:46:55] [PASSED] drm_test_format_min_pitch_two_plane
[03:46:55] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[03:46:55] [PASSED] drm_test_format_min_pitch_tiled
[03:46:55] =================== [PASSED] drm_format ====================
[03:46:55] ============== drm_framebuffer (10 subtests) ===============
[03:46:55] ========== drm_test_framebuffer_check_src_coords  ==========
[03:46:55] [PASSED] Success: source fits into fb
[03:46:55] [PASSED] Fail: overflowing fb with x-axis coordinate
[03:46:55] [PASSED] Fail: overflowing fb with y-axis coordinate
[03:46:55] [PASSED] Fail: overflowing fb with source width
[03:46:55] [PASSED] Fail: overflowing fb with source height
[03:46:55] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[03:46:55] [PASSED] drm_test_framebuffer_cleanup
[03:46:55] =============== drm_test_framebuffer_create  ===============
[03:46:55] [PASSED] ABGR8888 normal sizes
[03:46:55] [PASSED] ABGR8888 max sizes
[03:46:55] [PASSED] ABGR8888 pitch greater than min required
[03:46:55] [PASSED] ABGR8888 pitch less than min required
[03:46:55] [PASSED] ABGR8888 Invalid width
[03:46:55] [PASSED] ABGR8888 Invalid buffer handle
[03:46:55] [PASSED] No pixel format
[03:46:55] [PASSED] ABGR8888 Width 0
[03:46:55] [PASSED] ABGR8888 Height 0
[03:46:55] [PASSED] ABGR8888 Out of bound height * pitch combination
[03:46:55] [PASSED] ABGR8888 Large buffer offset
[03:46:55] [PASSED] ABGR8888 Buffer offset for inexistent plane
[03:46:55] [PASSED] ABGR8888 Invalid flag
[03:46:55] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[03:46:55] [PASSED] ABGR8888 Valid buffer modifier
[03:46:55] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[03:46:55] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[03:46:55] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[03:46:55] [PASSED] NV12 Normal sizes
[03:46:55] [PASSED] NV12 Max sizes
[03:46:55] [PASSED] NV12 Invalid pitch
[03:46:55] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[03:46:55] [PASSED] NV12 different  modifier per-plane
[03:46:55] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[03:46:55] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[03:46:55] [PASSED] NV12 Modifier for inexistent plane
[03:46:55] [PASSED] NV12 Handle for inexistent plane
[03:46:55] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[03:46:55] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[03:46:55] [PASSED] YVU420 Normal sizes
[03:46:55] [PASSED] YVU420 Max sizes
[03:46:55] [PASSED] YVU420 Invalid pitch
[03:46:55] [PASSED] YVU420 Different pitches
[03:46:55] [PASSED] YVU420 Different buffer offsets/pitches
[03:46:55] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[03:46:55] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[03:46:55] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[03:46:55] [PASSED] YVU420 Valid modifier
[03:46:55] [PASSED] YVU420 Different modifiers per plane
[03:46:55] [PASSED] YVU420 Modifier for inexistent plane
[03:46:55] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[03:46:55] [PASSED] X0L2 Normal sizes
[03:46:55] [PASSED] X0L2 Max sizes
[03:46:55] [PASSED] X0L2 Invalid pitch
[03:46:55] [PASSED] X0L2 Pitch greater than minimum required
[03:46:55] [PASSED] X0L2 Handle for inexistent plane
[03:46:55] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[03:46:55] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[03:46:55] [PASSED] X0L2 Valid modifier
[03:46:55] [PASSED] X0L2 Modifier for inexistent plane
[03:46:55] =========== [PASSED] drm_test_framebuffer_create ===========
[03:46:55] [PASSED] drm_test_framebuffer_free
[03:46:55] [PASSED] drm_test_framebuffer_init
[03:46:55] [PASSED] drm_test_framebuffer_init_bad_format
[03:46:55] [PASSED] drm_test_framebuffer_init_dev_mismatch
[03:46:55] [PASSED] drm_test_framebuffer_lookup
[03:46:55] [PASSED] drm_test_framebuffer_lookup_inexistent
[03:46:55] [PASSED] drm_test_framebuffer_modifiers_not_supported
[03:46:55] ================= [PASSED] drm_framebuffer =================
[03:46:55] ================ drm_gem_shmem (8 subtests) ================
[03:46:55] [PASSED] drm_gem_shmem_test_obj_create
[03:46:55] [PASSED] drm_gem_shmem_test_obj_create_private
[03:46:55] [PASSED] drm_gem_shmem_test_pin_pages
[03:46:55] [PASSED] drm_gem_shmem_test_vmap
[03:46:55] [PASSED] drm_gem_shmem_test_get_pages_sgt
[03:46:55] [PASSED] drm_gem_shmem_test_get_sg_table
[03:46:55] [PASSED] drm_gem_shmem_test_madvise
[03:46:55] [PASSED] drm_gem_shmem_test_purge
[03:46:55] ================== [PASSED] drm_gem_shmem ==================
[03:46:55] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[03:46:55] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[03:46:55] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[03:46:55] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[03:46:55] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[03:46:55] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[03:46:55] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[03:46:55] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[03:46:55] [PASSED] Automatic
[03:46:55] [PASSED] Full
[03:46:55] [PASSED] Limited 16:235
[03:46:55] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[03:46:55] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[03:46:55] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[03:46:55] [PASSED] drm_test_check_disable_connector
[03:46:55] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[03:46:55] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[03:46:55] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[03:46:55] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[03:46:55] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[03:46:55] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[03:46:55] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[03:46:55] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[03:46:55] [PASSED] drm_test_check_output_bpc_dvi
[03:46:55] [PASSED] drm_test_check_output_bpc_format_vic_1
[03:46:55] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[03:46:55] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[03:46:55] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[03:46:55] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[03:46:55] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[03:46:55] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[03:46:55] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[03:46:55] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[03:46:55] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[03:46:55] [PASSED] drm_test_check_broadcast_rgb_value
[03:46:55] [PASSED] drm_test_check_bpc_8_value
[03:46:55] [PASSED] drm_test_check_bpc_10_value
[03:46:55] [PASSED] drm_test_check_bpc_12_value
[03:46:55] [PASSED] drm_test_check_format_value
[03:46:55] [PASSED] drm_test_check_tmds_char_value
[03:46:55] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[03:46:55] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[03:46:55] [PASSED] drm_test_check_mode_valid
[03:46:55] [PASSED] drm_test_check_mode_valid_reject
[03:46:55] [PASSED] drm_test_check_mode_valid_reject_rate
[03:46:55] [PASSED] drm_test_check_mode_valid_reject_max_clock
[03:46:55] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[03:46:55] ================= drm_managed (2 subtests) =================
[03:46:55] [PASSED] drm_test_managed_release_action
[03:46:55] [PASSED] drm_test_managed_run_action
[03:46:55] =================== [PASSED] drm_managed ===================
[03:46:55] =================== drm_mm (6 subtests) ====================
[03:46:55] [PASSED] drm_test_mm_init
[03:46:55] [PASSED] drm_test_mm_debug
[03:46:55] [PASSED] drm_test_mm_align32
[03:46:55] [PASSED] drm_test_mm_align64
[03:46:55] [PASSED] drm_test_mm_lowest
[03:46:55] [PASSED] drm_test_mm_highest
[03:46:55] ===================== [PASSED] drm_mm ======================
[03:46:55] ============= drm_modes_analog_tv (5 subtests) =============
[03:46:55] [PASSED] drm_test_modes_analog_tv_mono_576i
[03:46:55] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[03:46:55] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[03:46:55] [PASSED] drm_test_modes_analog_tv_pal_576i
[03:46:55] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[03:46:55] =============== [PASSED] drm_modes_analog_tv ===============
[03:46:55] ============== drm_plane_helper (2 subtests) ===============
[03:46:55] =============== drm_test_check_plane_state  ================
[03:46:55] [PASSED] clipping_simple
[03:46:55] [PASSED] clipping_rotate_reflect
[03:46:55] [PASSED] positioning_simple
[03:46:55] [PASSED] upscaling
[03:46:55] [PASSED] downscaling
[03:46:55] [PASSED] rounding1
[03:46:55] [PASSED] rounding2
[03:46:55] [PASSED] rounding3
[03:46:55] [PASSED] rounding4
[03:46:55] =========== [PASSED] drm_test_check_plane_state ============
[03:46:55] =========== drm_test_check_invalid_plane_state  ============
[03:46:55] [PASSED] positioning_invalid
[03:46:55] [PASSED] upscaling_invalid
[03:46:55] [PASSED] downscaling_invalid
[03:46:55] ======= [PASSED] drm_test_check_invalid_plane_state ========
[03:46:55] ================ [PASSED] drm_plane_helper =================
[03:46:55] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[03:46:55] ====== drm_test_connector_helper_tv_get_modes_check  =======
[03:46:55] [PASSED] None
[03:46:55] [PASSED] PAL
[03:46:55] [PASSED] NTSC
[03:46:55] [PASSED] Both, NTSC Default
[03:46:55] [PASSED] Both, PAL Default
[03:46:55] [PASSED] Both, NTSC Default, with PAL on command-line
[03:46:55] [PASSED] Both, PAL Default, with NTSC on command-line
[03:46:55] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[03:46:55] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[03:46:55] ================== drm_rect (9 subtests) ===================
[03:46:55] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[03:46:55] [PASSED] drm_test_rect_clip_scaled_not_clipped
[03:46:55] [PASSED] drm_test_rect_clip_scaled_clipped
[03:46:55] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[03:46:55] ================= drm_test_rect_intersect  =================
[03:46:55] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[03:46:55] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[03:46:55] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[03:46:55] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[03:46:55] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[03:46:55] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[03:46:55] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[03:46:55] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[03:46:55] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[03:46:55] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[03:46:55] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[03:46:55] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[03:46:55] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[03:46:55] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[03:46:55] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[03:46:55] ============= [PASSED] drm_test_rect_intersect =============
[03:46:55] ================ drm_test_rect_calc_hscale  ================
[03:46:55] [PASSED] normal use
[03:46:55] [PASSED] out of max range
[03:46:55] [PASSED] out of min range
[03:46:55] [PASSED] zero dst
[03:46:55] [PASSED] negative src
[03:46:55] [PASSED] negative dst
[03:46:55] ============ [PASSED] drm_test_rect_calc_hscale ============
[03:46:55] ================ drm_test_rect_calc_vscale  ================
[03:46:55] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[03:46:55] [PASSED] out of max range
[03:46:55] [PASSED] out of min range
[03:46:55] [PASSED] zero dst
[03:46:55] [PASSED] negative src
[03:46:55] [PASSED] negative dst
[03:46:55] ============ [PASSED] drm_test_rect_calc_vscale ============
[03:46:55] ================== drm_test_rect_rotate  ===================
[03:46:55] [PASSED] reflect-x
[03:46:55] [PASSED] reflect-y
[03:46:55] [PASSED] rotate-0
[03:46:55] [PASSED] rotate-90
[03:46:55] [PASSED] rotate-180
[03:46:55] [PASSED] rotate-270
[03:46:55] ============== [PASSED] drm_test_rect_rotate ===============
[03:46:55] ================ drm_test_rect_rotate_inv  =================
[03:46:55] [PASSED] reflect-x
[03:46:55] [PASSED] reflect-y
[03:46:55] [PASSED] rotate-0
[03:46:55] [PASSED] rotate-90
[03:46:55] [PASSED] rotate-180
[03:46:55] [PASSED] rotate-270
[03:46:55] ============ [PASSED] drm_test_rect_rotate_inv =============
[03:46:55] ==================== [PASSED] drm_rect =====================
[03:46:55] ============ drm_sysfb_modeset_test (1 subtest) ============
[03:46:55] ============ drm_test_sysfb_build_fourcc_list  =============
[03:46:55] [PASSED] no native formats
[03:46:55] [PASSED] XRGB8888 as native format
[03:46:55] [PASSED] remove duplicates
[03:46:55] [PASSED] convert alpha formats
[03:46:55] [PASSED] random formats
[03:46:55] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[03:46:55] ============= [PASSED] drm_sysfb_modeset_test ==============
[03:46:55] ============================================================
[03:46:55] Testing complete. Ran 622 tests: passed: 622
[03:46:55] Elapsed time: 26.886s total, 1.744s configuring, 24.725s building, 0.386s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[03:46:55] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[03:46:57] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[03:47:06] Starting KUnit Kernel (1/1)...
[03:47:06] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[03:47:06] ================= ttm_device (5 subtests) ==================
[03:47:06] [PASSED] ttm_device_init_basic
[03:47:06] [PASSED] ttm_device_init_multiple
[03:47:06] [PASSED] ttm_device_fini_basic
[03:47:06] [PASSED] ttm_device_init_no_vma_man
[03:47:06] ================== ttm_device_init_pools  ==================
[03:47:06] [PASSED] No DMA allocations, no DMA32 required
[03:47:06] [PASSED] DMA allocations, DMA32 required
[03:47:06] [PASSED] No DMA allocations, DMA32 required
[03:47:06] [PASSED] DMA allocations, no DMA32 required
[03:47:06] ============== [PASSED] ttm_device_init_pools ==============
[03:47:06] =================== [PASSED] ttm_device ====================
[03:47:06] ================== ttm_pool (8 subtests) ===================
[03:47:06] ================== ttm_pool_alloc_basic  ===================
[03:47:06] [PASSED] One page
[03:47:06] [PASSED] More than one page
[03:47:06] [PASSED] Above the allocation limit
[03:47:06] [PASSED] One page, with coherent DMA mappings enabled
[03:47:06] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[03:47:06] ============== [PASSED] ttm_pool_alloc_basic ===============
[03:47:06] ============== ttm_pool_alloc_basic_dma_addr  ==============
[03:47:06] [PASSED] One page
[03:47:06] [PASSED] More than one page
[03:47:06] [PASSED] Above the allocation limit
[03:47:06] [PASSED] One page, with coherent DMA mappings enabled
[03:47:06] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[03:47:06] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[03:47:06] [PASSED] ttm_pool_alloc_order_caching_match
[03:47:06] [PASSED] ttm_pool_alloc_caching_mismatch
[03:47:06] [PASSED] ttm_pool_alloc_order_mismatch
[03:47:06] [PASSED] ttm_pool_free_dma_alloc
[03:47:06] [PASSED] ttm_pool_free_no_dma_alloc
[03:47:06] [PASSED] ttm_pool_fini_basic
[03:47:06] ==================== [PASSED] ttm_pool =====================
[03:47:06] ================ ttm_resource (8 subtests) =================
[03:47:06] ================= ttm_resource_init_basic  =================
[03:47:06] [PASSED] Init resource in TTM_PL_SYSTEM
[03:47:06] [PASSED] Init resource in TTM_PL_VRAM
[03:47:06] [PASSED] Init resource in a private placement
[03:47:06] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[03:47:06] ============= [PASSED] ttm_resource_init_basic =============
[03:47:06] [PASSED] ttm_resource_init_pinned
[03:47:06] [PASSED] ttm_resource_fini_basic
[03:47:06] [PASSED] ttm_resource_manager_init_basic
[03:47:06] [PASSED] ttm_resource_manager_usage_basic
[03:47:06] [PASSED] ttm_resource_manager_set_used_basic
[03:47:06] [PASSED] ttm_sys_man_alloc_basic
[03:47:06] [PASSED] ttm_sys_man_free_basic
[03:47:06] ================== [PASSED] ttm_resource ===================
[03:47:06] =================== ttm_tt (15 subtests) ===================
[03:47:06] ==================== ttm_tt_init_basic  ====================
[03:47:06] [PASSED] Page-aligned size
[03:47:06] [PASSED] Extra pages requested
[03:47:06] ================ [PASSED] ttm_tt_init_basic ================
[03:47:06] [PASSED] ttm_tt_init_misaligned
[03:47:06] [PASSED] ttm_tt_fini_basic
[03:47:06] [PASSED] ttm_tt_fini_sg
[03:47:06] [PASSED] ttm_tt_fini_shmem
[03:47:06] [PASSED] ttm_tt_create_basic
[03:47:06] [PASSED] ttm_tt_create_invalid_bo_type
[03:47:06] [PASSED] ttm_tt_create_ttm_exists
[03:47:06] [PASSED] ttm_tt_create_failed
[03:47:06] [PASSED] ttm_tt_destroy_basic
[03:47:06] [PASSED] ttm_tt_populate_null_ttm
[03:47:06] [PASSED] ttm_tt_populate_populated_ttm
[03:47:06] [PASSED] ttm_tt_unpopulate_basic
[03:47:06] [PASSED] ttm_tt_unpopulate_empty_ttm
[03:47:06] [PASSED] ttm_tt_swapin_basic
[03:47:06] ===================== [PASSED] ttm_tt ======================
[03:47:06] =================== ttm_bo (14 subtests) ===================
[03:47:06] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[03:47:06] [PASSED] Cannot be interrupted and sleeps
[03:47:06] [PASSED] Cannot be interrupted, locks straight away
[03:47:06] [PASSED] Can be interrupted, sleeps
[03:47:06] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[03:47:06] [PASSED] ttm_bo_reserve_locked_no_sleep
[03:47:06] [PASSED] ttm_bo_reserve_no_wait_ticket
[03:47:06] [PASSED] ttm_bo_reserve_double_resv
[03:47:06] [PASSED] ttm_bo_reserve_interrupted
[03:47:06] [PASSED] ttm_bo_reserve_deadlock
[03:47:06] [PASSED] ttm_bo_unreserve_basic
[03:47:06] [PASSED] ttm_bo_unreserve_pinned
[03:47:06] [PASSED] ttm_bo_unreserve_bulk
[03:47:06] [PASSED] ttm_bo_fini_basic
[03:47:06] [PASSED] ttm_bo_fini_shared_resv
[03:47:06] [PASSED] ttm_bo_pin_basic
[03:47:06] [PASSED] ttm_bo_pin_unpin_resource
[03:47:06] [PASSED] ttm_bo_multiple_pin_one_unpin
[03:47:06] ===================== [PASSED] ttm_bo ======================
[03:47:06] ============== ttm_bo_validate (21 subtests) ===============
[03:47:06] ============== ttm_bo_init_reserved_sys_man  ===============
[03:47:06] [PASSED] Buffer object for userspace
[03:47:06] [PASSED] Kernel buffer object
[03:47:06] [PASSED] Shared buffer object
[03:47:06] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[03:47:06] ============== ttm_bo_init_reserved_mock_man  ==============
[03:47:06] [PASSED] Buffer object for userspace
[03:47:06] [PASSED] Kernel buffer object
[03:47:06] [PASSED] Shared buffer object
[03:47:06] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[03:47:06] [PASSED] ttm_bo_init_reserved_resv
[03:47:06] ================== ttm_bo_validate_basic  ==================
[03:47:06] [PASSED] Buffer object for userspace
[03:47:06] [PASSED] Kernel buffer object
[03:47:06] [PASSED] Shared buffer object
[03:47:06] ============== [PASSED] ttm_bo_validate_basic ==============
[03:47:06] [PASSED] ttm_bo_validate_invalid_placement
[03:47:06] ============= ttm_bo_validate_same_placement  ==============
[03:47:06] [PASSED] System manager
[03:47:06] [PASSED] VRAM manager
[03:47:06] ========= [PASSED] ttm_bo_validate_same_placement ==========
[03:47:06] [PASSED] ttm_bo_validate_failed_alloc
[03:47:06] [PASSED] ttm_bo_validate_pinned
[03:47:06] [PASSED] ttm_bo_validate_busy_placement
[03:47:06] ================ ttm_bo_validate_multihop  =================
[03:47:06] [PASSED] Buffer object for userspace
[03:47:06] [PASSED] Kernel buffer object
[03:47:06] [PASSED] Shared buffer object
[03:47:06] ============ [PASSED] ttm_bo_validate_multihop =============
[03:47:06] ========== ttm_bo_validate_no_placement_signaled  ==========
[03:47:06] [PASSED] Buffer object in system domain, no page vector
[03:47:06] [PASSED] Buffer object in system domain with an existing page vector
[03:47:06] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[03:47:06] ======== ttm_bo_validate_no_placement_not_signaled  ========
[03:47:06] [PASSED] Buffer object for userspace
[03:47:06] [PASSED] Kernel buffer object
[03:47:06] [PASSED] Shared buffer object
[03:47:06] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[03:47:06] [PASSED] ttm_bo_validate_move_fence_signaled
[03:47:06] ========= ttm_bo_validate_move_fence_not_signaled  =========
[03:47:06] [PASSED] Waits for GPU
[03:47:06] [PASSED] Tries to lock straight away
[03:47:06] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[03:47:06] [PASSED] ttm_bo_validate_happy_evict
[03:47:06] [PASSED] ttm_bo_validate_all_pinned_evict
[03:47:06] [PASSED] ttm_bo_validate_allowed_only_evict
[03:47:06] [PASSED] ttm_bo_validate_deleted_evict
[03:47:06] [PASSED] ttm_bo_validate_busy_domain_evict
[03:47:06] [PASSED] ttm_bo_validate_evict_gutting
[03:47:06] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[03:47:06] ================= [PASSED] ttm_bo_validate =================
[03:47:06] ============================================================
[03:47:06] Testing complete. Ran 101 tests: passed: 101
[03:47:06] Elapsed time: 11.412s total, 1.668s configuring, 9.476s building, 0.226s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/xe: Add Xe3p support

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1451 bytes --]

== Series Details ==

Series: drm/xe: Add Xe3p support
URL   : https://patchwork.freedesktop.org/series/155866/
State : success

== Summary ==

CI Bug Log - changes from xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada_BAT -> xe-pw-155866v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-155866v1_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_flip@basic-plain-flip@b-edp1:
    - bat-adlp-7:         [PASS][1] -> [DMESG-WARN][2] ([Intel XE#4543]) +1 other test dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/bat-adlp-7/igt@kms_flip@basic-plain-flip@b-edp1.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/bat-adlp-7/igt@kms_flip@basic-plain-flip@b-edp1.html

  
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543


Build changes
-------------

  * Linux: xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada -> xe-pw-155866v1

  IGT_8582: 8582
  xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada: c917f7d11493984be9f381ca0a7667bd3e587ada
  xe-pw-155866v1: 155866v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/index.html

[-- Attachment #2: Type: text/html, Size: 2016 bytes --]

Re: [PATCH 01/23] drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05

[Shekhar Chauhan]

On 10/14/2025 8:54, Lucas De Marchi wrote:
> From: Shekhar Chauhan <shekhar.chauhan@intel.com>
>
> Add graphics IP versions 30.04 & 30.05 and initial workarounds for these
> IP versions.
>
> BSpec: 74201
> Cc: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
> Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_pci.c        | 2 ++
>   drivers/gpu/drm/xe/xe_wa.c         | 6 +++---
>   drivers/gpu/drm/xe/xe_wa_oob.rules | 7 +++++--
>   3 files changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 944c698808ace..c1e89689953b7 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -149,6 +149,8 @@ static const struct xe_ip graphics_ips[] = {
>   	{ 3000, "Xe3_LPG", &graphics_xe2 },
>   	{ 3001, "Xe3_LPG", &graphics_xe2 },
>   	{ 3003, "Xe3_LPG", &graphics_xe2 },
> +	{ 3004, "Xe3_LPG", &graphics_xe2 },
> +	{ 3005, "Xe3_LPG", &graphics_xe2 },
>   };
>   
>   /* Pre-GMDID Media IPs */
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index c60159a130014..24b6d4bb0b962 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -684,7 +684,7 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>   	},
>   	{ XE_RTP_NAME("13012615864"),
>   	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), OR,
> -		       GRAPHICS_VERSION(3003),
> +		       GRAPHICS_VERSION_RANGE(3003, 3005),
>   		       FUNC(xe_rtp_match_first_render_or_compute)),
>   	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
>   	},
> @@ -695,7 +695,7 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>   			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
>   	},
>   	{ XE_RTP_NAME("14021402888"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION(3003), FUNC(xe_rtp_match_first_render_or_compute)),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3003, 3005), FUNC(xe_rtp_match_first_render_or_compute)),
>   	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
>   	},
>   	{ XE_RTP_NAME("18041344222"),
> @@ -913,7 +913,7 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>   			     DIS_AUTOSTRIP))
>   	},
>   	{ XE_RTP_NAME("22021007897"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3003), ENGINE_CLASS(RENDER)),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)),
>   	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
>   	},
>   };
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index f3a6d5d239cec..9aff2e56fd3e4 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -34,14 +34,17 @@
>   13011645652	GRAPHICS_VERSION(2004)
>   		GRAPHICS_VERSION_RANGE(3000, 3001)
>   		GRAPHICS_VERSION(3003)
> +		GRAPHICS_VERSION_RANGE(3004, 3005)
>   14022293748	GRAPHICS_VERSION_RANGE(2001, 2002)

Any specific reason for keeping 3003 different from the range of (3004, 
3005)? Can we have a single range from (3003, 3005)? Same for the two 
additions below.

Other than this, there are a couple of new workarounds which are 
introduced for these IPs, but maybe we can add them once the initial 
upstreaming is finished, nothing major.

Apart from these two comments, LGTM, and,

Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>

>   		GRAPHICS_VERSION(2004)
>   		GRAPHICS_VERSION_RANGE(3000, 3001)
>   		GRAPHICS_VERSION(3003)
> +		GRAPHICS_VERSION_RANGE(3004, 3005)
>   22019794406	GRAPHICS_VERSION_RANGE(2001, 2002)
>   		GRAPHICS_VERSION(2004)
>   		GRAPHICS_VERSION_RANGE(3000, 3001)
>   		GRAPHICS_VERSION(3003)
> +		GRAPHICS_VERSION_RANGE(3004, 3005)
>   22019338487	MEDIA_VERSION(2000)
>   		GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_not_sriov_vf)
>   		MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), FUNC(xe_rtp_match_not_sriov_vf)
> @@ -63,11 +66,11 @@
>   16023105232	GRAPHICS_VERSION_RANGE(2001, 3001)
>   		MEDIA_VERSION_RANGE(1301, 3000)
>   		MEDIA_VERSION(3002)
> -		GRAPHICS_VERSION(3003)
> +		GRAPHICS_VERSION_RANGE(3003, 3005)
>   16026508708	GRAPHICS_VERSION_RANGE(1200, 3001)
>   		MEDIA_VERSION_RANGE(1300, 3000)
>   		MEDIA_VERSION(3002)
> -		GRAPHICS_VERSION(3003)
> +		GRAPHICS_VERSION_RANGE(3003, 3005)
>   14020001231	GRAPHICS_VERSION_RANGE(2001,2004), FUNC(xe_rtp_match_psmi_enabled)
>   		MEDIA_VERSION(2000), FUNC(xe_rtp_match_psmi_enabled)
>   		MEDIA_VERSION(3000), FUNC(xe_rtp_match_psmi_enabled)
>

Re: [PATCH 02/23] drm/xe/xe3p_lpm: Add support for media IP versions 35.00 & 35.03

[Shekhar Chauhan]

On 10/14/2025 8:54, Lucas De Marchi wrote:
> From: Shekhar Chauhan <shekhar.chauhan@intel.com>
>
> Xe3p_LPM is very similar to Xe3_LPM on the kmd interface, so it can use
> the same descriptor structure. Add both 35.00 and 35.03 IP versions.
>
> BSpec: 74201, 74202, 77977
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
LGTM,
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_pci.c | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index c1e89689953b7..8480e53990031 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -164,6 +164,8 @@ static const struct xe_ip media_ips[] = {
>   	{ 2000, "Xe2_LPM", &media_xelpmp },
>   	{ 3000, "Xe3_LPM", &media_xelpmp },
>   	{ 3002, "Xe3_LPM", &media_xelpmp },
> +	{ 3500, "Xe3p_LPM", &media_xelpmp },
> +	{ 3503, "Xe3p_LPM", &media_xelpmp },
>   };
>   
>   static const struct xe_device_desc tgl_desc = {
>

Re: [PATCH 14/23] drm/xe/nvl: Define NVL-S platform

[Shekhar Chauhan]

On 10/14/2025 8:54, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
>
> Provide the basic platform definitions and PCI IDs for NVL-S.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

LGTM,

Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>

> ---
>   drivers/gpu/drm/xe/xe_pci.c            | 9 +++++++++
>   drivers/gpu/drm/xe/xe_platform_types.h | 1 +
>   include/drm/intel/pciids.h             | 9 +++++++++
>   3 files changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 8480e53990031..aa8359a4c5594 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -354,6 +354,14 @@ static const struct xe_device_desc ptl_desc = {
>   	.needs_shared_vf_gt_wq = true,
>   };
>   
> +static const struct xe_device_desc nvls_desc = {
> +	PLATFORM(NOVALAKE_S),
> +	.dma_mask_size = 46,
> +	.has_display = true,
> +	.max_gt_per_tile = 2,
> +	.require_force_probe = true,
> +};
> +
>   #undef PLATFORM
>   __diag_pop();
>   
> @@ -382,6 +390,7 @@ static const struct pci_device_id pciidlist[] = {
>   	INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
>   	INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
>   	INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
> +	INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
>   	{ }
>   };
>   MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
> index d08574c4cdb8b..f5140a244daf3 100644
> --- a/drivers/gpu/drm/xe/xe_platform_types.h
> +++ b/drivers/gpu/drm/xe/xe_platform_types.h
> @@ -24,6 +24,7 @@ enum xe_platform {
>   	XE_LUNARLAKE,
>   	XE_BATTLEMAGE,
>   	XE_PANTHERLAKE,
> +	XE_NOVALAKE_S,
>   };
>   
>   enum xe_subplatform {
> diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
> index 69d4ae92d822a..00dd007f538ff 100644
> --- a/include/drm/intel/pciids.h
> +++ b/include/drm/intel/pciids.h
> @@ -884,4 +884,13 @@
>   	MACRO__(0xFD80, ## __VA_ARGS__), \
>   	MACRO__(0xFD81, ## __VA_ARGS__)
>   
> +/* NVL-S */
> +#define INTEL_NVLS_IDS(MACRO__, ...) \
> +	MACRO__(0xD740, ## __VA_ARGS__), \
> +	MACRO__(0xD741, ## __VA_ARGS__), \
> +	MACRO__(0xD742, ## __VA_ARGS__), \
> +	MACRO__(0xD743, ## __VA_ARGS__), \
> +	MACRO__(0xD744, ## __VA_ARGS__), \
> +	MACRO__(0xD745, ## __VA_ARGS__)
> +
>   #endif /* __PCIIDS_H__ */
>

Re: [PATCH 16/23] drm/xe/nvls: Attach MOCS table for NVL-S

[Shekhar Chauhan]

On 10/14/2025 8:54, Lucas De Marchi wrote:
> From: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
>
> The MOCS table for NVL-S is the same of Xe2.

Nitpick: Maybe rephrase it to "The MOCS table for NVL-S is the same as 
that of Xe2". Also, can we have the Bspec listed for this, to assist the 
reviewer.

Aside from this, LGTM,

Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>

>
> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_mocs.c | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
> index 7b68c22ff7bbc..e8ec4114302e5 100644
> --- a/drivers/gpu/drm/xe/xe_mocs.c
> +++ b/drivers/gpu/drm/xe/xe_mocs.c
> @@ -576,6 +576,7 @@ static unsigned int get_mocs_settings(struct xe_device *xe,
>   	memset(info, 0, sizeof(struct xe_mocs_info));
>   
>   	switch (xe->info.platform) {
> +	case XE_NOVALAKE_S:
>   	case XE_PANTHERLAKE:
>   	case XE_LUNARLAKE:
>   	case XE_BATTLEMAGE:
>

Re: [PATCH 17/23] drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition

[Shekhar Chauhan]

On 10/14/2025 8:54, Lucas De Marchi wrote:
> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>
> Add support for graphics IP Xe3p_XPC having IP version 35.11.
>
> Bspec: 77979, 77975
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_pci.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index aa8359a4c5594..83e5e0c314a42 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -119,6 +119,15 @@ static const struct xe_graphics_desc graphics_xe2 = {
>   	XE2_GFX_FEATURES,
>   };
>   
> +static const struct xe_graphics_desc graphics_xe3p_xpc = {
> +	XE2_GFX_FEATURES,
> +	.hw_engine_mask =
> +		GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) |

In Bspec, I see the number of RES_COPY_ENGINES as 0, which signals that 
there is no BCS0. But, at the same time, I see SERVICE_COPY_ENGINES as 
0. So, why are we having a mask from BCS1 to BCS8? Maybe I'm 
interpreting the table wrong in some way.

But, aside from this change, other changes look fine, I can provide the 
RB once the above query is clarified.

> +		GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0),
> +	.va_bits = 57,
> +	.has_flat_ccs = false,
> +};
> +
>   static const struct xe_media_desc media_xem = {
>   	.hw_engine_mask =
>   		GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
> @@ -151,6 +160,7 @@ static const struct xe_ip graphics_ips[] = {
>   	{ 3003, "Xe3_LPG", &graphics_xe2 },
>   	{ 3004, "Xe3_LPG", &graphics_xe2 },
>   	{ 3005, "Xe3_LPG", &graphics_xe2 },
> +	{ 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
>   };
>   
>   /* Pre-GMDID Media IPs */
>

Re: [PATCH 21/23] drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs

[Shekhar Chauhan]

On 10/14/2025 8:54, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
>
> The compression overfetch tuning settings only apply to platforms that
> support FlatCCS.  In Xe3p_XPC (and any future IPs that also lack
> compression) some of the registers being adjusted by this tuning will
> not exist or may have been repurposed for something else, so we should
> take care not to try to program them.
>
> Note that our xe_rtp_match_has_flatccs() function will also return false
> on platforms that do have FlatCCS in the hardware design, but have
> compression manually disabled in the BIOS.  On such platforms the
> registers still exist (and it would be fine to continue programming
> them), but they would have no effect, so skipping that tuning is also
> safe.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
The patch in itself looks fine to me, but, the patch doesn't 
specifically play only around Xe3p_XPC. Maybe we can move this patch out 
of the current series, or if we wish to keep it here, can we instead 
drop the xe3p_xpc from the prefix? Thoughts?
> ---
>   drivers/gpu/drm/xe/xe_rtp.c    |  6 ++++++
>   drivers/gpu/drm/xe/xe_rtp.h    | 10 ++++++++++
>   drivers/gpu/drm/xe/xe_tuning.c |  9 ++++++---
>   3 files changed, 22 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
> index b5f430d59f805..22a879270c1ec 100644
> --- a/drivers/gpu/drm/xe/xe_rtp.c
> +++ b/drivers/gpu/drm/xe/xe_rtp.c
> @@ -376,3 +376,9 @@ bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,
>   {
>   	return xe_gt_has_discontiguous_dss_groups(gt);
>   }
> +
> +bool xe_rtp_match_has_flat_ccs(const struct xe_gt *gt,
> +			      const struct xe_hw_engine *hwe)
> +{
> +	return gt_to_xe(gt)->info.has_flat_ccs;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
> index ac12ddf6cde6d..92f0d16110dd5 100644
> --- a/drivers/gpu/drm/xe/xe_rtp.h
> +++ b/drivers/gpu/drm/xe/xe_rtp.h
> @@ -483,4 +483,14 @@ bool xe_rtp_match_psmi_enabled(const struct xe_gt *gt,
>   bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,
>   						  const struct xe_hw_engine *hwe);
>   
> +/**
> + * xe_rtp_match_has_flat_ccs - Match when platform has FlatCCS compression
> + * @gt: GT structure
> + * @hwe: Engine instance
> + *
> + * Returns: true if platform has FlatCCS compression, false otherwise
> + */
> +bool xe_rtp_match_has_flat_ccs(const struct xe_gt *gt,
> +			       const struct xe_hw_engine *hwe);
> +
>   #endif
> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> index fd58ea5e78bf6..7c140d8cb1e07 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.c
> +++ b/drivers/gpu/drm/xe/xe_tuning.c
> @@ -40,7 +40,8 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>   				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
>   	},
>   	{ XE_RTP_NAME("Tuning: Compression Overfetch"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
> +		       FUNC(xe_rtp_match_has_flat_ccs)),
>   	  XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
>   			 SET(CCCHKNREG1, L3CMPCTRL))
>   	},
> @@ -58,12 +59,14 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>   	  XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3, COMPPWOVERFETCHEN))
>   	},
>   	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
> +		       FUNC(xe_rtp_match_has_flat_ccs)),
>   	  XE_RTP_ACTIONS(SET(L3SQCREG2,
>   			     COMPMEMRD256BOVRFETCHEN))
>   	},
>   	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only - media"),
> -	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
> +	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED),
> +		       FUNC(xe_rtp_match_has_flat_ccs)),
>   	  XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
>   			     COMPMEMRD256BOVRFETCHEN))
>   	},
>

Re: [PATCH 17/23] drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition

[Shekhar Chauhan]

On 10/14/2025 13:34, Shekhar Chauhan wrote:
>
> On 10/14/2025 8:54, Lucas De Marchi wrote:
>> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>>
>> Add support for graphics IP Xe3p_XPC having IP version 35.11.
>>
>> Bspec: 77979, 77975
>> Signed-off-by: Balasubramani Vivekanandan 
>> <balasubramani.vivekanandan@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>   drivers/gpu/drm/xe/xe_pci.c | 10 ++++++++++
>>   1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>> index aa8359a4c5594..83e5e0c314a42 100644
>> --- a/drivers/gpu/drm/xe/xe_pci.c
>> +++ b/drivers/gpu/drm/xe/xe_pci.c
>> @@ -119,6 +119,15 @@ static const struct xe_graphics_desc 
>> graphics_xe2 = {
>>       XE2_GFX_FEATURES,
>>   };
>>   +static const struct xe_graphics_desc graphics_xe3p_xpc = {
>> +    XE2_GFX_FEATURES,
>> +    .hw_engine_mask =
>> +        GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) |
>
> In Bspec, I see the number of RES_COPY_ENGINES as 0, which signals 
> that there is no BCS0. But, at the same time, I see 
> SERVICE_COPY_ENGINES as 0. So, why are we having a mask from BCS1 to 
> BCS8? Maybe I'm interpreting the table wrong in some way.
>
> But, aside from this change, other changes look fine, I can provide 
> the RB once the above query is clarified.

Forgot to add the name/signature here, so, for future conversations and 
references, adding it now,

-shekhar

>
>> +        GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0),
>> +    .va_bits = 57,
>> +    .has_flat_ccs = false,
>> +};
>> +
>>   static const struct xe_media_desc media_xem = {
>>       .hw_engine_mask =
>>           GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
>> @@ -151,6 +160,7 @@ static const struct xe_ip graphics_ips[] = {
>>       { 3003, "Xe3_LPG", &graphics_xe2 },
>>       { 3004, "Xe3_LPG", &graphics_xe2 },
>>       { 3005, "Xe3_LPG", &graphics_xe2 },
>> +    { 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
>>   };
>>     /* Pre-GMDID Media IPs */
>>

Re: [PATCH 21/23] drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs

[Shekhar Chauhan]

On 10/14/2025 13:39, Shekhar Chauhan wrote:
>
> On 10/14/2025 8:54, Lucas De Marchi wrote:
>> From: Matt Roper <matthew.d.roper@intel.com>
>>
>> The compression overfetch tuning settings only apply to platforms that
>> support FlatCCS.  In Xe3p_XPC (and any future IPs that also lack
>> compression) some of the registers being adjusted by this tuning will
>> not exist or may have been repurposed for something else, so we should
>> take care not to try to program them.
>>
>> Note that our xe_rtp_match_has_flatccs() function will also return false
>> on platforms that do have FlatCCS in the hardware design, but have
>> compression manually disabled in the BIOS.  On such platforms the
>> registers still exist (and it would be fine to continue programming
>> them), but they would have no effect, so skipping that tuning is also
>> safe.
>>
>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> The patch in itself looks fine to me, but, the patch doesn't 
> specifically play only around Xe3p_XPC. Maybe we can move this patch 
> out of the current series, or if we wish to keep it here, can we 
> instead drop the xe3p_xpc from the prefix? Thoughts?

Forgot to add the name/signature here, apologies, and adding it now for 
future references/conversations,

-shekhar

>> ---
>>   drivers/gpu/drm/xe/xe_rtp.c    |  6 ++++++
>>   drivers/gpu/drm/xe/xe_rtp.h    | 10 ++++++++++
>>   drivers/gpu/drm/xe/xe_tuning.c |  9 ++++++---
>>   3 files changed, 22 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
>> index b5f430d59f805..22a879270c1ec 100644
>> --- a/drivers/gpu/drm/xe/xe_rtp.c
>> +++ b/drivers/gpu/drm/xe/xe_rtp.c
>> @@ -376,3 +376,9 @@ bool 
>> xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,
>>   {
>>       return xe_gt_has_discontiguous_dss_groups(gt);
>>   }
>> +
>> +bool xe_rtp_match_has_flat_ccs(const struct xe_gt *gt,
>> +                  const struct xe_hw_engine *hwe)
>> +{
>> +    return gt_to_xe(gt)->info.has_flat_ccs;
>> +}
>> diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
>> index ac12ddf6cde6d..92f0d16110dd5 100644
>> --- a/drivers/gpu/drm/xe/xe_rtp.h
>> +++ b/drivers/gpu/drm/xe/xe_rtp.h
>> @@ -483,4 +483,14 @@ bool xe_rtp_match_psmi_enabled(const struct 
>> xe_gt *gt,
>>   bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct 
>> xe_gt *gt,
>>                             const struct xe_hw_engine *hwe);
>>   +/**
>> + * xe_rtp_match_has_flat_ccs - Match when platform has FlatCCS 
>> compression
>> + * @gt: GT structure
>> + * @hwe: Engine instance
>> + *
>> + * Returns: true if platform has FlatCCS compression, false otherwise
>> + */
>> +bool xe_rtp_match_has_flat_ccs(const struct xe_gt *gt,
>> +                   const struct xe_hw_engine *hwe);
>> +
>>   #endif
>> diff --git a/drivers/gpu/drm/xe/xe_tuning.c 
>> b/drivers/gpu/drm/xe/xe_tuning.c
>> index fd58ea5e78bf6..7c140d8cb1e07 100644
>> --- a/drivers/gpu/drm/xe/xe_tuning.c
>> +++ b/drivers/gpu/drm/xe/xe_tuning.c
>> @@ -40,7 +40,8 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>>                      REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
>>       },
>>       { XE_RTP_NAME("Tuning: Compression Overfetch"),
>> -      XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 
>> XE_RTP_END_VERSION_UNDEFINED)),
>> +      XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 
>> XE_RTP_END_VERSION_UNDEFINED),
>> +               FUNC(xe_rtp_match_has_flat_ccs)),
>>         XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
>>                SET(CCCHKNREG1, L3CMPCTRL))
>>       },
>> @@ -58,12 +59,14 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>>         XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3, COMPPWOVERFETCHEN))
>>       },
>>       { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
>> -      XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 
>> XE_RTP_END_VERSION_UNDEFINED)),
>> +      XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 
>> XE_RTP_END_VERSION_UNDEFINED),
>> +               FUNC(xe_rtp_match_has_flat_ccs)),
>>         XE_RTP_ACTIONS(SET(L3SQCREG2,
>>                    COMPMEMRD256BOVRFETCHEN))
>>       },
>>       { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only - media"),
>> -      XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, 
>> XE_RTP_END_VERSION_UNDEFINED)),
>> +      XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, 
>> XE_RTP_END_VERSION_UNDEFINED),
>> +               FUNC(xe_rtp_match_has_flat_ccs)),
>>         XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
>>                    COMPMEMRD256BOVRFETCHEN))
>>       },
>>

Re: [PATCH 05/23] drm/xe/xe3p_lpm: Stop reading the CTC_MODE register

[Shekhar Chauhan]

On 10/14/2025 8:54, Lucas De Marchi wrote:
> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>
> CTC_MODE register is removed by Xe3p.  Stop reading that register on
> Xe3p and later platforms.
>
> Bspec: 62395

Again, maybe I'm referencing the Bspec in a wrong way, but I do see this 
register existing for IP 35. Maybe a possible tagging issue in the 
Bspec? Can someone comment here, if I'm missing something.

-shekhar

> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_gt_clock.c | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
> index 4f011d1573c65..26052710be8a7 100644
> --- a/drivers/gpu/drm/xe/xe_gt_clock.c
> +++ b/drivers/gpu/drm/xe/xe_gt_clock.c
> @@ -57,6 +57,10 @@ static void read_crystal_clock(struct xe_gt *gt, u32 rpm_config_reg, u32 *freq,
>   
>   static void check_ctc_mode(struct xe_gt *gt)
>   {
> +	/* CTC_MODE register is removed by Xe3p */
> +	if (GT_VER(gt) >= 35)
> +		return;
> +
>   	/*
>   	 * CTC_MODE[0] = 1 is definitely not supported for Xe2 and later
>   	 * platforms.  In theory it could be a valid setting for pre-Xe2
>

✓ Xe.CI.Full: success for drm/xe: Add Xe3p support

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 72046 bytes --]

== Series Details ==

Series: drm/xe: Add Xe3p support
URL   : https://patchwork.freedesktop.org/series/155866/
State : success

== Summary ==

CI Bug Log - changes from xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada_FULL -> xe-pw-155866v1_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-155866v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_hwmon@hwmon-write:
    - shard-adlp:         NOTRUN -> [SKIP][1] ([Intel XE#1125] / [Intel XE#5574])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-8/igt@intel_hwmon@hwmon-write.html

  * igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [FAIL][2] ([Intel XE#3884]) +1 other test fail
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1.html

  * igt@kms_big_fb@linear-16bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][3] ([Intel XE#1407]) +2 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_big_fb@linear-16bpp-rotate-270.html

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-adlp:         NOTRUN -> [SKIP][4] ([Intel XE#316]) +2 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2328])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-4/igt@kms_big_fb@y-tiled-addfb.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][6] ([Intel XE#619])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-433/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-lnl:          NOTRUN -> [SKIP][7] ([Intel XE#1477])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][8] ([Intel XE#4543]) +10 other tests dmesg-fail
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#1124]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-adlp:         NOTRUN -> [SKIP][10] ([Intel XE#607])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-adlp:         NOTRUN -> [SKIP][11] ([Intel XE#610]) +1 other test skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][12] ([Intel XE#1124]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-432/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-adlp:         NOTRUN -> [SKIP][13] ([Intel XE#1124]) +11 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
    - shard-bmg:          [PASS][14] -> [SKIP][15] ([Intel XE#2314] / [Intel XE#2894]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-3/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html

  * igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
    - shard-adlp:         NOTRUN -> [SKIP][16] ([Intel XE#2191]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-9/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2314] / [Intel XE#2894])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-4/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][18] ([Intel XE#2191])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-433/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-2-displays-1920x1080p:
    - shard-adlp:         NOTRUN -> [SKIP][19] ([Intel XE#367]) +2 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-3-displays-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][20] ([Intel XE#367])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_bw@linear-tiling-3-displays-2160x1440p.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc:
    - shard-adlp:         NOTRUN -> [SKIP][21] ([Intel XE#455] / [Intel XE#787]) +43 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][22] ([Intel XE#455] / [Intel XE#787]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-435/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-c-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][23] ([Intel XE#787]) +6 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-435/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-c-dp-4.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2652] / [Intel XE#787]) +3 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-3/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][25] ([Intel XE#787]) +65 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#2887]) +2 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][27] ([Intel XE#2907])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#2669]) +3 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs@pipe-b-edp-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][29] ([Intel XE#2907])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][30] -> [INCOMPLETE][31] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [PASS][32] -> [INCOMPLETE][33] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-dp-4:
    - shard-dg2-set2:     [PASS][34] -> [INCOMPLETE][35] ([Intel XE#6014] / [Intel XE#6168])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-dp-4.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     [PASS][36] -> [DMESG-WARN][37] ([Intel XE#1727] / [Intel XE#3113])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-6.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-6.html

  * igt@kms_chamelium_color@ctm-negative:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#306]) +1 other test skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_chamelium_color@ctm-negative.html
    - shard-adlp:         NOTRUN -> [SKIP][39] ([Intel XE#306]) +1 other test skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_chamelium_color@ctm-negative.html

  * igt@kms_chamelium_hpd@hdmi-hpd:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#373])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_chamelium_hpd@hdmi-hpd.html

  * igt@kms_chamelium_hpd@hdmi-hpd-after-hibernate:
    - shard-dg2-set2:     NOTRUN -> [SKIP][41] ([Intel XE#373])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-435/igt@kms_chamelium_hpd@hdmi-hpd-after-hibernate.html

  * igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
    - shard-adlp:         NOTRUN -> [SKIP][42] ([Intel XE#373]) +10 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html

  * igt@kms_content_protection@atomic-dpms@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][43] ([Intel XE#1178])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-3/igt@kms_content_protection@atomic-dpms@pipe-a-dp-2.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-adlp:         NOTRUN -> [SKIP][44] ([Intel XE#307]) +1 other test skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-9/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@mei-interface:
    - shard-lnl:          NOTRUN -> [SKIP][45] ([Intel XE#1468])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_content_protection@mei-interface.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-adlp:         NOTRUN -> [SKIP][46] ([Intel XE#308])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-lnl:          NOTRUN -> [SKIP][47] ([Intel XE#1424]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-adlp:         NOTRUN -> [SKIP][48] ([Intel XE#309]) +5 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
    - shard-lnl:          NOTRUN -> [SKIP][49] ([Intel XE#309])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][50] -> [SKIP][51] ([Intel XE#2291]) +7 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-3/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-bmg:          [PASS][52] -> [FAIL][53] ([Intel XE#1475])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-dg2-set2:     NOTRUN -> [SKIP][54] ([Intel XE#323])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-435/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
    - shard-adlp:         NOTRUN -> [SKIP][55] ([Intel XE#323])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-bmg:          [PASS][56] -> [SKIP][57] ([Intel XE#1340])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-2/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dp_aux_dev:
    - shard-adlp:         NOTRUN -> [SKIP][58] ([Intel XE#3009])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@kms_dp_aux_dev.html
    - shard-bmg:          [PASS][59] -> [SKIP][60] ([Intel XE#3009])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-5/igt@kms_dp_aux_dev.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-6/igt@kms_dp_aux_dev.html

  * igt@kms_dp_link_training@uhbr-mst:
    - shard-lnl:          NOTRUN -> [SKIP][61] ([Intel XE#4354])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_dp_link_training@uhbr-mst.html
    - shard-adlp:         NOTRUN -> [SKIP][62] ([Intel XE#4356])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_dp_link_training@uhbr-mst.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-adlp:         NOTRUN -> [SKIP][63] ([Intel XE#4331])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
    - shard-adlp:         NOTRUN -> [SKIP][64] ([Intel XE#4422])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-8/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html

  * igt@kms_feature_discovery@psr1:
    - shard-adlp:         NOTRUN -> [SKIP][65] ([Intel XE#1135])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][66] ([Intel XE#1421]) +1 other test skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
    - shard-adlp:         NOTRUN -> [SKIP][67] ([Intel XE#310]) +4 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-8/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html

  * igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset:
    - shard-bmg:          NOTRUN -> [SKIP][68] ([Intel XE#2316])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-4/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html

  * igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
    - shard-bmg:          [PASS][69] -> [SKIP][70] ([Intel XE#2316]) +2 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-2/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-6/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-lnl:          [PASS][71] -> [FAIL][72] ([Intel XE#301])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a1:
    - shard-adlp:         NOTRUN -> [DMESG-WARN][73] ([Intel XE#4543]) +5 other tests dmesg-warn
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a1.html

  * igt@kms_flip@flip-vs-rmfb-interruptible:
    - shard-adlp:         [PASS][74] -> [DMESG-WARN][75] ([Intel XE#4543] / [Intel XE#5208])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-adlp-9/igt@kms_flip@flip-vs-rmfb-interruptible.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-2/igt@kms_flip@flip-vs-rmfb-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-adlp:         [PASS][76] -> [DMESG-WARN][77] ([Intel XE#4543]) +12 other tests dmesg-warn
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-adlp-6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-2/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-wf_vblank-interruptible:
    - shard-adlp:         [PASS][78] -> [DMESG-WARN][79] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-adlp-2/igt@kms_flip@flip-vs-wf_vblank-interruptible.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@kms_flip@flip-vs-wf_vblank-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling:
    - shard-adlp:         NOTRUN -> [SKIP][80] ([Intel XE#455]) +25 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#1401] / [Intel XE#1745]) +1 other test skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][82] ([Intel XE#1401]) +1 other test skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][83] ([Intel XE#4543] / [Intel XE#4921]) +5 other tests dmesg-fail
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-x:
    - shard-adlp:         [PASS][84] -> [DMESG-FAIL][85] ([Intel XE#4543])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-x.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-x.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-blt:
    - shard-adlp:         NOTRUN -> [SKIP][86] ([Intel XE#651]) +13 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-blt.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][87] ([Intel XE#651]) +3 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-435/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][88] ([Intel XE#2312]) +1 other test skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render:
    - shard-adlp:         NOTRUN -> [SKIP][89] ([Intel XE#656]) +49 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][90] ([Intel XE#651]) +3 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_frontbuffer_tracking@drrs-suspend.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][91] ([Intel XE#2311])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-adlp:         NOTRUN -> [SKIP][92] ([Intel XE#653]) +14 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-move:
    - shard-dg2-set2:     NOTRUN -> [SKIP][93] ([Intel XE#653])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-435/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][94] ([Intel XE#656]) +6 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-lnl:          NOTRUN -> [SKIP][95] ([Intel XE#3374] / [Intel XE#3544])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@static-swap:
    - shard-bmg:          [PASS][96] -> [SKIP][97] ([Intel XE#1503]) +1 other test skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-3/igt@kms_hdr@static-swap.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-6/igt@kms_hdr@static-swap.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-bmg:          [PASS][98] -> [SKIP][99] ([Intel XE#3012])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-3/igt@kms_joiner@basic-force-big-joiner.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-6/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-lnl:          NOTRUN -> [SKIP][100] ([Intel XE#4329])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-adlp:         NOTRUN -> [SKIP][101] ([Intel XE#870])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-bmg:          NOTRUN -> [SKIP][102] ([Intel XE#2392])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-4/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-adlp:         NOTRUN -> [SKIP][103] ([Intel XE#836])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_pm_rpm@universal-planes:
    - shard-adlp:         NOTRUN -> [DMESG-WARN][104] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#5750])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@kms_pm_rpm@universal-planes.html

  * igt@kms_pm_rpm@universal-planes@plane-33:
    - shard-adlp:         NOTRUN -> [DMESG-WARN][105] ([Intel XE#2953] / [Intel XE#4173])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@kms_pm_rpm@universal-planes@plane-33.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-lnl:          NOTRUN -> [SKIP][106] ([Intel XE#1406] / [Intel XE#2893] / [Intel XE#4608])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][107] ([Intel XE#1406] / [Intel XE#4608]) +1 other test skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-b-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
    - shard-dg2-set2:     NOTRUN -> [SKIP][108] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-435/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-adlp:         NOTRUN -> [SKIP][109] ([Intel XE#1406] / [Intel XE#1489]) +10 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-8/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][110] ([Intel XE#1406] / [Intel XE#1489])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-4/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][111] ([Intel XE#1406] / [Intel XE#2893])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-adlp:         NOTRUN -> [SKIP][112] ([Intel XE#1122] / [Intel XE#1406] / [Intel XE#5580])
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-9/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@fbc-pr-cursor-plane-move:
    - shard-lnl:          NOTRUN -> [SKIP][113] ([Intel XE#1406]) +1 other test skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_psr@fbc-pr-cursor-plane-move.html

  * igt@kms_psr@fbc-pr-sprite-render:
    - shard-adlp:         NOTRUN -> [SKIP][114] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +14 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@kms_psr@fbc-pr-sprite-render.html

  * igt@kms_psr@pr-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][115] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +1 other test skip
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-432/igt@kms_psr@pr-dpms.html

  * igt@kms_psr@pr-primary-blt:
    - shard-bmg:          NOTRUN -> [SKIP][116] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-4/igt@kms_psr@pr-primary-blt.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][117] ([Intel XE#1127])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-432/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-adlp:         NOTRUN -> [SKIP][118] ([Intel XE#3414]) +1 other test skip
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_sequence@get-busy:
    - shard-adlp:         [PASS][119] -> [DMESG-WARN][120] ([Intel XE#2953] / [Intel XE#4173]) +9 other tests dmesg-warn
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-adlp-2/igt@kms_sequence@get-busy.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@kms_sequence@get-busy.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-bmg:          [PASS][121] -> [SKIP][122] ([Intel XE#1435])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-2/igt@kms_setmode@invalid-clone-single-crtc.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-4/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-lnl:          NOTRUN -> [SKIP][123] ([Intel XE#330])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@kms_tv_load_detect@load-detect.html
    - shard-adlp:         NOTRUN -> [SKIP][124] ([Intel XE#330])
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@kms_tv_load_detect@load-detect.html

  * igt@xe_ccs@suspend-resume:
    - shard-adlp:         NOTRUN -> [SKIP][125] ([Intel XE#455] / [Intel XE#488] / [Intel XE#5607])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-9/igt@xe_ccs@suspend-resume.html

  * igt@xe_compute@ccs-mode-compute-kernel:
    - shard-adlp:         NOTRUN -> [SKIP][126] ([Intel XE#1447] / [Intel XE#5596])
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-8/igt@xe_compute@ccs-mode-compute-kernel.html

  * igt@xe_compute_preempt@compute-preempt:
    - shard-adlp:         NOTRUN -> [SKIP][127] ([Intel XE#455] / [Intel XE#5632])
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@xe_compute_preempt@compute-preempt.html

  * igt@xe_copy_basic@mem-copy-linear-0xfd:
    - shard-adlp:         NOTRUN -> [SKIP][128] ([Intel XE#1123])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@xe_copy_basic@mem-copy-linear-0xfd.html

  * igt@xe_copy_basic@mem-set-linear-0x369:
    - shard-adlp:         NOTRUN -> [SKIP][129] ([Intel XE#1126])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-8/igt@xe_copy_basic@mem-set-linear-0x369.html

  * igt@xe_eu_stall@blocking-re-enable:
    - shard-dg2-set2:     NOTRUN -> [SKIP][130] ([Intel XE#5626])
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-432/igt@xe_eu_stall@blocking-re-enable.html

  * igt@xe_eudebug@sysfs-toggle:
    - shard-lnl:          NOTRUN -> [SKIP][131] ([Intel XE#4837]) +3 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@xe_eudebug@sysfs-toggle.html

  * igt@xe_eudebug_online@single-step:
    - shard-adlp:         NOTRUN -> [SKIP][132] ([Intel XE#4837] / [Intel XE#5565]) +15 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-8/igt@xe_eudebug_online@single-step.html

  * igt@xe_evict@evict-large-cm:
    - shard-adlp:         NOTRUN -> [SKIP][133] ([Intel XE#261] / [Intel XE#5564]) +3 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-8/igt@xe_evict@evict-large-cm.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-adlp:         NOTRUN -> [SKIP][134] ([Intel XE#261]) +5 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@xe_evict@evict-mixed-many-threads-small.html
    - shard-lnl:          NOTRUN -> [SKIP][135] ([Intel XE#688]) +1 other test skip
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_evict@evict-threads-small:
    - shard-adlp:         NOTRUN -> [SKIP][136] ([Intel XE#261] / [Intel XE#688])
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-8/igt@xe_evict@evict-threads-small.html

  * igt@xe_evict_ccs@evict-overcommit-standalone-nofree-reopen:
    - shard-adlp:         NOTRUN -> [SKIP][137] ([Intel XE#688])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@xe_evict_ccs@evict-overcommit-standalone-nofree-reopen.html

  * igt@xe_exec_balancer@many-execqueues-cm-virtual-userptr-invalidate-race:
    - shard-bmg:          [PASS][138] -> [FAIL][139] ([Intel XE#5625]) +1 other test fail
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-2/igt@xe_exec_balancer@many-execqueues-cm-virtual-userptr-invalidate-race.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-6/igt@xe_exec_balancer@many-execqueues-cm-virtual-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate:
    - shard-adlp:         NOTRUN -> [SKIP][140] ([Intel XE#1392] / [Intel XE#5575]) +11 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_basic@multigpu-no-exec-basic-defer-bind:
    - shard-lnl:          NOTRUN -> [SKIP][141] ([Intel XE#1392]) +1 other test skip
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@xe_exec_basic@multigpu-no-exec-basic-defer-bind.html

  * igt@xe_exec_basic@twice-null-rebind:
    - shard-bmg:          [PASS][142] -> [DMESG-WARN][143] ([Intel XE#3876])
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-2/igt@xe_exec_basic@twice-null-rebind.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-6/igt@xe_exec_basic@twice-null-rebind.html

  * igt@xe_exec_fault_mode@many-bindexecqueue-userptr-imm:
    - shard-adlp:         NOTRUN -> [SKIP][144] ([Intel XE#288] / [Intel XE#5561]) +30 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@xe_exec_fault_mode@many-bindexecqueue-userptr-imm.html

  * igt@xe_exec_fault_mode@many-execqueues-basic:
    - shard-dg2-set2:     NOTRUN -> [SKIP][145] ([Intel XE#288])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-435/igt@xe_exec_fault_mode@many-execqueues-basic.html

  * igt@xe_exec_fault_mode@once-bindexecqueue-userptr-invalidate-imm:
    - shard-bmg:          [PASS][146] -> [FAIL][147] ([Intel XE#6050]) +1 other test fail
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-2/igt@xe_exec_fault_mode@once-bindexecqueue-userptr-invalidate-imm.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-6/igt@xe_exec_fault_mode@once-bindexecqueue-userptr-invalidate-imm.html

  * igt@xe_exec_mix_modes@exec-spinner-interrupted-lr:
    - shard-adlp:         NOTRUN -> [SKIP][148] ([Intel XE#2360])
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-8/igt@xe_exec_mix_modes@exec-spinner-interrupted-lr.html

  * igt@xe_exec_reset@cm-gt-reset:
    - shard-bmg:          [PASS][149] -> [FAIL][150] ([Intel XE#6325])
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-2/igt@xe_exec_reset@cm-gt-reset.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-6/igt@xe_exec_reset@cm-gt-reset.html

  * igt@xe_exec_system_allocator@once-mmap-huge-nomemset:
    - shard-adlp:         NOTRUN -> [SKIP][151] ([Intel XE#4915]) +277 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-8/igt@xe_exec_system_allocator@once-mmap-huge-nomemset.html

  * igt@xe_exec_system_allocator@process-many-execqueues-malloc-busy-nomemset:
    - shard-dg2-set2:     NOTRUN -> [SKIP][152] ([Intel XE#4915]) +18 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-432/igt@xe_exec_system_allocator@process-many-execqueues-malloc-busy-nomemset.html

  * igt@xe_exec_system_allocator@process-many-malloc-bo-unmap:
    - shard-bmg:          [PASS][153] -> [FAIL][154] ([Intel XE#4937] / [Intel XE#5625]) +22 other tests fail
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-2/igt@xe_exec_system_allocator@process-many-malloc-bo-unmap.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-6/igt@xe_exec_system_allocator@process-many-malloc-bo-unmap.html

  * igt@xe_exec_system_allocator@threads-many-large-mmap-huge:
    - shard-lnl:          NOTRUN -> [SKIP][155] ([Intel XE#4943]) +5 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@xe_exec_system_allocator@threads-many-large-mmap-huge.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][156] ([Intel XE#4943])
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-1/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-huge-nomemset.html

  * igt@xe_exec_threads@threads-bal-shared-vm-basic:
    - shard-bmg:          [PASS][157] -> [DMESG-FAIL][158] ([Intel XE#3876])
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-2/igt@xe_exec_threads@threads-bal-shared-vm-basic.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-6/igt@xe_exec_threads@threads-bal-shared-vm-basic.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-dg2-set2:     NOTRUN -> [ABORT][159] ([Intel XE#5466])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-435/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
    - shard-adlp:         NOTRUN -> [ABORT][160] ([Intel XE#5530])
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv:
    - shard-dg2-set2:     [PASS][161] -> [DMESG-WARN][162] ([Intel XE#5893])
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-dg2-434/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-435/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html

  * igt@xe_gt_freq@freq_range_exec:
    - shard-bmg:          [PASS][163] -> [TIMEOUT][164] ([Intel XE#3876]) +1 other test timeout
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-2/igt@xe_gt_freq@freq_range_exec.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-6/igt@xe_gt_freq@freq_range_exec.html

  * igt@xe_live_ktest@xe_bo:
    - shard-adlp:         NOTRUN -> [SKIP][165] ([Intel XE#2229] / [Intel XE#455]) +1 other test skip
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@xe_live_ktest@xe_bo.html

  * igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
    - shard-adlp:         NOTRUN -> [SKIP][166] ([Intel XE#2229])
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html

  * igt@xe_mmap@pci-membarrier:
    - shard-lnl:          NOTRUN -> [SKIP][167] ([Intel XE#5100])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@xe_mmap@pci-membarrier.html
    - shard-adlp:         NOTRUN -> [SKIP][168] ([Intel XE#5100])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@xe_mmap@pci-membarrier.html

  * igt@xe_module_load@force-load:
    - shard-adlp:         NOTRUN -> [SKIP][169] ([Intel XE#378] / [Intel XE#5612])
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@xe_module_load@force-load.html

  * igt@xe_oa@mmio-triggered-reports-read:
    - shard-adlp:         NOTRUN -> [SKIP][170] ([Intel XE#6032])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-9/igt@xe_oa@mmio-triggered-reports-read.html

  * igt@xe_oa@syncs-syncobj-cfg:
    - shard-adlp:         NOTRUN -> [SKIP][171] ([Intel XE#3573]) +6 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-9/igt@xe_oa@syncs-syncobj-cfg.html

  * igt@xe_pat@display-vs-wb-transient:
    - shard-adlp:         NOTRUN -> [SKIP][172] ([Intel XE#1337] / [Intel XE#5572])
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@xe_pat@display-vs-wb-transient.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][173] ([Intel XE#1337])
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-435/igt@xe_pat@display-vs-wb-transient.html

  * igt@xe_pat@pat-index-xe2:
    - shard-adlp:         NOTRUN -> [SKIP][174] ([Intel XE#977])
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@xe_pat@pat-index-xe2.html

  * igt@xe_pm@d3cold-i2c:
    - shard-adlp:         NOTRUN -> [SKIP][175] ([Intel XE#5694])
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@xe_pm@d3cold-i2c.html

  * igt@xe_pm@d3cold-mmap-vram:
    - shard-lnl:          NOTRUN -> [SKIP][176] ([Intel XE#2284] / [Intel XE#366]) +1 other test skip
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@xe_pm@d3cold-mmap-vram.html

  * igt@xe_pm@s2idle-vm-bind-userptr:
    - shard-adlp:         [PASS][177] -> [DMESG-WARN][178] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4504])
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-adlp-2/igt@xe_pm@s2idle-vm-bind-userptr.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@xe_pm@s2idle-vm-bind-userptr.html

  * igt@xe_pm@s3-d3cold-basic-exec:
    - shard-adlp:         NOTRUN -> [SKIP][179] ([Intel XE#2284] / [Intel XE#366]) +1 other test skip
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@xe_pm@s3-d3cold-basic-exec.html

  * igt@xe_pm@vram-d3cold-threshold:
    - shard-adlp:         NOTRUN -> [SKIP][180] ([Intel XE#5611] / [Intel XE#579])
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@xe_pm@vram-d3cold-threshold.html

  * igt@xe_pmu@fn-engine-activity-load:
    - shard-dg2-set2:     NOTRUN -> [SKIP][181] ([Intel XE#4650])
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-435/igt@xe_pmu@fn-engine-activity-load.html

  * igt@xe_pxp@display-pxp-fb:
    - shard-bmg:          NOTRUN -> [SKIP][182] ([Intel XE#4733])
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-1/igt@xe_pxp@display-pxp-fb.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-suspend:
    - shard-adlp:         NOTRUN -> [SKIP][183] ([Intel XE#4733] / [Intel XE#5594]) +3 other tests skip
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-8/igt@xe_pxp@pxp-stale-bo-exec-post-suspend.html

  * igt@xe_query@multigpu-query-config:
    - shard-lnl:          NOTRUN -> [SKIP][184] ([Intel XE#944])
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@xe_query@multigpu-query-config.html

  * igt@xe_query@multigpu-query-uc-fw-version-huc:
    - shard-adlp:         NOTRUN -> [SKIP][185] ([Intel XE#944]) +1 other test skip
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-9/igt@xe_query@multigpu-query-uc-fw-version-huc.html

  * igt@xe_render_copy@render-stress-4-copies:
    - shard-adlp:         NOTRUN -> [SKIP][186] ([Intel XE#4814] / [Intel XE#5614]) +1 other test skip
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-8/igt@xe_render_copy@render-stress-4-copies.html

  * igt@xe_sriov_scheduling@equal-throughput:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][187] ([Intel XE#3868] / [Intel XE#5213]) +1 other test dmesg-fail
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-1/igt@xe_sriov_scheduling@equal-throughput.html
    - shard-lnl:          NOTRUN -> [SKIP][188] ([Intel XE#4351])
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-3/igt@xe_sriov_scheduling@equal-throughput.html

  
#### Possible fixes ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][189] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168]) -> [PASS][190]
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [INCOMPLETE][191] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#6168]) -> [PASS][192]
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-d-hdmi-a-6.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-d-hdmi-a-6.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-bmg:          [SKIP][193] ([Intel XE#2291]) -> [PASS][194] +8 other tests pass
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-flip-vs-modeset-vs-hang:
    - shard-bmg:          [SKIP][195] ([Intel XE#2316]) -> [PASS][196] +10 other tests pass
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-4/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-3/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [FAIL][197] ([Intel XE#301]) -> [PASS][198]
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-rmfb:
    - shard-adlp:         [DMESG-WARN][199] ([Intel XE#4543] / [Intel XE#5208]) -> [PASS][200]
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-adlp-8/igt@kms_flip@flip-vs-rmfb.html
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-8/igt@kms_flip@flip-vs-rmfb.html

  * igt@kms_flip@flip-vs-rmfb@b-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][201] ([Intel XE#4543]) -> [PASS][202] +4 other tests pass
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-adlp-8/igt@kms_flip@flip-vs-rmfb@b-hdmi-a1.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-8/igt@kms_flip@flip-vs-rmfb@b-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-bmg:          [INCOMPLETE][203] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][204] +1 other test pass
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-3/igt@kms_flip@flip-vs-suspend-interruptible.html
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-4/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-bmg:          [SKIP][205] ([Intel XE#1503]) -> [PASS][206]
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-6/igt@kms_hdr@invalid-metadata-sizes.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-1/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-bmg:          [SKIP][207] ([Intel XE#3012]) -> [PASS][208]
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-4/igt@kms_joiner@invalid-modeset-force-big-joiner.html
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-3/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-bmg:          [SKIP][209] ([Intel XE#4596]) -> [PASS][210] +1 other test pass
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-4.html
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-1/igt@kms_plane_multiple@2x-tiling-4.html

  * {igt@xe_pmu@fn-engine-activity-sched-if-idle@engine-drm_xe_engine_class_video_enhance1}:
    - shard-bmg:          [DMESG-WARN][211] ([Intel XE#3876]) -> [PASS][212] +1 other test pass
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-6/igt@xe_pmu@fn-engine-activity-sched-if-idle@engine-drm_xe_engine_class_video_enhance1.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-1/igt@xe_pmu@fn-engine-activity-sched-if-idle@engine-drm_xe_engine_class_video_enhance1.html

  
#### Warnings ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][213] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168]) -> [INCOMPLETE][214] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522])
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-bmg:          [SKIP][215] ([Intel XE#2341]) -> [FAIL][216] ([Intel XE#1178])
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-4/igt@kms_content_protection@atomic-dpms.html
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-3/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@legacy:
    - shard-bmg:          [FAIL][217] ([Intel XE#1178]) -> [SKIP][218] ([Intel XE#2341]) +1 other test skip
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-2/igt@kms_content_protection@legacy.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-6/igt@kms_content_protection@legacy.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-y:
    - shard-adlp:         [DMESG-FAIL][219] ([Intel XE#4543]) -> [FAIL][220] ([Intel XE#1874])
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-y.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-y.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][221] ([Intel XE#2311]) -> [SKIP][222] ([Intel XE#2312]) +18 other tests skip
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-adlp:         [DMESG-FAIL][223] ([Intel XE#4543]) -> [DMESG-FAIL][224] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543])
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-adlp-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-adlp-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          [SKIP][225] ([Intel XE#2312]) -> [SKIP][226] ([Intel XE#5390]) +10 other tests skip
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-bmg:          [SKIP][227] ([Intel XE#5390]) -> [SKIP][228] ([Intel XE#2312]) +8 other tests skip
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][229] ([Intel XE#2312]) -> [SKIP][230] ([Intel XE#2311]) +21 other tests skip
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
    - shard-bmg:          [SKIP][231] ([Intel XE#2312]) -> [SKIP][232] ([Intel XE#2313]) +20 other tests skip
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][233] ([Intel XE#2313]) -> [SKIP][234] ([Intel XE#2312]) +19 other tests skip
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][235] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][236] ([Intel XE#3544])
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-4/igt@kms_hdr@brightness-with-hdr.html
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][237] ([Intel XE#2426]) -> [SKIP][238] ([Intel XE#2509])
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
    - shard-dg2-set2:     [SKIP][239] ([Intel XE#1500]) -> [SKIP][240] ([Intel XE#362])
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-dg2-436/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_pm@d3hot-i2c:
    - shard-bmg:          [SKIP][241] ([Intel XE#5742]) -> [TIMEOUT][242] ([Intel XE#3876] / [Intel XE#6162])
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-2/igt@xe_pm@d3hot-i2c.html
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/shard-bmg-6/igt@xe_pm@d3hot-i2c.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
  [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1337
  [Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1447
  [Intel XE#1468]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1468
  [Intel XE#1475]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1475
  [Intel XE#1477]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1477
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
  [Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#3009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3009
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
  [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
  [Intel XE#3884]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3884
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4329
  [Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4351
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4356
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4504
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4814
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/488
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4921]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4921
  [Intel XE#4937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4937
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5213]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5213
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
  [Intel XE#5503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5503
  [Intel XE#5530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5530
  [Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
  [Intel XE#5564]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5564
  [Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
  [Intel XE#5572]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5572
  [Intel XE#5574]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5574
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#5580]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5580
  [Intel XE#5594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5594
  [Intel XE#5596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5596
  [Intel XE#5607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5607
  [Intel XE#5611]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5611
  [Intel XE#5612]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5612
  [Intel XE#5614]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5614
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
  [Intel XE#5632]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5632
  [Intel XE#5694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5694
  [Intel XE#5742]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5742
  [Intel XE#5750]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5750
  [Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
  [Intel XE#5893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5893
  [Intel XE#6011]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6011
  [Intel XE#6014]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6014
  [Intel XE#6032]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6032
  [Intel XE#6050]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6050
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#6162]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6162
  [Intel XE#6168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6168
  [Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6320
  [Intel XE#6325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6325
  [Intel XE#6326]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6326
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977


Build changes
-------------

  * Linux: xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada -> xe-pw-155866v1

  IGT_8582: 8582
  xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada: c917f7d11493984be9f381ca0a7667bd3e587ada
  xe-pw-155866v1: 155866v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155866v1/index.html

[-- Attachment #2: Type: text/html, Size: 86081 bytes --]

Re: [PATCH 12/23] drm/xe/xe3p: Flush userptr/shrinker bo cachelines manually

[Thomas Hellström]

Hi,

On Mon, 2025-10-13 at 20:24 -0700, Lucas De Marchi wrote:
> From: Tejas Upadhyay <tejas.upadhyay@intel.com>
> 
> Starting with Xe3p, HW will flush cachelines marked with XA only when
> media is off. We have few cases where kernel will have non-XA
> cachelines
> which needs manual flush as we postpone the invalidation.

is XA- and non-XA cachelines described somewhere in the code?

> 
> Flush asap from correctness POV to ensure non accelerated CPU copy to
> swap/shmem file will see coherent view of memory, but also from
> security
> POV where later flush can't corrupt the next user of those pages.
> 
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> [ TODO: xe_device_needs_cache_flush() seems a bad name that doesn't
>   really review the context - it may need to be renamed/localized ]
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

This worries me. Any dma-fence *must*, when signaled, have flushed all
caches from data resulting from the operation it marks the completion
of. The code below indicates that's not the case?

Note also that the wait for idle in xe_bo_trigger_rebind does not
guarantee that the bo is idle, just that there are no pending bind
operations.

In fault mode we have a slightly different approach to ensure data is
flushed before pages are released.

Could you elaborate a bit on how this is intendend to work.

Thanks,
Thomas


> ---
>  drivers/gpu/drm/xe/xe_bo.c      |  3 ++-
>  drivers/gpu/drm/xe/xe_device.c  | 20 ++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_device.h  |  1 +
>  drivers/gpu/drm/xe/xe_userptr.c |  3 ++-
>  4 files changed, 25 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
> index 7b65020818738..05bc61d9e37cf 100644
> --- a/drivers/gpu/drm/xe/xe_bo.c
> +++ b/drivers/gpu/drm/xe/xe_bo.c
> @@ -673,7 +673,8 @@ static int xe_bo_trigger_rebind(struct xe_device
> *xe, struct xe_bo *bo,
>  
>  		if (!xe_vm_in_fault_mode(vm)) {
>  			drm_gpuvm_bo_evict(vm_bo, true);
> -			continue;
> +			if (!xe_device_needs_cache_flush(xe))
> +				continue;
>  		}
>  
>  		if (!idle) {
> diff --git a/drivers/gpu/drm/xe/xe_device.c
> b/drivers/gpu/drm/xe/xe_device.c
> index 7efa8da9e1069..168a45fe36838 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -1081,6 +1081,26 @@ void xe_device_l2_flush(struct xe_device *xe)
>  	xe_force_wake_put(gt_to_fw(gt), fw_ref);
>  }
>  
> +/**
> + * xe_device_needs_cache_flush - Whether the cache needs to be
> flushed
> + * @xe: The device to check.
> + *
> + * Return: true if the device needs cache flush, false otherwise.
> + */
> +bool xe_device_needs_cache_flush(struct xe_device *xe)
> +{
> +	/*
> +	 * Xe3p will flush cachelines marked with XA only when media
> is off. We
> +	 * have few cases where kernel will have non-XA cachelines
> which needs
> +	 * manual flush and this is one of them as we postpone the
> +	 * invalidation. Flush asap from correctness POV to ensure
> non
> +	 * accelerated CPU copy to swap/shmem file will see coherent
> view of
> +	 * memory, but also from security POV where later flush
> can't corrupt
> +	 * the next user of those pages.
> +	 */
> +	return GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe);
> +}
> +
>  /**
>   * xe_device_td_flush() - Flush transient L3 cache entries
>   * @xe: The device
> diff --git a/drivers/gpu/drm/xe/xe_device.h
> b/drivers/gpu/drm/xe/xe_device.h
> index 32cc6323b7f64..15e67db44b56c 100644
> --- a/drivers/gpu/drm/xe/xe_device.h
> +++ b/drivers/gpu/drm/xe/xe_device.h
> @@ -179,6 +179,7 @@ void xe_device_snapshot_print(struct xe_device
> *xe, struct drm_printer *p);
>  u64 xe_device_canonicalize_addr(struct xe_device *xe, u64 address);
>  u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64
> address);
>  
> +bool xe_device_needs_cache_flush(struct xe_device *xe);
>  void xe_device_td_flush(struct xe_device *xe);
>  void xe_device_l2_flush(struct xe_device *xe);
>  
> diff --git a/drivers/gpu/drm/xe/xe_userptr.c
> b/drivers/gpu/drm/xe/xe_userptr.c
> index f16e92cd80904..86ce1c3ef41aa 100644
> --- a/drivers/gpu/drm/xe/xe_userptr.c
> +++ b/drivers/gpu/drm/xe/xe_userptr.c
> @@ -112,7 +112,8 @@ static void __vma_userptr_invalidate(struct xe_vm
> *vm, struct xe_userptr_vma *uv
>  				    false, MAX_SCHEDULE_TIMEOUT);
>  	XE_WARN_ON(err <= 0);
>  
> -	if (xe_vm_in_fault_mode(vm) && userptr->initial_bind) {
> +	if ((xe_vm_in_fault_mode(vm) ||
> xe_device_needs_cache_flush(vm->xe)) &&
> +	    userptr->initial_bind) {
>  		err = xe_vm_invalidate_vma(vma);
>  		XE_WARN_ON(err);
>  	}
> 

Re: [PATCH 01/23] drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05

[Matt Roper]

On Mon, Oct 13, 2025 at 08:24:33PM -0700, Lucas De Marchi wrote:
> From: Shekhar Chauhan <shekhar.chauhan@intel.com>
> 
> Add graphics IP versions 30.04 & 30.05 and initial workarounds for these
> IP versions.
> 
> BSpec: 74201
> Cc: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
> Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_pci.c        | 2 ++
>  drivers/gpu/drm/xe/xe_wa.c         | 6 +++---
>  drivers/gpu/drm/xe/xe_wa_oob.rules | 7 +++++--
>  3 files changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 944c698808ace..c1e89689953b7 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -149,6 +149,8 @@ static const struct xe_ip graphics_ips[] = {
>  	{ 3000, "Xe3_LPG", &graphics_xe2 },
>  	{ 3001, "Xe3_LPG", &graphics_xe2 },
>  	{ 3003, "Xe3_LPG", &graphics_xe2 },
> +	{ 3004, "Xe3_LPG", &graphics_xe2 },
> +	{ 3005, "Xe3_LPG", &graphics_xe2 },
>  };
>  
>  /* Pre-GMDID Media IPs */
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index c60159a130014..24b6d4bb0b962 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -684,7 +684,7 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  	},
>  	{ XE_RTP_NAME("13012615864"),
>  	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), OR,
> -		       GRAPHICS_VERSION(3003),
> +		       GRAPHICS_VERSION_RANGE(3003, 3005),
>  		       FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
>  	},
> @@ -695,7 +695,7 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
>  	},
>  	{ XE_RTP_NAME("14021402888"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION(3003), FUNC(xe_rtp_match_first_render_or_compute)),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3003, 3005), FUNC(xe_rtp_match_first_render_or_compute)),
>  	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
>  	},
>  	{ XE_RTP_NAME("18041344222"),
> @@ -913,7 +913,7 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  			     DIS_AUTOSTRIP))
>  	},
>  	{ XE_RTP_NAME("22021007897"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3003), ENGINE_CLASS(RENDER)),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3005), ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
>  	},
>  };
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index f3a6d5d239cec..9aff2e56fd3e4 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -34,14 +34,17 @@
>  13011645652	GRAPHICS_VERSION(2004)
>  		GRAPHICS_VERSION_RANGE(3000, 3001)
>  		GRAPHICS_VERSION(3003)
> +		GRAPHICS_VERSION_RANGE(3004, 3005)

As Shekhar pointed out, 30.04/30.05 can be combined with the 30.03 line
for all of these.

Otherwise,

        Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

>  14022293748	GRAPHICS_VERSION_RANGE(2001, 2002)
>  		GRAPHICS_VERSION(2004)
>  		GRAPHICS_VERSION_RANGE(3000, 3001)
>  		GRAPHICS_VERSION(3003)
> +		GRAPHICS_VERSION_RANGE(3004, 3005)
>  22019794406	GRAPHICS_VERSION_RANGE(2001, 2002)
>  		GRAPHICS_VERSION(2004)
>  		GRAPHICS_VERSION_RANGE(3000, 3001)
>  		GRAPHICS_VERSION(3003)
> +		GRAPHICS_VERSION_RANGE(3004, 3005)
>  22019338487	MEDIA_VERSION(2000)
>  		GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_not_sriov_vf)
>  		MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), FUNC(xe_rtp_match_not_sriov_vf)
> @@ -63,11 +66,11 @@
>  16023105232	GRAPHICS_VERSION_RANGE(2001, 3001)
>  		MEDIA_VERSION_RANGE(1301, 3000)
>  		MEDIA_VERSION(3002)
> -		GRAPHICS_VERSION(3003)
> +		GRAPHICS_VERSION_RANGE(3003, 3005)
>  16026508708	GRAPHICS_VERSION_RANGE(1200, 3001)
>  		MEDIA_VERSION_RANGE(1300, 3000)
>  		MEDIA_VERSION(3002)
> -		GRAPHICS_VERSION(3003)
> +		GRAPHICS_VERSION_RANGE(3003, 3005)
>  14020001231	GRAPHICS_VERSION_RANGE(2001,2004), FUNC(xe_rtp_match_psmi_enabled)
>  		MEDIA_VERSION(2000), FUNC(xe_rtp_match_psmi_enabled)
>  		MEDIA_VERSION(3000), FUNC(xe_rtp_match_psmi_enabled)
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 02/23] drm/xe/xe3p_lpm: Add support for media IP versions 35.00 & 35.03

[Matt Roper]

On Mon, Oct 13, 2025 at 08:24:34PM -0700, Lucas De Marchi wrote:
> From: Shekhar Chauhan <shekhar.chauhan@intel.com>
> 
> Xe3p_LPM is very similar to Xe3_LPM on the kmd interface, so it can use
> the same descriptor structure. Add both 35.00 and 35.03 IP versions.
> 
> BSpec: 74201, 74202, 77977

Should page 77979 also be included in this list since that's where the
35.03 number is actually documented?

Otherwise,

        Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_pci.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index c1e89689953b7..8480e53990031 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -164,6 +164,8 @@ static const struct xe_ip media_ips[] = {
>  	{ 2000, "Xe2_LPM", &media_xelpmp },
>  	{ 3000, "Xe3_LPM", &media_xelpmp },
>  	{ 3002, "Xe3_LPM", &media_xelpmp },
> +	{ 3500, "Xe3p_LPM", &media_xelpmp },
> +	{ 3503, "Xe3p_LPM", &media_xelpmp },
>  };
>  
>  static const struct xe_device_desc tgl_desc = {
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 03/23] drm/xe/xe3p_lpm: Configure MAIN_GAMCTRL_QUEUE_SELECT

[Matt Roper]

On Mon, Oct 13, 2025 at 08:24:35PM -0700, Lucas De Marchi wrote:
> From: Brian Welty <brian.welty@intel.com>
> 
> Starting from Xe3p, there are two different copies of some of the GAM
> registers:  the traditional MCR variant at their old locations, and a
> new unicast copy known as "main_gamctrl."  The Xe driver doesn't use
> these registers directly, but we need to instruct the GuC on which set
> it should use.  Since the new, unicast registers are preferred (since
> they avoid the need for unnecessary MCR synchronization), set a new GuC
> feature flag, GUC_CTL_MAIN_GAMCTRL_QUEUES to convey this decision.  A
> new helper function, xe_guc_using_main_gamctrl_queues(), is added for
> use in the 3 independent places that need to handle configuration of the
> new reporting queues.
> 
> The mmio write to enable the main gamctl is only done during the general
> GuC upload.  The gamctrl registers are not accessed by the GuC during
> hwconfig load.
> 
> Last, the ADS blob for communicating the queue addresses contains both a
> DPA and GGTT offset. The GuC documentation states that DPA is now MBZ
> when using the MAIN_GAMCTRL queues.
> 
> Signed-off-by: Brian Welty <brian.welty@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  3 +++
>  drivers/gpu/drm/xe/xe_gt.h           |  6 ++++++
>  drivers/gpu/drm/xe/xe_guc.c          | 27 +++++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_guc.h          |  1 +
>  drivers/gpu/drm/xe/xe_guc_ads.c      |  6 +++++-
>  drivers/gpu/drm/xe/xe_guc_fwif.h     |  1 +
>  6 files changed, 43 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 51f2a03847f9d..47e13a3fb9072 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -545,6 +545,9 @@
>  #define SARB_CHICKEN1				XE_REG_MCR(0xe90c)
>  #define   COMP_CKN_IN				REG_GENMASK(30, 29)
>  
> +#define MAIN_GAMCTRL_MODE			XE_REG(0xef00)
> +#define   MAIN_GAMCTRL_QUEUE_SELECT		REG_BIT(0)
> +
>  #define RCU_MODE				XE_REG(0x14800, XE_REG_OPTION_MASKED)
>  #define   RCU_MODE_FIXED_SLICE_CCS_MODE		REG_BIT(1)
>  #define   RCU_MODE_CCS_ENABLE			REG_BIT(0)
> diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h
> index 5df2ffe3ff838..9d710049da455 100644
> --- a/drivers/gpu/drm/xe/xe_gt.h
> +++ b/drivers/gpu/drm/xe/xe_gt.h
> @@ -22,6 +22,12 @@
>  
>  #define CCS_MASK(gt) (((gt)->info.engine_mask & XE_HW_ENGINE_CCS_MASK) >> XE_HW_ENGINE_CCS0)
>  
> +#define GT_VER(gt) ({ \
> +	typeof(gt) gt_ = (gt); \
> +	struct xe_device *xe = gt_to_xe(gt_); \
> +	xe_gt_is_media_type(gt_) ? MEDIA_VER(xe) : GRAPHICS_VER(xe); \
> +})
> +
>  extern struct fault_attr gt_reset_failure;
>  static inline bool xe_fault_inject_gt_reset(void)
>  {
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index d94490979adc0..37e3735f34e63 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -91,6 +91,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
>  	if (xe_configfs_get_psmi_enabled(to_pci_dev(xe->drm.dev)))
>  		flags |= GUC_CTL_ENABLE_PSMI_LOGGING;
>  
> +	if (xe_guc_using_main_gamctrl_queues(guc))
> +		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
> +
>  	return flags;
>  }
>  
> @@ -1255,8 +1258,13 @@ int xe_guc_min_load_for_hwconfig(struct xe_guc *guc)
>  
>  int xe_guc_upload(struct xe_guc *guc)
>  {
> +	struct xe_gt *gt = guc_to_gt(guc);
> +
>  	xe_guc_ads_populate(&guc->ads);
>  
> +	if (xe_guc_using_main_gamctrl_queues(guc))
> +		xe_mmio_write32(&gt->mmio, MAIN_GAMCTRL_MODE, MAIN_GAMCTRL_QUEUE_SELECT);
> +
>  	return __xe_guc_upload(guc);
>  }
>  
> @@ -1657,6 +1665,25 @@ void xe_guc_declare_wedged(struct xe_guc *guc)
>  	xe_guc_submit_wedge(guc);
>  }
>  
> +/**
> + * xe_guc_using_main_gamctrl_queues() - Detect which reporting queues to use.
> + * @guc: The GuC object
> + *
> + * For Xe3p and beyond, we want to program the hardware to use the
> + * "Main GAMCTRL queue" rather than the legacy queue before we upload
> + * the GuC firmware.  This will allow the GuC to use a new set of
> + * registers for pagefault handling and avoid some unnecessary
> + * complications with MCR register range handling.
> + *
> + * Return: true if can use new main gamctrl queues.
> + */
> +bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc)
> +{
> +	struct xe_gt *gt = guc_to_gt(guc);
> +
> +	return GT_VER(gt) >= 35;

Revisiting the spec on this, I'm not sure whether using GT_VER() here is
actually the right thing to do.  As far as I can see, the media GT does
not actually have a "main gamctrl" register range at all (i.e., bspec
76445 only lists MCR gamctrl ranges, and 0x38EF00-0x38EFFF falls within
a reserved/unused block).  That means that registers like
MAIN_GAMCTRL_MODE that we're trying to write during xe_guc_upload above
don't actually exist for the media GT.  Furthermore, the tagging on the
register detail page 73540 also seems to imply that this only applies to
the primary/graphics GT.


Matt

> +}
> +
>  #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
>  #include "tests/xe_guc_g2g_test.c"
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h
> index 1cca05967e621..e2d4c5f44ae34 100644
> --- a/drivers/gpu/drm/xe/xe_guc.h
> +++ b/drivers/gpu/drm/xe/xe_guc.h
> @@ -52,6 +52,7 @@ void xe_guc_stop_prepare(struct xe_guc *guc);
>  void xe_guc_stop(struct xe_guc *guc);
>  int xe_guc_start(struct xe_guc *guc);
>  void xe_guc_declare_wedged(struct xe_guc *guc);
> +bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc);
>  
>  #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
>  int xe_guc_g2g_test_notification(struct xe_guc *guc, u32 *payload, u32 len);
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index 22ac2a8b74c80..bcb85a1bf26d9 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -820,16 +820,20 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
>  static void guc_um_init_params(struct xe_guc_ads *ads)
>  {
>  	u32 um_queue_offset = guc_ads_um_queues_offset(ads);
> +	struct xe_guc *guc = ads_to_guc(ads);
>  	u64 base_dpa;
>  	u32 base_ggtt;
> +	bool with_dpa;
>  	int i;
>  
> +	with_dpa = !xe_guc_using_main_gamctrl_queues(guc);
> +
>  	base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset;
>  	base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset;
>  
>  	for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) {
>  		ads_blob_write(ads, um_init_params.queue_params[i].base_dpa,
> -			       base_dpa + (i * GUC_UM_QUEUE_SIZE));
> +			       with_dpa ? (base_dpa + (i * GUC_UM_QUEUE_SIZE)) : 0);
>  		ads_blob_write(ads, um_init_params.queue_params[i].base_ggtt_address,
>  			       base_ggtt + (i * GUC_UM_QUEUE_SIZE));
>  		ads_blob_write(ads, um_init_params.queue_params[i].size_in_bytes,
> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
> index 50c4c2406132e..c90dd266e9cf9 100644
> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> @@ -113,6 +113,7 @@ struct guc_update_exec_queue_policy {
>  #define   GUC_CTL_ENABLE_SLPC		BIT(2)
>  #define   GUC_CTL_ENABLE_LITE_RESTORE	BIT(4)
>  #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
> +#define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
>  #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
>  
>  #define GUC_CTL_DEBUG			3
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 04/23] drm/xe/xe3p_lpm: Add special check in Media GT for Main GAMCTRL

[Matt Roper]

On Mon, Oct 13, 2025 at 08:24:36PM -0700, Lucas De Marchi wrote:
> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> 
> For Xe3p arch some subunits of an IP may be different. The GMD_ID
> register returns the Xe3p arch and dedicates the reserved field to mark
> possible subunit differences. Generally this is an under-the-hood
> implementation detail that drivers don't need to worry about, but the
> new Main_GAMCTRL may be enabled or not depending on those.
> 
> Those reserved bits are described for Xe3p as: "If Zero, No special case
> to be handled. If Non-Zero, special case to be handled by Software
> agent.". That special case is defined per Arch. So if media version is
> 35, also check the additional reserved bits. To avoid confusion with the
> usual meaning of "reserved", define them as GMD_ID_SUBIP_FLAG_MASK.
> 
> Bspec: 74201
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  6 ++++++
>  drivers/gpu/drm/xe/xe_guc.c          | 19 +++++++++++++++++++
>  2 files changed, 25 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 47e13a3fb9072..937dc341abe5e 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -37,6 +37,12 @@
>  #define GMD_ID					XE_REG(0xd8c)
>  #define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
>  #define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
> +/*
> + * Spec defines these bits as "Reserved", but then make them assume some
> + * meaning that depends on the ARCH. To avoid any confusion, call them
> + * SUBIP_FLAG_MASK.
> + */
> +#define   GMD_ID_SUBIP_FLAG_MASK		REG_GENMASK(13, 6)
>  #define   GMD_ID_REVID				REG_GENMASK(5, 0)
>  
>  #define FORCEWAKE_ACK_GSC			XE_REG(0xdf8)
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 37e3735f34e63..ecc3e091b89e6 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -1681,6 +1681,25 @@ bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc)
>  {
>  	struct xe_gt *gt = guc_to_gt(guc);
>  
> +	/*
> +	 * For Xe3p media gt (35), the GuC and the CS subunits may be still Xe3
> +	 * that lacks the Main GAMCTRL support. Reserved bits from the GMD_ID
> +	 * inform the IP version of the subunits.

See feedback on previous patch; I think it may turn out to be the case
that main gamctrl doesn't exist for the media GT even for the cases
where GuC and CS subunits are fully Xe3p.  If so, we may be able to drop
this patch.


Matt

> +	 */
> +	if (xe_gt_is_media_type(gt) && MEDIA_VER(gt_to_xe(gt)) == 35) {
> +		u32 val = xe_mmio_read32(&gt->mmio, GMD_ID);
> +		u32 subip = REG_FIELD_GET(GMD_ID_SUBIP_FLAG_MASK, val);
> +
> +		if (!subip)
> +			return true;
> +
> +		xe_gt_WARN(gt, subip != 1,
> +			   "GMD_ID has unknown value in the SUBIP_FLAG field - 0x%x\n",
> +			   subip);
> +
> +		return false;
> +	}
> +
>  	return GT_VER(gt) >= 35;
>  }
>  
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 05/23] drm/xe/xe3p_lpm: Stop reading the CTC_MODE register

[Matt Roper]

On Mon, Oct 13, 2025 at 08:24:37PM -0700, Lucas De Marchi wrote:
> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> 
> CTC_MODE register is removed by Xe3p.  Stop reading that register on
> Xe3p and later platforms.
> 
> Bspec: 62395
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_gt_clock.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
> index 4f011d1573c65..26052710be8a7 100644
> --- a/drivers/gpu/drm/xe/xe_gt_clock.c
> +++ b/drivers/gpu/drm/xe/xe_gt_clock.c
> @@ -57,6 +57,10 @@ static void read_crystal_clock(struct xe_gt *gt, u32 rpm_config_reg, u32 *freq,
>  
>  static void check_ctc_mode(struct xe_gt *gt)
>  {
> +	/* CTC_MODE register is removed by Xe3p */
> +	if (GT_VER(gt) >= 35)
> +		return;
> +
>  	/*
>  	 * CTC_MODE[0] = 1 is definitely not supported for Xe2 and later
>  	 * platforms.  In theory it could be a valid setting for pre-Xe2
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 05/23] drm/xe/xe3p_lpm: Stop reading the CTC_MODE register

[Matt Roper]

On Tue, Oct 14, 2025 at 05:28:48PM +0530, Shekhar Chauhan wrote:
> 
> On 10/14/2025 8:54, Lucas De Marchi wrote:
> > From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > 
> > CTC_MODE register is removed by Xe3p.  Stop reading that register on
> > Xe3p and later platforms.
> > 
> > Bspec: 62395
> 
> Again, maybe I'm referencing the Bspec in a wrong way, but I do see this
> register existing for IP 35. Maybe a possible tagging issue in the Bspec?
> Can someone comment here, if I'm missing something.

So looking a bit closer based on your comment, I think maybe this should
actually be a GRAPHICS_VER() test rather than a GT_VER() test.  It gets
a bit confusing since the bspec website still tries to print stuff out
in a platform-based manner, which makes it hard to follow exactly which
IP versions and GTs are actually relevant.  In this case the first
REMOVEDBY() tag listed is what documents the removal of the CTC_MODE
register, but it appears that tag only applies to primary GT; the media
GT is not included by the change referenced.  And then if you look
through the jumble of platform names that come after that, it does
indeed appear that media is still listed as having the register, but the
primary GT no longer appears in the list for platforms with Xe3p IP.

So maybe this is another case where we should be using GRAPHICS_VER
instead of GT_VER.  I'm not sure it really matters too much though since
we don't actually use the register for anything, except to complain
about a condition we expect to never show up.


Matt

> 
> -shekhar
> 
> > Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> >   drivers/gpu/drm/xe/xe_gt_clock.c | 4 ++++
> >   1 file changed, 4 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
> > index 4f011d1573c65..26052710be8a7 100644
> > --- a/drivers/gpu/drm/xe/xe_gt_clock.c
> > +++ b/drivers/gpu/drm/xe/xe_gt_clock.c
> > @@ -57,6 +57,10 @@ static void read_crystal_clock(struct xe_gt *gt, u32 rpm_config_reg, u32 *freq,
> >   static void check_ctc_mode(struct xe_gt *gt)
> >   {
> > +	/* CTC_MODE register is removed by Xe3p */
> > +	if (GT_VER(gt) >= 35)
> > +		return;
> > +
> >   	/*
> >   	 * CTC_MODE[0] = 1 is definitely not supported for Xe2 and later
> >   	 * platforms.  In theory it could be a valid setting for pre-Xe2
> > 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 05/23] drm/xe/xe3p_lpm: Stop reading the CTC_MODE register

[Matt Roper]

On Tue, Oct 14, 2025 at 09:40:50AM -0700, Matt Roper wrote:
> On Mon, Oct 13, 2025 at 08:24:37PM -0700, Lucas De Marchi wrote:
> > From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > 
> > CTC_MODE register is removed by Xe3p.  Stop reading that register on
> > Xe3p and later platforms.
> > 
> > Bspec: 62395
> > Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Actually, based on Shekhar's comment I took a 2nd look and maybe this is
a case where it should be a GRAPHICS_VER check instead of GT_VER.  See
my reply to Shekhar for details.


Matt

> 
> > ---
> >  drivers/gpu/drm/xe/xe_gt_clock.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
> > index 4f011d1573c65..26052710be8a7 100644
> > --- a/drivers/gpu/drm/xe/xe_gt_clock.c
> > +++ b/drivers/gpu/drm/xe/xe_gt_clock.c
> > @@ -57,6 +57,10 @@ static void read_crystal_clock(struct xe_gt *gt, u32 rpm_config_reg, u32 *freq,
> >  
> >  static void check_ctc_mode(struct xe_gt *gt)
> >  {
> > +	/* CTC_MODE register is removed by Xe3p */
> > +	if (GT_VER(gt) >= 35)
> > +		return;
> > +
> >  	/*
> >  	 * CTC_MODE[0] = 1 is definitely not supported for Xe2 and later
> >  	 * platforms.  In theory it could be a valid setting for pre-Xe2
> > 
> > -- 
> > 2.51.0
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 06/23] drm/xe/xe3p_lpm: Skip disabling NOA on unsupported IPs

[Matt Roper]

On Mon, Oct 13, 2025 at 08:24:38PM -0700, Lucas De Marchi wrote:
> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> 
> IP version 35 has removed "NOA Enable Signal" bit from RPM_CONFIG1
> register. Skip clearing that bit on unsupported IPs.
> 
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Bspec: 62391
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_oa.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
> index a4894eb0d7f3f..f901ba52b4032 100644
> --- a/drivers/gpu/drm/xe/xe_oa.c
> +++ b/drivers/gpu/drm/xe/xe_oa.c
> @@ -837,7 +837,8 @@ static void xe_oa_disable_metric_set(struct xe_oa_stream *stream)
>  		xe_oa_configure_oa_context(stream, false);
>  
>  	/* Make sure we disable noa to save power. */
> -	xe_mmio_rmw32(mmio, RPM_CONFIG1, GT_NOA_ENABLE, 0);
> +	if (GT_VER(stream->gt) < 35)
> +		xe_mmio_rmw32(mmio, RPM_CONFIG1, GT_NOA_ENABLE, 0);
>  
>  	sqcnt1 = SQCNT1_PMON_ENABLE |
>  		 (HAS_OA_BPC_REPORTING(stream->oa->xe) ? SQCNT1_OABPC : 0);
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 13/23] drm/xe: Dump CURRENT_LRCA and CSMQDEBUG registers

[Matt Roper]

On Mon, Oct 13, 2025 at 08:24:45PM -0700, Lucas De Marchi wrote:
> From: Wang Xin <x.wang@intel.com>
> 
> Add CURRENT_LRCA and CSMQDEBUG to register dump to help debugging.

It might be worth splitting this into two patches since CURRENT_LRCA is
something that's been around forever and can already be dumped
unconditionally on existing platforms, whereas CSMQDEBUG is a new Xe3p
register.

Also, I think CSMQDEBUG dumping would probably make more sense to be
included as part of the MQ patch series that Niranjana will be sending
later; dumping this register doesn't really have any value outside the
context of that other work.

A couple more comments farther down...

> 
> Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Wang Xin <x.wang@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_engine_regs.h |  5 +++
>  drivers/gpu/drm/xe/xe_guc_capture.c      | 53 +++++++++++++++++++++++++++++++-
>  2 files changed, 57 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index f4c3e1187a00a..7b6ec0cf78c85 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -141,6 +141,9 @@
>  #define   INHIBIT_SWITCH_UNTIL_PREEMPTED	REG_BIT(31)
>  #define   IDLE_DELAY				REG_GENMASK(20, 0)
>  
> +#define RING_CURRENT_LRCA(base)			XE_REG((base) + 0x240)
> +#define   CURRENT_LRCA_VALID			REG_BIT(0)
> +
>  #define RING_CONTEXT_CONTROL(base)		XE_REG((base) + 0x244, XE_REG_OPTION_MASKED)
>  #define	  CTX_CTRL_PXP_ENABLE			REG_BIT(10)
>  #define	  CTX_CTRL_OAC_CONTEXT_ENABLE		REG_BIT(8)
> @@ -153,6 +156,8 @@
>  #define   GFX_DISABLE_LEGACY_MODE		REG_BIT(3)
>  #define   GFX_MSIX_INTERRUPT_ENABLE		REG_BIT(13)
>  
> +#define RING_CSMQDEBUG(base)			XE_REG((base) + 0x2b0)
> +
>  #define RING_TIMESTAMP(base)			XE_REG((base) + 0x358)
>  
>  #define RING_TIMESTAMP_UDW(base)		XE_REG((base) + 0x358 + 4)
> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
> index 243dad3e24185..265aa7b7614ce 100644
> --- a/drivers/gpu/drm/xe/xe_guc_capture.c
> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c
> @@ -122,6 +122,7 @@ struct __guc_capture_parsed_output {
>  	{ RING_IPEHR(0),		REG_32BIT,	0,	0,	0,	"IPEHR"}, \
>  	{ RING_INSTDONE(0),		REG_32BIT,	0,	0,	0,	"RING_INSTDONE"}, \
>  	{ INDIRECT_RING_STATE(0),	REG_32BIT,	0,	0,	0,	"INDIRECT_RING_STATE"}, \
> +	{ RING_CURRENT_LRCA(0),		REG_32BIT,	0,	0,	0,	"CURRENT_LRCA"}, \
>  	{ RING_ACTHD(0),		REG_64BIT_LOW_DW, 0,	0,	0,	NULL}, \
>  	{ RING_ACTHD_UDW(0),		REG_64BIT_HI_DW, 0,	0,	0,	"ACTHD"}, \
>  	{ RING_BBADDR(0),		REG_64BIT_LOW_DW, 0,	0,	0,	NULL}, \
> @@ -149,6 +150,9 @@ struct __guc_capture_parsed_output {
>  	{ SFC_DONE(2),			0,	0,	0,	0,	"SFC_DONE[2]"}, \
>  	{ SFC_DONE(3),			0,	0,	0,	0,	"SFC_DONE[3]"}
>  
> +#define XE3P_BASE_ENGINE_INSTANCE \
> +	{ RING_CSMQDEBUG(0),		REG_32BIT,	0,	0,	0,	"CSMQDEBUG"}
> +
>  /* XE_LP Global */
>  static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = {
>  	COMMON_XELP_BASE_GLOBAL,
> @@ -195,6 +199,36 @@ static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = {
>  	COMMON_BASE_ENGINE_INSTANCE,
>  };
>  
> +/* Render / Compute Per-Engine-Instance */
> +static const struct __guc_mmio_reg_descr xe3p_rc_inst_regs[] = {
> +	COMMON_BASE_ENGINE_INSTANCE,
> +	XE3P_BASE_ENGINE_INSTANCE,
> +};
> +
> +/* Media Decode/Encode Per-Engine-Instance */

I'm also wondering if we really need to dump it for the vcs/vecs/gsc
engines; although the register technically exists there, those engines
don't actually support MQ so maybe it's only worth dumping on the CCS
and BCS engines?

> +static const struct __guc_mmio_reg_descr xe3p_vd_inst_regs[] = {
> +	COMMON_BASE_ENGINE_INSTANCE,
> +	XE3P_BASE_ENGINE_INSTANCE,
> +};
> +
> +/* Video Enhancement Per-Engine-Instance */
> +static const struct __guc_mmio_reg_descr xe3p_vec_inst_regs[] = {
> +	COMMON_BASE_ENGINE_INSTANCE,
> +	XE3P_BASE_ENGINE_INSTANCE,
> +};
> +
> +/* Blitter Per-Engine-Instance */
> +static const struct __guc_mmio_reg_descr xe3p_blt_inst_regs[] = {
> +	COMMON_BASE_ENGINE_INSTANCE,
> +	XE3P_BASE_ENGINE_INSTANCE,
> +};
> +
> +/* XE3P - GSC Per-Engine-Instance */
> +static const struct __guc_mmio_reg_descr xe3p_gsc_inst_regs[] = {
> +	COMMON_BASE_ENGINE_INSTANCE,
> +	XE3P_BASE_ENGINE_INSTANCE,
> +};
> +
>  /*
>   * Empty list to prevent warnings about unknown class/instance types
>   * as not all class/instance types have entries on all platforms.
> @@ -245,6 +279,21 @@ static const struct __guc_mmio_reg_descr_group xe_hpg_lists[] = {
>  	{}
>  };
>  
> + /* List of lists for graphic product version >= 3500 */
> +static const struct __guc_mmio_reg_descr_group xe3p_lists[] = {
> +	MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0),
> +	MAKE_REGLIST(xe_hpg_rc_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
> +	MAKE_REGLIST(xe3p_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
> +	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO),
> +	MAKE_REGLIST(xe3p_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO),
> +	MAKE_REGLIST(xe_vec_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
> +	MAKE_REGLIST(xe3p_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
> +	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER),
> +	MAKE_REGLIST(xe3p_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
> +	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
> +	MAKE_REGLIST(xe3p_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
> +	{}
> +};
>  static const char * const capture_list_type_names[] = {
>  	"Global",
>  	"Class",
> @@ -292,7 +341,9 @@ guc_capture_remove_stale_matches_from_list(struct xe_guc_state_capture *gc,
>  static const struct __guc_mmio_reg_descr_group *
>  guc_capture_get_device_reglist(struct xe_device *xe)
>  {
> -	if (GRAPHICS_VERx100(xe) >= 1255)
> +	if (GRAPHICS_VERx100(xe) >= 3500)

Since there's no IP with a version of exactly 35.00, I'd just do
"GRAPHICS_VER(xe) >= 35" to avoid any confusion.  Also in the comment a
little bit farther up, I'd replace the "graphic product version >= 3500"
with "Xe3p and beyond."


Matt

> +		return xe3p_lists;
> +	else if (GRAPHICS_VERx100(xe) >= 1255)
>  		return xe_hpg_lists;
>  	else
>  		return xe_lp_lists;
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 17/23] drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition

[Matt Roper]

On Tue, Oct 14, 2025 at 01:34:30PM +0530, Shekhar Chauhan wrote:
> 
> On 10/14/2025 8:54, Lucas De Marchi wrote:
> > From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > 
> > Add support for graphics IP Xe3p_XPC having IP version 35.11.
> > 
> > Bspec: 77979, 77975
> > Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> >   drivers/gpu/drm/xe/xe_pci.c | 10 ++++++++++
> >   1 file changed, 10 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> > index aa8359a4c5594..83e5e0c314a42 100644
> > --- a/drivers/gpu/drm/xe/xe_pci.c
> > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > @@ -119,6 +119,15 @@ static const struct xe_graphics_desc graphics_xe2 = {
> >   	XE2_GFX_FEATURES,
> >   };
> > +static const struct xe_graphics_desc graphics_xe3p_xpc = {
> > +	XE2_GFX_FEATURES,
> > +	.hw_engine_mask =
> > +		GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) |
> 
> In Bspec, I see the number of RES_COPY_ENGINES as 0, which signals that
> there is no BCS0. But, at the same time, I see SERVICE_COPY_ENGINES as 0.
> So, why are we having a mask from BCS1 to BCS8? Maybe I'm interpreting the
> table wrong in some way.

The table on page 74110?  I see all non-zero values for
SERVICE_COPY_ENGINES (which makes sense because I don't think we'd be
able to function at all without at least one copy engine to assist with
various vram operations).

But note that the details on that page are product/SKU-specific numbers
and not something we're allowed to hardcode in the driver.  In general
we have a way to discover the presence/absence of up to 8 engines via
fuses, so we give a mask that matches what the fuses allow us to
discover.  The actual engine mask will get reduced down during
initialization according to what we discover upon fuse readout.  We do
the same thing with other engine types that are runtime discoverable as
well.


Matt

> 
> But, aside from this change, other changes look fine, I can provide the RB
> once the above query is clarified.
> 
> > +		GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0),
> > +	.va_bits = 57,
> > +	.has_flat_ccs = false,
> > +};
> > +
> >   static const struct xe_media_desc media_xem = {
> >   	.hw_engine_mask =
> >   		GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
> > @@ -151,6 +160,7 @@ static const struct xe_ip graphics_ips[] = {
> >   	{ 3003, "Xe3_LPG", &graphics_xe2 },
> >   	{ 3004, "Xe3_LPG", &graphics_xe2 },
> >   	{ 3005, "Xe3_LPG", &graphics_xe2 },
> > +	{ 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
> >   };
> >   /* Pre-GMDID Media IPs */
> > 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 17/23] drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition

[Matt Roper]

On Mon, Oct 13, 2025 at 08:24:49PM -0700, Lucas De Marchi wrote:
> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> 
> Add support for graphics IP Xe3p_XPC having IP version 35.11.
> 
> Bspec: 77979, 77975
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_pci.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index aa8359a4c5594..83e5e0c314a42 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -119,6 +119,15 @@ static const struct xe_graphics_desc graphics_xe2 = {
>  	XE2_GFX_FEATURES,
>  };
>  
> +static const struct xe_graphics_desc graphics_xe3p_xpc = {
> +	XE2_GFX_FEATURES,
> +	.hw_engine_mask =
> +		GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) |
> +		GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0),
> +	.va_bits = 57,
> +	.has_flat_ccs = false,
> +};
> +
>  static const struct xe_media_desc media_xem = {
>  	.hw_engine_mask =
>  		GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
> @@ -151,6 +160,7 @@ static const struct xe_ip graphics_ips[] = {
>  	{ 3003, "Xe3_LPG", &graphics_xe2 },
>  	{ 3004, "Xe3_LPG", &graphics_xe2 },
>  	{ 3005, "Xe3_LPG", &graphics_xe2 },
> +	{ 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
>  };
>  
>  /* Pre-GMDID Media IPs */
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 18/23] drm/xe/xe3p_xpc: Add L3 bank mask

[Matt Roper]

On Mon, Oct 13, 2025 at 08:24:50PM -0700, Lucas De Marchi wrote:
> From: Fei Yang <fei.yang@intel.com>
> 
> Expose L3 bank mask through topology query interface.
> 
> Bspec: 74110

This is the wrong reference; 73439 is probably the one we want to use.

We should also expand the commit message a bit.  On this IP,
MIRROR_L3BANK_ENABLE represents the full L3 bank mask (not just a
per-node mask), and each bit represents a single bank.  That's why we
don't need the extra complexity that we had on other recent platforms.


Matt

> Signed-off-by: Fei Yang <fei.yang@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_gt_topology.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
> index 80ef3a6e0a3b5..14af073783ad3 100644
> --- a/drivers/gpu/drm/xe/xe_gt_topology.c
> +++ b/drivers/gpu/drm/xe/xe_gt_topology.c
> @@ -148,7 +148,11 @@ load_l3_bank_mask(struct xe_gt *gt, xe_l3_bank_mask_t l3_bank_mask)
>  	if (!xe_gt_topology_report_l3(gt))
>  		return;
>  
> -	if (GRAPHICS_VER(xe) >= 30) {
> +	if (GRAPHICS_VERx100(xe) == 3511) {
> +		u32 fuse_val = xe_mmio_read32(mmio, MIRROR_L3BANK_ENABLE);
> +
> +		bitmap_from_arr32(l3_bank_mask, &fuse_val, 32);
> +	} else if (GRAPHICS_VER(xe) >= 30) {
>  		xe_l3_bank_mask_t per_node = {};
>  		u32 meml3_en = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, fuse3);
>  		u32 mirror_l3bank_enable = xe_mmio_read32(mmio, MIRROR_L3BANK_ENABLE);
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 20/23] drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx

[Matt Roper]

On Mon, Oct 13, 2025 at 08:24:52PM -0700, Lucas De Marchi wrote:
> From: S A Muqthyar Ahmed <syed.abdul.muqthyar.ahmed@intel.com>
> 
> Current implementation of compute walker has dependency on GPU/SW Stack
> which requires SW/UMD to wait for event from KMD to indicate
> PIPE_CONTROL interrup was done. This created latency on SW stack.
> 
> This feature adds support to generate completion interrupt from GPGPU
> walker which does not support MSIx and avoid software using Pipe control
> drain/idle latency.
> 
> Suggested-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> Signed-off-by: S A Muqthyar Ahmed <syed.abdul.muqthyar.ahmed@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
>  drivers/gpu/drm/xe/xe_irq.c           | 4 ++++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> index 7c2a3a1401424..9c46b5fb81412 100644
> --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> @@ -82,6 +82,7 @@
>  #define   GSC_ER_COMPLETE			REG_BIT(5)
>  #define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)
>  #define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
> +#define   GT_COMPUTE_WALKER_INTERRUPT		REG_BIT(2)
>  #define   GT_RENDER_USER_INTERRUPT		REG_BIT(0)
>  
>  /* irqs for OTHER_KCR_INSTANCE */
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index af519414a4297..e01b158895342 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -150,6 +150,10 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>  	if (xe_device_uc_enabled(xe)) {
>  		irqs = GT_RENDER_USER_INTERRUPT |
>  			GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
> +
> +		/* Enable Compute Walker Interrupt for non-MSIX platforms */
> +		if (GRAPHICS_VERx100(xe) >= 3511 && !xe_device_has_msix(xe))
> +			irqs |= GT_COMPUTE_WALKER_INTERRUPT;

This bit only exists in the compute engine interrupt vector (bspec
62346) and render engine interrupt vector (bspec 62353).  It does not
exist in the blitter (62345), vcs (62354), vecs (62355), or gsc (63341),
which makes sense because none of those engines can run compute walkers.
Should we be making sure we only try to unmask and enable this interrupt
on supported engine types?


Matt

>  	} else {
>  		irqs = GT_RENDER_USER_INTERRUPT |
>  		       GT_CS_MASTER_ERROR_INTERRUPT |
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 21/23] drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs

[Matt Roper]

On Tue, Oct 14, 2025 at 01:39:39PM +0530, Shekhar Chauhan wrote:
> 
> On 10/14/2025 8:54, Lucas De Marchi wrote:
> > From: Matt Roper <matthew.d.roper@intel.com>
> > 
> > The compression overfetch tuning settings only apply to platforms that
> > support FlatCCS.  In Xe3p_XPC (and any future IPs that also lack
> > compression) some of the registers being adjusted by this tuning will
> > not exist or may have been repurposed for something else, so we should
> > take care not to try to program them.
> > 
> > Note that our xe_rtp_match_has_flatccs() function will also return false
> > on platforms that do have FlatCCS in the hardware design, but have
> > compression manually disabled in the BIOS.  On such platforms the
> > registers still exist (and it would be fine to continue programming
> > them), but they would have no effect, so skipping that tuning is also
> > safe.
> > 
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> The patch in itself looks fine to me, but, the patch doesn't specifically
> play only around Xe3p_XPC. Maybe we can move this patch out of the current
> series, or if we wish to keep it here, can we instead drop the xe3p_xpc from
> the prefix? Thoughts?

Aside from PVC (which is Xe1 and not relevant to these tuning settings),
Xe3p_XPC is the only IP we have without FlatCCS in the design, so at the
moment this patch is specific to Xe3p_XPC.  As a general architecture
though, if we eventually wind up with other IPs down the road that also
lack FlatCCS, then these tuning settings will also not apply to them for
the same reasons.


Matt

> > ---
> >   drivers/gpu/drm/xe/xe_rtp.c    |  6 ++++++
> >   drivers/gpu/drm/xe/xe_rtp.h    | 10 ++++++++++
> >   drivers/gpu/drm/xe/xe_tuning.c |  9 ++++++---
> >   3 files changed, 22 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
> > index b5f430d59f805..22a879270c1ec 100644
> > --- a/drivers/gpu/drm/xe/xe_rtp.c
> > +++ b/drivers/gpu/drm/xe/xe_rtp.c
> > @@ -376,3 +376,9 @@ bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,
> >   {
> >   	return xe_gt_has_discontiguous_dss_groups(gt);
> >   }
> > +
> > +bool xe_rtp_match_has_flat_ccs(const struct xe_gt *gt,
> > +			      const struct xe_hw_engine *hwe)
> > +{
> > +	return gt_to_xe(gt)->info.has_flat_ccs;
> > +}
> > diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
> > index ac12ddf6cde6d..92f0d16110dd5 100644
> > --- a/drivers/gpu/drm/xe/xe_rtp.h
> > +++ b/drivers/gpu/drm/xe/xe_rtp.h
> > @@ -483,4 +483,14 @@ bool xe_rtp_match_psmi_enabled(const struct xe_gt *gt,
> >   bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,
> >   						  const struct xe_hw_engine *hwe);
> > +/**
> > + * xe_rtp_match_has_flat_ccs - Match when platform has FlatCCS compression
> > + * @gt: GT structure
> > + * @hwe: Engine instance
> > + *
> > + * Returns: true if platform has FlatCCS compression, false otherwise
> > + */
> > +bool xe_rtp_match_has_flat_ccs(const struct xe_gt *gt,
> > +			       const struct xe_hw_engine *hwe);
> > +
> >   #endif
> > diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> > index fd58ea5e78bf6..7c140d8cb1e07 100644
> > --- a/drivers/gpu/drm/xe/xe_tuning.c
> > +++ b/drivers/gpu/drm/xe/xe_tuning.c
> > @@ -40,7 +40,8 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
> >   				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
> >   	},
> >   	{ XE_RTP_NAME("Tuning: Compression Overfetch"),
> > -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
> > +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
> > +		       FUNC(xe_rtp_match_has_flat_ccs)),
> >   	  XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
> >   			 SET(CCCHKNREG1, L3CMPCTRL))
> >   	},
> > @@ -58,12 +59,14 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
> >   	  XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3, COMPPWOVERFETCHEN))
> >   	},
> >   	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
> > -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
> > +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
> > +		       FUNC(xe_rtp_match_has_flat_ccs)),
> >   	  XE_RTP_ACTIONS(SET(L3SQCREG2,
> >   			     COMPMEMRD256BOVRFETCHEN))
> >   	},
> >   	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only - media"),
> > -	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
> > +	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED),
> > +		       FUNC(xe_rtp_match_has_flat_ccs)),
> >   	  XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
> >   			     COMPMEMRD256BOVRFETCHEN))
> >   	},
> > 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 23/23] drm/xe/xe3p: Add xe3p EU stall data format

[Matt Roper]

On Mon, Oct 13, 2025 at 08:24:55PM -0700, Lucas De Marchi wrote:
> From: Harish Chegondi <harish.chegondi@intel.com>
> 
> Starting with Xe3p, IP address in EU stall data is increases to 61 bits.

As far as I can see, the EU stall format isn't documented anywhere in
the bspec (which seems like a major oversight!) but the early
architecture document related to this change seems to indicate that a
full 64-bit IP was supposed to be written by hardware now

        "Bit filed[sic] 0-28 is now 0-63"

Your structure is only using 61 bits (which definitely makes sense if
the addresses are aligned since the lowest three bits would always be
0's); is there somewhere other than the bspec or architecture document
that we should be looking at to confirm this?

If you've been working directly with the hardware architects on this
feature, please poke them about documenting this clearly in the bspec
(with proper tagging by IP/platform) so that we can verify this is
handled correctly and also notice if/when the format changes again on
future platforms.


Matt

> 
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_eu_stall.c | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
> index f5cfdf29fde34..2bc6b593ff172 100644
> --- a/drivers/gpu/drm/xe/xe_eu_stall.c
> +++ b/drivers/gpu/drm/xe/xe_eu_stall.c
> @@ -124,6 +124,27 @@ struct xe_eu_stall_data_xe2 {
>  	__u64 unused[6];
>  } __packed;
>  
> +/*
> + * EU stall data format for Xe3p arch GPUs.
> + */
> +struct xe_eu_stall_data_xe3p {
> +	__u64 ip_addr:61;	  /* Bits 0  to 60  */
> +	__u64 tdr_count:8;	  /* Bits 61 to 68  */
> +	__u64 other_count:8;	  /* Bits 69 to 76  */
> +	__u64 control_count:8;	  /* Bits 77 to 84  */
> +	__u64 pipestall_count:8;  /* Bits 85 to 92  */
> +	__u64 send_count:8;	  /* Bits 93 to 100 */
> +	__u64 dist_acc_count:8;   /* Bits 101 to 108 */
> +	__u64 sbid_count:8;	  /* Bits 109 to 116 */
> +	__u64 sync_count:8;	  /* Bits 117 to 124 */
> +	__u64 inst_fetch_count:8; /* Bits 125 to 132 */
> +	__u64 active_count:8;	  /* Bits 133 to 140 */
> +	__u64 ex_id:3;		  /* Bits 141 to 143 */
> +	__u64 end_flag:1;	  /* Bit  144 */
> +	__u64 unused_bits:47;
> +	__u64 unused[5];
> +} __packed;
> +
>  const u64 eu_stall_sampling_rates[] = {251, 251 * 2, 251 * 3, 251 * 4, 251 * 5, 251 * 6, 251 * 7};
>  
>  /**
> @@ -169,6 +190,8 @@ size_t xe_eu_stall_data_record_size(struct xe_device *xe)
>  
>  	if (xe->info.platform == XE_PVC)
>  		record_size = sizeof(struct xe_eu_stall_data_pvc);
> +	else if (GRAPHICS_VER(xe) >= 35)
> +		record_size = sizeof(struct xe_eu_stall_data_xe3p);
>  	else if (GRAPHICS_VER(xe) >= 20)
>  		record_size = sizeof(struct xe_eu_stall_data_xe2);
>  
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 10/23] drm/xe/xe3p: Skip TD flush

[Matt Roper]

On Mon, Oct 13, 2025 at 08:24:42PM -0700, Lucas De Marchi wrote:
> From: Tejas Upadhyay <tejas.upadhyay@intel.com>
> 
> Xe3p has HW ability to do transient display flush so the xe driver can
> enable this HW feature by default and skip the software TD flush.

I think we need to expand on the description here.  "has HW ability to
do flush" is very ambiguous --- how/when specifically will the hardware
decide to flush the TD data if software isn't explicitly triggering it
anymore?

If I remember this feature correctly, the actual hardware change here is
that "display transient" data will now get flushed automatically anytime
"app transient" data gets flushed (whereas previously the display
transient data had to be flushed independently).  But I don't remember
the details for "app transient" off the top of my head now (I remember
it was complicated with different rules depending on whether the media
hardware was awake or asleep), and there's no reference to it in the
driver yet (I believe Xe3p is the first time it shows up, right?).  The
only Xe3p PAT table we have in this series (Xe3p_XPC) has neither XD nor
XA entries, so maybe this patch is coming too early to be useful.


Matt

> 
> Bspec: 60002
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_device.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index 6f8f72fd1b133..7efa8da9e1069 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -1103,6 +1103,14 @@ void xe_device_td_flush(struct xe_device *xe)
>  {
>  	struct xe_gt *root_gt;
>  
> +	/*
> +	 * From Xe3p onward the HW takes care of flush of TD entries also along
> +	 * with flushing XA entries, which will be at the usual sync points,
> +	 * like at the end of submission, so no manual flush is needed here.
> +	 */
> +	if (GRAPHICS_VER(xe) >= 35)
> +		return;
> +
>  	if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20)
>  		return;
>  
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 11/23] drm/xe/xe3p: Enable L2 flush optimization feature

[Matt Roper]

On Mon, Oct 13, 2025 at 08:24:43PM -0700, Lucas De Marchi wrote:
> From: Tejas Upadhyay <tejas.upadhyay@intel.com>
> 
> When set, the L2 flush optimization feature will control whether L2 is
> in Persistent or Transient mode through monitoring of media activity.

Similar to the previous patch, this commit message doesn't really help
the reader understand what's going on.  I believe the intent here was to
inform the GuC that it should be doing some of the special handling for
app-transient caching according to whether media is active or not;
that's why we have an unusual condition that checks the primary GT's
version, but then applies the GuC flag on the media GT.

But as noted on the previous patch, we still don't have a way to mark
data as transient yet on Xe3p (of either the display- or app- variety),
so this change may be a bit premature; we should postpone this to a
later series.  And at that time we should probably start out with a
kerneldoc patch first that explains these new caching behaviors so that
readers have the necessary context before we start changing the code
behavior.


Matt

> 
> To enable L2 flush optimization include new feature flag
> GUC_CTL_ENABLE_L2FLUSH_OPT is used when media gt type is detected.
> 
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_guc.c      | 3 +++
>  drivers/gpu/drm/xe/xe_guc_fwif.h | 1 +
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index ecc3e091b89e6..3296f28803593 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -94,6 +94,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
>  	if (xe_guc_using_main_gamctrl_queues(guc))
>  		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
>  
> +	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) && xe_gt_is_media_type(guc_to_gt(guc)))
> +		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
> +
>  	return flags;
>  }
>  
> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
> index c90dd266e9cf9..c42572306158d 100644
> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> @@ -115,6 +115,7 @@ struct guc_update_exec_queue_policy {
>  #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
>  #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
>  #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
> +#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
>  
>  #define GUC_CTL_DEBUG			3
>  #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 03/23] drm/xe/xe3p_lpm: Configure MAIN_GAMCTRL_QUEUE_SELECT

[Lucas De Marchi]

On Tue, Oct 14, 2025 at 09:34:03AM -0700, Matt Roper wrote:
>On Mon, Oct 13, 2025 at 08:24:35PM -0700, Lucas De Marchi wrote:
>> From: Brian Welty <brian.welty@intel.com>
>>
>> Starting from Xe3p, there are two different copies of some of the GAM
>> registers:  the traditional MCR variant at their old locations, and a
>> new unicast copy known as "main_gamctrl."  The Xe driver doesn't use
>> these registers directly, but we need to instruct the GuC on which set
>> it should use.  Since the new, unicast registers are preferred (since
>> they avoid the need for unnecessary MCR synchronization), set a new GuC
>> feature flag, GUC_CTL_MAIN_GAMCTRL_QUEUES to convey this decision.  A
>> new helper function, xe_guc_using_main_gamctrl_queues(), is added for
>> use in the 3 independent places that need to handle configuration of the
>> new reporting queues.
>>
>> The mmio write to enable the main gamctl is only done during the general
>> GuC upload.  The gamctrl registers are not accessed by the GuC during
>> hwconfig load.
>>
>> Last, the ADS blob for communicating the queue addresses contains both a
>> DPA and GGTT offset. The GuC documentation states that DPA is now MBZ
>> when using the MAIN_GAMCTRL queues.
>>
>> Signed-off-by: Brian Welty <brian.welty@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  3 +++
>>  drivers/gpu/drm/xe/xe_gt.h           |  6 ++++++
>>  drivers/gpu/drm/xe/xe_guc.c          | 27 +++++++++++++++++++++++++++
>>  drivers/gpu/drm/xe/xe_guc.h          |  1 +
>>  drivers/gpu/drm/xe/xe_guc_ads.c      |  6 +++++-
>>  drivers/gpu/drm/xe/xe_guc_fwif.h     |  1 +
>>  6 files changed, 43 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> index 51f2a03847f9d..47e13a3fb9072 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -545,6 +545,9 @@
>>  #define SARB_CHICKEN1				XE_REG_MCR(0xe90c)
>>  #define   COMP_CKN_IN				REG_GENMASK(30, 29)
>>
>> +#define MAIN_GAMCTRL_MODE			XE_REG(0xef00)
>> +#define   MAIN_GAMCTRL_QUEUE_SELECT		REG_BIT(0)
>> +
>>  #define RCU_MODE				XE_REG(0x14800, XE_REG_OPTION_MASKED)
>>  #define   RCU_MODE_FIXED_SLICE_CCS_MODE		REG_BIT(1)
>>  #define   RCU_MODE_CCS_ENABLE			REG_BIT(0)
>> diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h
>> index 5df2ffe3ff838..9d710049da455 100644
>> --- a/drivers/gpu/drm/xe/xe_gt.h
>> +++ b/drivers/gpu/drm/xe/xe_gt.h
>> @@ -22,6 +22,12 @@
>>
>>  #define CCS_MASK(gt) (((gt)->info.engine_mask & XE_HW_ENGINE_CCS_MASK) >> XE_HW_ENGINE_CCS0)
>>
>> +#define GT_VER(gt) ({ \
>> +	typeof(gt) gt_ = (gt); \
>> +	struct xe_device *xe = gt_to_xe(gt_); \
>> +	xe_gt_is_media_type(gt_) ? MEDIA_VER(xe) : GRAPHICS_VER(xe); \
>> +})
>> +
>>  extern struct fault_attr gt_reset_failure;
>>  static inline bool xe_fault_inject_gt_reset(void)
>>  {
>> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>> index d94490979adc0..37e3735f34e63 100644
>> --- a/drivers/gpu/drm/xe/xe_guc.c
>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>> @@ -91,6 +91,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
>>  	if (xe_configfs_get_psmi_enabled(to_pci_dev(xe->drm.dev)))
>>  		flags |= GUC_CTL_ENABLE_PSMI_LOGGING;
>>
>> +	if (xe_guc_using_main_gamctrl_queues(guc))
>> +		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
>> +
>>  	return flags;
>>  }
>>
>> @@ -1255,8 +1258,13 @@ int xe_guc_min_load_for_hwconfig(struct xe_guc *guc)
>>
>>  int xe_guc_upload(struct xe_guc *guc)
>>  {
>> +	struct xe_gt *gt = guc_to_gt(guc);
>> +
>>  	xe_guc_ads_populate(&guc->ads);
>>
>> +	if (xe_guc_using_main_gamctrl_queues(guc))
>> +		xe_mmio_write32(&gt->mmio, MAIN_GAMCTRL_MODE, MAIN_GAMCTRL_QUEUE_SELECT);
>> +
>>  	return __xe_guc_upload(guc);
>>  }
>>
>> @@ -1657,6 +1665,25 @@ void xe_guc_declare_wedged(struct xe_guc *guc)
>>  	xe_guc_submit_wedge(guc);
>>  }
>>
>> +/**
>> + * xe_guc_using_main_gamctrl_queues() - Detect which reporting queues to use.
>> + * @guc: The GuC object
>> + *
>> + * For Xe3p and beyond, we want to program the hardware to use the
>> + * "Main GAMCTRL queue" rather than the legacy queue before we upload
>> + * the GuC firmware.  This will allow the GuC to use a new set of
>> + * registers for pagefault handling and avoid some unnecessary
>> + * complications with MCR register range handling.
>> + *
>> + * Return: true if can use new main gamctrl queues.
>> + */
>> +bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc)
>> +{
>> +	struct xe_gt *gt = guc_to_gt(guc);
>> +
>> +	return GT_VER(gt) >= 35;
>
>Revisiting the spec on this, I'm not sure whether using GT_VER() here is
>actually the right thing to do.  As far as I can see, the media GT does
>not actually have a "main gamctrl" register range at all (i.e., bspec
>76445 only lists MCR gamctrl ranges, and 0x38EF00-0x38EFFF falls within
>a reserved/unused block).  That means that registers like

true

>MAIN_GAMCTRL_MODE that we're trying to write during xe_guc_upload above

We do have MAIN_GAMCTRL_MODE for xe3p_lpm in bspec 73540.
The tagging is odd, but there is a reference to the register at
0x38EF00. It wouldn't make sense to have a 0x38xxxx register instance
for primary/graphics GT.

So either

1) we don't have it like you said
2) we have it and there's something missing in the MCR ranges

>don't actually exist for the media GT.  Furthermore, the tagging on the
>register detail page 73540 also seems to imply that this only applies to
>the primary/graphics GT.

so... in that case we'd need to check both the gt type and graphics ver,
so we load GuC with those different flags. I will take a shot at that
and check if anything breaks.

Bala, since you did the patch following this, do you remember of
anything related to this?

Lucas De Marchi

>
>
>Matt
>
>> +}
>> +
>>  #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
>>  #include "tests/xe_guc_g2g_test.c"
>>  #endif
>> diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h
>> index 1cca05967e621..e2d4c5f44ae34 100644
>> --- a/drivers/gpu/drm/xe/xe_guc.h
>> +++ b/drivers/gpu/drm/xe/xe_guc.h
>> @@ -52,6 +52,7 @@ void xe_guc_stop_prepare(struct xe_guc *guc);
>>  void xe_guc_stop(struct xe_guc *guc);
>>  int xe_guc_start(struct xe_guc *guc);
>>  void xe_guc_declare_wedged(struct xe_guc *guc);
>> +bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc);
>>
>>  #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
>>  int xe_guc_g2g_test_notification(struct xe_guc *guc, u32 *payload, u32 len);
>> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
>> index 22ac2a8b74c80..bcb85a1bf26d9 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
>> @@ -820,16 +820,20 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
>>  static void guc_um_init_params(struct xe_guc_ads *ads)
>>  {
>>  	u32 um_queue_offset = guc_ads_um_queues_offset(ads);
>> +	struct xe_guc *guc = ads_to_guc(ads);
>>  	u64 base_dpa;
>>  	u32 base_ggtt;
>> +	bool with_dpa;
>>  	int i;
>>
>> +	with_dpa = !xe_guc_using_main_gamctrl_queues(guc);
>> +
>>  	base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset;
>>  	base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset;
>>
>>  	for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) {
>>  		ads_blob_write(ads, um_init_params.queue_params[i].base_dpa,
>> -			       base_dpa + (i * GUC_UM_QUEUE_SIZE));
>> +			       with_dpa ? (base_dpa + (i * GUC_UM_QUEUE_SIZE)) : 0);
>>  		ads_blob_write(ads, um_init_params.queue_params[i].base_ggtt_address,
>>  			       base_ggtt + (i * GUC_UM_QUEUE_SIZE));
>>  		ads_blob_write(ads, um_init_params.queue_params[i].size_in_bytes,
>> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
>> index 50c4c2406132e..c90dd266e9cf9 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
>> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
>> @@ -113,6 +113,7 @@ struct guc_update_exec_queue_policy {
>>  #define   GUC_CTL_ENABLE_SLPC		BIT(2)
>>  #define   GUC_CTL_ENABLE_LITE_RESTORE	BIT(4)
>>  #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
>> +#define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
>>  #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
>>
>>  #define GUC_CTL_DEBUG			3
>>
>> --
>> 2.51.0
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [PATCH 17/23] drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition

[Shekhar Chauhan]

On 10/14/2025 23:03, Matt Roper wrote:
> On Tue, Oct 14, 2025 at 01:34:30PM +0530, Shekhar Chauhan wrote:
>> On 10/14/2025 8:54, Lucas De Marchi wrote:
>>> From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>>>
>>> Add support for graphics IP Xe3p_XPC having IP version 35.11.
>>>
>>> Bspec: 77979, 77975
>>> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>> ---
>>>    drivers/gpu/drm/xe/xe_pci.c | 10 ++++++++++
>>>    1 file changed, 10 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>>> index aa8359a4c5594..83e5e0c314a42 100644
>>> --- a/drivers/gpu/drm/xe/xe_pci.c
>>> +++ b/drivers/gpu/drm/xe/xe_pci.c
>>> @@ -119,6 +119,15 @@ static const struct xe_graphics_desc graphics_xe2 = {
>>>    	XE2_GFX_FEATURES,
>>>    };
>>> +static const struct xe_graphics_desc graphics_xe3p_xpc = {
>>> +	XE2_GFX_FEATURES,
>>> +	.hw_engine_mask =
>>> +		GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) |
>> In Bspec, I see the number of RES_COPY_ENGINES as 0, which signals that
>> there is no BCS0. But, at the same time, I see SERVICE_COPY_ENGINES as 0.
>> So, why are we having a mask from BCS1 to BCS8? Maybe I'm interpreting the
>> table wrong in some way.
> The table on page 74110?  I see all non-zero values for
> SERVICE_COPY_ENGINES (which makes sense because I don't think we'd be
> able to function at all without at least one copy engine to assist with
> various vram operations).
>
> But note that the details on that page are product/SKU-specific numbers
> and not something we're allowed to hardcode in the driver.  In general
> we have a way to discover the presence/absence of up to 8 engines via
> fuses, so we give a mask that matches what the fuses allow us to
> discover.  The actual engine mask will get reduced down during
> initialization according to what we discover upon fuse readout.  We do
> the same thing with other engine types that are runtime discoverable as
> well.
>
>
> Matt

Okay okay, thanks

-shekhar

>
>> But, aside from this change, other changes look fine, I can provide the RB
>> once the above query is clarified.
>>
>>> +		GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0),
>>> +	.va_bits = 57,
>>> +	.has_flat_ccs = false,
>>> +};
>>> +
>>>    static const struct xe_media_desc media_xem = {
>>>    	.hw_engine_mask =
>>>    		GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
>>> @@ -151,6 +160,7 @@ static const struct xe_ip graphics_ips[] = {
>>>    	{ 3003, "Xe3_LPG", &graphics_xe2 },
>>>    	{ 3004, "Xe3_LPG", &graphics_xe2 },
>>>    	{ 3005, "Xe3_LPG", &graphics_xe2 },
>>> +	{ 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
>>>    };
>>>    /* Pre-GMDID Media IPs */
>>>

Re: [PATCH 21/23] drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs

[Shekhar Chauhan]

On 10/14/2025 23:44, Matt Roper wrote:
> On Tue, Oct 14, 2025 at 01:39:39PM +0530, Shekhar Chauhan wrote:
>> On 10/14/2025 8:54, Lucas De Marchi wrote:
>>> From: Matt Roper <matthew.d.roper@intel.com>
>>>
>>> The compression overfetch tuning settings only apply to platforms that
>>> support FlatCCS.  In Xe3p_XPC (and any future IPs that also lack
>>> compression) some of the registers being adjusted by this tuning will
>>> not exist or may have been repurposed for something else, so we should
>>> take care not to try to program them.
>>>
>>> Note that our xe_rtp_match_has_flatccs() function will also return false
>>> on platforms that do have FlatCCS in the hardware design, but have
>>> compression manually disabled in the BIOS.  On such platforms the
>>> registers still exist (and it would be fine to continue programming
>>> them), but they would have no effect, so skipping that tuning is also
>>> safe.
>>>
>>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> The patch in itself looks fine to me, but, the patch doesn't specifically
>> play only around Xe3p_XPC. Maybe we can move this patch out of the current
>> series, or if we wish to keep it here, can we instead drop the xe3p_xpc from
>> the prefix? Thoughts?
> Aside from PVC (which is Xe1 and not relevant to these tuning settings),
> Xe3p_XPC is the only IP we have without FlatCCS in the design, so at the
> moment this patch is specific to Xe3p_XPC.  As a general architecture
> though, if we eventually wind up with other IPs down the road that also
> lack FlatCCS, then these tuning settings will also not apply to them for
> the same reasons.
>
>
> Matt

Okay, makes sense, I'm still skeptical on whether this should be named 
with the prefix Xe3p_XPC if we expect it to carry it's effect to other 
future platforms as well. For that reason, I believe, the commit title 
can be 'drm/xe: Skip compression tuning on platforms without flatccs'. 
This in itself engulfs Xe3p_XPC (and any other future platforms). But, 
consider this feedback as only a nitpick.

Since the changes already look good,

Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>

>
>>> ---
>>>    drivers/gpu/drm/xe/xe_rtp.c    |  6 ++++++
>>>    drivers/gpu/drm/xe/xe_rtp.h    | 10 ++++++++++
>>>    drivers/gpu/drm/xe/xe_tuning.c |  9 ++++++---
>>>    3 files changed, 22 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
>>> index b5f430d59f805..22a879270c1ec 100644
>>> --- a/drivers/gpu/drm/xe/xe_rtp.c
>>> +++ b/drivers/gpu/drm/xe/xe_rtp.c
>>> @@ -376,3 +376,9 @@ bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,
>>>    {
>>>    	return xe_gt_has_discontiguous_dss_groups(gt);
>>>    }
>>> +
>>> +bool xe_rtp_match_has_flat_ccs(const struct xe_gt *gt,
>>> +			      const struct xe_hw_engine *hwe)
>>> +{
>>> +	return gt_to_xe(gt)->info.has_flat_ccs;
>>> +}
>>> diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
>>> index ac12ddf6cde6d..92f0d16110dd5 100644
>>> --- a/drivers/gpu/drm/xe/xe_rtp.h
>>> +++ b/drivers/gpu/drm/xe/xe_rtp.h
>>> @@ -483,4 +483,14 @@ bool xe_rtp_match_psmi_enabled(const struct xe_gt *gt,
>>>    bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,
>>>    						  const struct xe_hw_engine *hwe);
>>> +/**
>>> + * xe_rtp_match_has_flat_ccs - Match when platform has FlatCCS compression
>>> + * @gt: GT structure
>>> + * @hwe: Engine instance
>>> + *
>>> + * Returns: true if platform has FlatCCS compression, false otherwise
>>> + */
>>> +bool xe_rtp_match_has_flat_ccs(const struct xe_gt *gt,
>>> +			       const struct xe_hw_engine *hwe);
>>> +
>>>    #endif
>>> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
>>> index fd58ea5e78bf6..7c140d8cb1e07 100644
>>> --- a/drivers/gpu/drm/xe/xe_tuning.c
>>> +++ b/drivers/gpu/drm/xe/xe_tuning.c
>>> @@ -40,7 +40,8 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>>>    				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
>>>    	},
>>>    	{ XE_RTP_NAME("Tuning: Compression Overfetch"),
>>> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
>>> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
>>> +		       FUNC(xe_rtp_match_has_flat_ccs)),
>>>    	  XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
>>>    			 SET(CCCHKNREG1, L3CMPCTRL))
>>>    	},
>>> @@ -58,12 +59,14 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>>>    	  XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3, COMPPWOVERFETCHEN))
>>>    	},
>>>    	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
>>> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
>>> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
>>> +		       FUNC(xe_rtp_match_has_flat_ccs)),
>>>    	  XE_RTP_ACTIONS(SET(L3SQCREG2,
>>>    			     COMPMEMRD256BOVRFETCHEN))
>>>    	},
>>>    	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only - media"),
>>> -	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
>>> +	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED),
>>> +		       FUNC(xe_rtp_match_has_flat_ccs)),
>>>    	  XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
>>>    			     COMPMEMRD256BOVRFETCHEN))
>>>    	},
>>>

Re: [PATCH 05/23] drm/xe/xe3p_lpm: Stop reading the CTC_MODE register

[Lucas De Marchi]

On Tue, Oct 14, 2025 at 09:52:11AM -0700, Matt Roper wrote:
>On Tue, Oct 14, 2025 at 05:28:48PM +0530, Shekhar Chauhan wrote:
>>
>> On 10/14/2025 8:54, Lucas De Marchi wrote:
>> > From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>> >
>> > CTC_MODE register is removed by Xe3p.  Stop reading that register on
>> > Xe3p and later platforms.
>> >
>> > Bspec: 62395
>>
>> Again, maybe I'm referencing the Bspec in a wrong way, but I do see this
>> register existing for IP 35. Maybe a possible tagging issue in the Bspec?
>> Can someone comment here, if I'm missing something.
>
>So looking a bit closer based on your comment, I think maybe this should
>actually be a GRAPHICS_VER() test rather than a GT_VER() test.  It gets
>a bit confusing since the bspec website still tries to print stuff out
>in a platform-based manner, which makes it hard to follow exactly which
>IP versions and GTs are actually relevant.  In this case the first
>REMOVEDBY() tag listed is what documents the removal of the CTC_MODE
>register, but it appears that tag only applies to primary GT; the media
>GT is not included by the change referenced.  And then if you look
>through the jumble of platform names that come after that, it does
>indeed appear that media is still listed as having the register, but the
>primary GT no longer appears in the list for platforms with Xe3p IP.
>
>So maybe this is another case where we should be using GRAPHICS_VER
>instead of GT_VER.  I'm not sure it really matters too much though since
>we don't actually use the register for anything, except to complain
>about a condition we expect to never show up.

maybe at this point we should just drop the entire thing?
It's not supported for xe2/xe3, it's dropped for xe3p. It's supported
for unofficially supported platforms, but we don't really know what to
do in that case.

So I think it'd be safe to just drop the entire function and now worry
about what is the exact gt version. Thoughts?

Lucas De Marchi

>
>
>Matt
>
>>
>> -shekhar
>>
>> > Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> > ---
>> >   drivers/gpu/drm/xe/xe_gt_clock.c | 4 ++++
>> >   1 file changed, 4 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
>> > index 4f011d1573c65..26052710be8a7 100644
>> > --- a/drivers/gpu/drm/xe/xe_gt_clock.c
>> > +++ b/drivers/gpu/drm/xe/xe_gt_clock.c
>> > @@ -57,6 +57,10 @@ static void read_crystal_clock(struct xe_gt *gt, u32 rpm_config_reg, u32 *freq,
>> >   static void check_ctc_mode(struct xe_gt *gt)
>> >   {
>> > +	/* CTC_MODE register is removed by Xe3p */
>> > +	if (GT_VER(gt) >= 35)
>> > +		return;
>> > +
>> >   	/*
>> >   	 * CTC_MODE[0] = 1 is definitely not supported for Xe2 and later
>> >   	 * platforms.  In theory it could be a valid setting for pre-Xe2
>> >
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [PATCH 11/23] drm/xe/xe3p: Enable L2 flush optimization feature

[Lucas De Marchi]

On Tue, Oct 14, 2025 at 12:43:37PM -0700, Matt Roper wrote:
>On Mon, Oct 13, 2025 at 08:24:43PM -0700, Lucas De Marchi wrote:
>> From: Tejas Upadhyay <tejas.upadhyay@intel.com>
>>
>> When set, the L2 flush optimization feature will control whether L2 is
>> in Persistent or Transient mode through monitoring of media activity.
>
>Similar to the previous patch, this commit message doesn't really help
>the reader understand what's going on.  I believe the intent here was to
>inform the GuC that it should be doing some of the special handling for
>app-transient caching according to whether media is active or not;
>that's why we have an unusual condition that checks the primary GT's
>version, but then applies the GuC flag on the media GT.
>
>But as noted on the previous patch, we still don't have a way to mark
>data as transient yet on Xe3p (of either the display- or app- variety),
>so this change may be a bit premature; we should postpone this to a
>later series.  And at that time we should probably start out with a
>kerneldoc patch first that explains these new caching behaviors so that
>readers have the necessary context before we start changing the code
>behavior.

agreed. I will drop this on next rev

thanks
Lucas De Marchi

>
>
>Matt
>
>>
>> To enable L2 flush optimization include new feature flag
>> GUC_CTL_ENABLE_L2FLUSH_OPT is used when media gt type is detected.
>>
>> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/xe/xe_guc.c      | 3 +++
>>  drivers/gpu/drm/xe/xe_guc_fwif.h | 1 +
>>  2 files changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>> index ecc3e091b89e6..3296f28803593 100644
>> --- a/drivers/gpu/drm/xe/xe_guc.c
>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>> @@ -94,6 +94,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
>>  	if (xe_guc_using_main_gamctrl_queues(guc))
>>  		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
>>
>> +	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) && xe_gt_is_media_type(guc_to_gt(guc)))
>> +		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
>> +
>>  	return flags;
>>  }
>>
>> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
>> index c90dd266e9cf9..c42572306158d 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
>> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
>> @@ -115,6 +115,7 @@ struct guc_update_exec_queue_policy {
>>  #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
>>  #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
>>  #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
>> +#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
>>
>>  #define GUC_CTL_DEBUG			3
>>  #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
>>
>> --
>> 2.51.0
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [PATCH 13/23] drm/xe: Dump CURRENT_LRCA and CSMQDEBUG registers

[Lucas De Marchi]

On Tue, Oct 14, 2025 at 10:24:45AM -0700, Matt Roper wrote:
>On Mon, Oct 13, 2025 at 08:24:45PM -0700, Lucas De Marchi wrote:
>> From: Wang Xin <x.wang@intel.com>
>>
>> Add CURRENT_LRCA and CSMQDEBUG to register dump to help debugging.
>
>It might be worth splitting this into two patches since CURRENT_LRCA is
>something that's been around forever and can already be dumped
>unconditionally on existing platforms, whereas CSMQDEBUG is a new Xe3p
>register.
>
>Also, I think CSMQDEBUG dumping would probably make more sense to be
>included as part of the MQ patch series that Niranjana will be sending
>later; dumping this register doesn't really have any value outside the
>context of that other work.

ack on splitting. I will do it, but also send the CSMQDEBUG support on
next rev. My thought was that have that in would actually help getting
the MQ changes. But we can also decide not to pick that patch now, in
which case Niranjana can add it to his series.

>
>A couple more comments farther down...
>
>>
>> Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Wang Xin <x.wang@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/xe/regs/xe_engine_regs.h |  5 +++
>>  drivers/gpu/drm/xe/xe_guc_capture.c      | 53 +++++++++++++++++++++++++++++++-
>>  2 files changed, 57 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
>> index f4c3e1187a00a..7b6ec0cf78c85 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
>> @@ -141,6 +141,9 @@
>>  #define   INHIBIT_SWITCH_UNTIL_PREEMPTED	REG_BIT(31)
>>  #define   IDLE_DELAY				REG_GENMASK(20, 0)
>>
>> +#define RING_CURRENT_LRCA(base)			XE_REG((base) + 0x240)
>> +#define   CURRENT_LRCA_VALID			REG_BIT(0)
>> +
>>  #define RING_CONTEXT_CONTROL(base)		XE_REG((base) + 0x244, XE_REG_OPTION_MASKED)
>>  #define	  CTX_CTRL_PXP_ENABLE			REG_BIT(10)
>>  #define	  CTX_CTRL_OAC_CONTEXT_ENABLE		REG_BIT(8)
>> @@ -153,6 +156,8 @@
>>  #define   GFX_DISABLE_LEGACY_MODE		REG_BIT(3)
>>  #define   GFX_MSIX_INTERRUPT_ENABLE		REG_BIT(13)
>>
>> +#define RING_CSMQDEBUG(base)			XE_REG((base) + 0x2b0)
>> +
>>  #define RING_TIMESTAMP(base)			XE_REG((base) + 0x358)
>>
>>  #define RING_TIMESTAMP_UDW(base)		XE_REG((base) + 0x358 + 4)
>> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
>> index 243dad3e24185..265aa7b7614ce 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_capture.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c
>> @@ -122,6 +122,7 @@ struct __guc_capture_parsed_output {
>>  	{ RING_IPEHR(0),		REG_32BIT,	0,	0,	0,	"IPEHR"}, \
>>  	{ RING_INSTDONE(0),		REG_32BIT,	0,	0,	0,	"RING_INSTDONE"}, \
>>  	{ INDIRECT_RING_STATE(0),	REG_32BIT,	0,	0,	0,	"INDIRECT_RING_STATE"}, \
>> +	{ RING_CURRENT_LRCA(0),		REG_32BIT,	0,	0,	0,	"CURRENT_LRCA"}, \
>>  	{ RING_ACTHD(0),		REG_64BIT_LOW_DW, 0,	0,	0,	NULL}, \
>>  	{ RING_ACTHD_UDW(0),		REG_64BIT_HI_DW, 0,	0,	0,	"ACTHD"}, \
>>  	{ RING_BBADDR(0),		REG_64BIT_LOW_DW, 0,	0,	0,	NULL}, \
>> @@ -149,6 +150,9 @@ struct __guc_capture_parsed_output {
>>  	{ SFC_DONE(2),			0,	0,	0,	0,	"SFC_DONE[2]"}, \
>>  	{ SFC_DONE(3),			0,	0,	0,	0,	"SFC_DONE[3]"}
>>
>> +#define XE3P_BASE_ENGINE_INSTANCE \
>> +	{ RING_CSMQDEBUG(0),		REG_32BIT,	0,	0,	0,	"CSMQDEBUG"}
>> +
>>  /* XE_LP Global */
>>  static const struct __guc_mmio_reg_descr xe_lp_global_regs[] = {
>>  	COMMON_XELP_BASE_GLOBAL,
>> @@ -195,6 +199,36 @@ static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = {
>>  	COMMON_BASE_ENGINE_INSTANCE,
>>  };
>>
>> +/* Render / Compute Per-Engine-Instance */
>> +static const struct __guc_mmio_reg_descr xe3p_rc_inst_regs[] = {
>> +	COMMON_BASE_ENGINE_INSTANCE,
>> +	XE3P_BASE_ENGINE_INSTANCE,
>> +};
>> +
>> +/* Media Decode/Encode Per-Engine-Instance */
>
>I'm also wondering if we really need to dump it for the vcs/vecs/gsc
>engines; although the register technically exists there, those engines
>don't actually support MQ so maybe it's only worth dumping on the CCS
>and BCS engines?
>
>> +static const struct __guc_mmio_reg_descr xe3p_vd_inst_regs[] = {
>> +	COMMON_BASE_ENGINE_INSTANCE,
>> +	XE3P_BASE_ENGINE_INSTANCE,
>> +};
>> +
>> +/* Video Enhancement Per-Engine-Instance */
>> +static const struct __guc_mmio_reg_descr xe3p_vec_inst_regs[] = {
>> +	COMMON_BASE_ENGINE_INSTANCE,
>> +	XE3P_BASE_ENGINE_INSTANCE,
>> +};
>> +
>> +/* Blitter Per-Engine-Instance */
>> +static const struct __guc_mmio_reg_descr xe3p_blt_inst_regs[] = {
>> +	COMMON_BASE_ENGINE_INSTANCE,
>> +	XE3P_BASE_ENGINE_INSTANCE,
>> +};
>> +
>> +/* XE3P - GSC Per-Engine-Instance */
>> +static const struct __guc_mmio_reg_descr xe3p_gsc_inst_regs[] = {
>> +	COMMON_BASE_ENGINE_INSTANCE,
>> +	XE3P_BASE_ENGINE_INSTANCE,
>> +};
>> +
>>  /*
>>   * Empty list to prevent warnings about unknown class/instance types
>>   * as not all class/instance types have entries on all platforms.
>> @@ -245,6 +279,21 @@ static const struct __guc_mmio_reg_descr_group xe_hpg_lists[] = {
>>  	{}
>>  };
>>
>> + /* List of lists for graphic product version >= 3500 */
>> +static const struct __guc_mmio_reg_descr_group xe3p_lists[] = {
>> +	MAKE_REGLIST(xe_lp_global_regs, PF, GLOBAL, 0),
>> +	MAKE_REGLIST(xe_hpg_rc_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
>> +	MAKE_REGLIST(xe3p_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE),
>> +	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEO),
>> +	MAKE_REGLIST(xe3p_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEO),
>> +	MAKE_REGLIST(xe_vec_class_regs, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
>> +	MAKE_REGLIST(xe3p_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE),
>> +	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_BLITTER),
>> +	MAKE_REGLIST(xe3p_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
>> +	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
>> +	MAKE_REGLIST(xe3p_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
>> +	{}
>> +};
>>  static const char * const capture_list_type_names[] = {
>>  	"Global",
>>  	"Class",
>> @@ -292,7 +341,9 @@ guc_capture_remove_stale_matches_from_list(struct xe_guc_state_capture *gc,
>>  static const struct __guc_mmio_reg_descr_group *
>>  guc_capture_get_device_reglist(struct xe_device *xe)
>>  {
>> -	if (GRAPHICS_VERx100(xe) >= 1255)
>> +	if (GRAPHICS_VERx100(xe) >= 3500)
>
>Since there's no IP with a version of exactly 35.00, I'd just do
>"GRAPHICS_VER(xe) >= 35" to avoid any confusion.  Also in the comment a
>little bit farther up, I'd replace the "graphic product version >= 3500"
>with "Xe3p and beyond."

thanks
Lucas De Marchi

>
>
>Matt
>
>> +		return xe3p_lists;
>> +	else if (GRAPHICS_VERx100(xe) >= 1255)
>>  		return xe_hpg_lists;
>>  	else
>>  		return xe_lp_lists;
>>
>> --
>> 2.51.0
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [PATCH 03/23] drm/xe/xe3p_lpm: Configure MAIN_GAMCTRL_QUEUE_SELECT

[Vivekanandan, Balasubramani]

On 14.10.2025 21:28, Lucas De Marchi wrote:
> On Tue, Oct 14, 2025 at 09:34:03AM -0700, Matt Roper wrote:
> > On Mon, Oct 13, 2025 at 08:24:35PM -0700, Lucas De Marchi wrote:
> > > From: Brian Welty <brian.welty@intel.com>
> > > 
> > > Starting from Xe3p, there are two different copies of some of the GAM
> > > registers:  the traditional MCR variant at their old locations, and a
> > > new unicast copy known as "main_gamctrl."  The Xe driver doesn't use
> > > these registers directly, but we need to instruct the GuC on which set
> > > it should use.  Since the new, unicast registers are preferred (since
> > > they avoid the need for unnecessary MCR synchronization), set a new GuC
> > > feature flag, GUC_CTL_MAIN_GAMCTRL_QUEUES to convey this decision.  A
> > > new helper function, xe_guc_using_main_gamctrl_queues(), is added for
> > > use in the 3 independent places that need to handle configuration of the
> > > new reporting queues.
> > > 
> > > The mmio write to enable the main gamctl is only done during the general
> > > GuC upload.  The gamctrl registers are not accessed by the GuC during
> > > hwconfig load.
> > > 
> > > Last, the ADS blob for communicating the queue addresses contains both a
> > > DPA and GGTT offset. The GuC documentation states that DPA is now MBZ
> > > when using the MAIN_GAMCTRL queues.
> > > 
> > > Signed-off-by: Brian Welty <brian.welty@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > >  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  3 +++
> > >  drivers/gpu/drm/xe/xe_gt.h           |  6 ++++++
> > >  drivers/gpu/drm/xe/xe_guc.c          | 27 +++++++++++++++++++++++++++
> > >  drivers/gpu/drm/xe/xe_guc.h          |  1 +
> > >  drivers/gpu/drm/xe/xe_guc_ads.c      |  6 +++++-
> > >  drivers/gpu/drm/xe/xe_guc_fwif.h     |  1 +
> > >  6 files changed, 43 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > > index 51f2a03847f9d..47e13a3fb9072 100644
> > > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > > @@ -545,6 +545,9 @@
> > >  #define SARB_CHICKEN1				XE_REG_MCR(0xe90c)
> > >  #define   COMP_CKN_IN				REG_GENMASK(30, 29)
> > > 
> > > +#define MAIN_GAMCTRL_MODE			XE_REG(0xef00)
> > > +#define   MAIN_GAMCTRL_QUEUE_SELECT		REG_BIT(0)
> > > +
> > >  #define RCU_MODE				XE_REG(0x14800, XE_REG_OPTION_MASKED)
> > >  #define   RCU_MODE_FIXED_SLICE_CCS_MODE		REG_BIT(1)
> > >  #define   RCU_MODE_CCS_ENABLE			REG_BIT(0)
> > > diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h
> > > index 5df2ffe3ff838..9d710049da455 100644
> > > --- a/drivers/gpu/drm/xe/xe_gt.h
> > > +++ b/drivers/gpu/drm/xe/xe_gt.h
> > > @@ -22,6 +22,12 @@
> > > 
> > >  #define CCS_MASK(gt) (((gt)->info.engine_mask & XE_HW_ENGINE_CCS_MASK) >> XE_HW_ENGINE_CCS0)
> > > 
> > > +#define GT_VER(gt) ({ \
> > > +	typeof(gt) gt_ = (gt); \
> > > +	struct xe_device *xe = gt_to_xe(gt_); \
> > > +	xe_gt_is_media_type(gt_) ? MEDIA_VER(xe) : GRAPHICS_VER(xe); \
> > > +})
> > > +
> > >  extern struct fault_attr gt_reset_failure;
> > >  static inline bool xe_fault_inject_gt_reset(void)
> > >  {
> > > diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> > > index d94490979adc0..37e3735f34e63 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc.c
> > > +++ b/drivers/gpu/drm/xe/xe_guc.c
> > > @@ -91,6 +91,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
> > >  	if (xe_configfs_get_psmi_enabled(to_pci_dev(xe->drm.dev)))
> > >  		flags |= GUC_CTL_ENABLE_PSMI_LOGGING;
> > > 
> > > +	if (xe_guc_using_main_gamctrl_queues(guc))
> > > +		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
> > > +
> > >  	return flags;
> > >  }
> > > 
> > > @@ -1255,8 +1258,13 @@ int xe_guc_min_load_for_hwconfig(struct xe_guc *guc)
> > > 
> > >  int xe_guc_upload(struct xe_guc *guc)
> > >  {
> > > +	struct xe_gt *gt = guc_to_gt(guc);
> > > +
> > >  	xe_guc_ads_populate(&guc->ads);
> > > 
> > > +	if (xe_guc_using_main_gamctrl_queues(guc))
> > > +		xe_mmio_write32(&gt->mmio, MAIN_GAMCTRL_MODE, MAIN_GAMCTRL_QUEUE_SELECT);
> > > +
> > >  	return __xe_guc_upload(guc);
> > >  }
> > > 
> > > @@ -1657,6 +1665,25 @@ void xe_guc_declare_wedged(struct xe_guc *guc)
> > >  	xe_guc_submit_wedge(guc);
> > >  }
> > > 
> > > +/**
> > > + * xe_guc_using_main_gamctrl_queues() - Detect which reporting queues to use.
> > > + * @guc: The GuC object
> > > + *
> > > + * For Xe3p and beyond, we want to program the hardware to use the
> > > + * "Main GAMCTRL queue" rather than the legacy queue before we upload
> > > + * the GuC firmware.  This will allow the GuC to use a new set of
> > > + * registers for pagefault handling and avoid some unnecessary
> > > + * complications with MCR register range handling.
> > > + *
> > > + * Return: true if can use new main gamctrl queues.
> > > + */
> > > +bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc)
> > > +{
> > > +	struct xe_gt *gt = guc_to_gt(guc);
> > > +
> > > +	return GT_VER(gt) >= 35;
> > 
> > Revisiting the spec on this, I'm not sure whether using GT_VER() here is
> > actually the right thing to do.  As far as I can see, the media GT does
> > not actually have a "main gamctrl" register range at all (i.e., bspec
> > 76445 only lists MCR gamctrl ranges, and 0x38EF00-0x38EFFF falls within
> > a reserved/unused block).  That means that registers like
> 
> true
> 
> > MAIN_GAMCTRL_MODE that we're trying to write during xe_guc_upload above
> 
> We do have MAIN_GAMCTRL_MODE for xe3p_lpm in bspec 73540.
> The tagging is odd, but there is a reference to the register at
> 0x38EF00. It wouldn't make sense to have a 0x38xxxx register instance
> for primary/graphics GT.
> 
> So either
> 
> 1) we don't have it like you said
> 2) we have it and there's something missing in the MCR ranges
> 
> > don't actually exist for the media GT.  Furthermore, the tagging on the
> > register detail page 73540 also seems to imply that this only applies to
> > the primary/graphics GT.
> 
> so... in that case we'd need to check both the gt type and graphics ver,
> so we load GuC with those different flags. I will take a shot at that
> and check if anything breaks.
> 
> Bala, since you did the patch following this, do you remember of
> anything related to this?

There seems to be a conflict between the Bspec and the HSD. HSD
16017994409 and the HAS claim the MainGAMCTRL is supported in Xe3p Media
IP whereas the Bspec page 73542 and the Steering table show the
MainGAMCTRL register range as not available for Xe3p Media.

For me it looks like a Bspec update issue. We have tested and verified
the current implementation which enables MainGAMCTRL for Media.
I would say lets keep the code as it is though it conflicts with the
spec and raise a Bspec issue to get it clarified.

Regards,
Bala

> 
> Lucas De Marchi
> 
> > 
> > 
> > Matt
> > 
> > > +}
> > > +
> > >  #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
> > >  #include "tests/xe_guc_g2g_test.c"
> > >  #endif
> > > diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h
> > > index 1cca05967e621..e2d4c5f44ae34 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc.h
> > > +++ b/drivers/gpu/drm/xe/xe_guc.h
> > > @@ -52,6 +52,7 @@ void xe_guc_stop_prepare(struct xe_guc *guc);
> > >  void xe_guc_stop(struct xe_guc *guc);
> > >  int xe_guc_start(struct xe_guc *guc);
> > >  void xe_guc_declare_wedged(struct xe_guc *guc);
> > > +bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc);
> > > 
> > >  #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
> > >  int xe_guc_g2g_test_notification(struct xe_guc *guc, u32 *payload, u32 len);
> > > diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> > > index 22ac2a8b74c80..bcb85a1bf26d9 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> > > +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> > > @@ -820,16 +820,20 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
> > >  static void guc_um_init_params(struct xe_guc_ads *ads)
> > >  {
> > >  	u32 um_queue_offset = guc_ads_um_queues_offset(ads);
> > > +	struct xe_guc *guc = ads_to_guc(ads);
> > >  	u64 base_dpa;
> > >  	u32 base_ggtt;
> > > +	bool with_dpa;
> > >  	int i;
> > > 
> > > +	with_dpa = !xe_guc_using_main_gamctrl_queues(guc);
> > > +
> > >  	base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset;
> > >  	base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset;
> > > 
> > >  	for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) {
> > >  		ads_blob_write(ads, um_init_params.queue_params[i].base_dpa,
> > > -			       base_dpa + (i * GUC_UM_QUEUE_SIZE));
> > > +			       with_dpa ? (base_dpa + (i * GUC_UM_QUEUE_SIZE)) : 0);
> > >  		ads_blob_write(ads, um_init_params.queue_params[i].base_ggtt_address,
> > >  			       base_ggtt + (i * GUC_UM_QUEUE_SIZE));
> > >  		ads_blob_write(ads, um_init_params.queue_params[i].size_in_bytes,
> > > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > index 50c4c2406132e..c90dd266e9cf9 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > @@ -113,6 +113,7 @@ struct guc_update_exec_queue_policy {
> > >  #define   GUC_CTL_ENABLE_SLPC		BIT(2)
> > >  #define   GUC_CTL_ENABLE_LITE_RESTORE	BIT(4)
> > >  #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
> > > +#define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
> > >  #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
> > > 
> > >  #define GUC_CTL_DEBUG			3
> > > 
> > > --
> > > 2.51.0
> > > 
> > 
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation

Re: [PATCH 05/23] drm/xe/xe3p_lpm: Stop reading the CTC_MODE register

[Vivekanandan, Balasubramani]

On 14.10.2025 22:41, Lucas De Marchi wrote:
> On Tue, Oct 14, 2025 at 09:52:11AM -0700, Matt Roper wrote:
> > On Tue, Oct 14, 2025 at 05:28:48PM +0530, Shekhar Chauhan wrote:
> > > 
> > > On 10/14/2025 8:54, Lucas De Marchi wrote:
> > > > From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > > >
> > > > CTC_MODE register is removed by Xe3p.  Stop reading that register on
> > > > Xe3p and later platforms.
> > > >
> > > > Bspec: 62395
> > > 
> > > Again, maybe I'm referencing the Bspec in a wrong way, but I do see this
> > > register existing for IP 35. Maybe a possible tagging issue in the Bspec?
> > > Can someone comment here, if I'm missing something.
> > 
> > So looking a bit closer based on your comment, I think maybe this should
> > actually be a GRAPHICS_VER() test rather than a GT_VER() test.  It gets
> > a bit confusing since the bspec website still tries to print stuff out
> > in a platform-based manner, which makes it hard to follow exactly which
> > IP versions and GTs are actually relevant.  In this case the first
> > REMOVEDBY() tag listed is what documents the removal of the CTC_MODE
> > register, but it appears that tag only applies to primary GT; the media
> > GT is not included by the change referenced.  And then if you look
> > through the jumble of platform names that come after that, it does
> > indeed appear that media is still listed as having the register, but the
> > primary GT no longer appears in the list for platforms with Xe3p IP.
> > 
> > So maybe this is another case where we should be using GRAPHICS_VER
> > instead of GT_VER.  I'm not sure it really matters too much though since
> > we don't actually use the register for anything, except to complain
> > about a condition we expect to never show up.
> 
> maybe at this point we should just drop the entire thing?
> It's not supported for xe2/xe3, it's dropped for xe3p. It's supported
> for unofficially supported platforms, but we don't really know what to
> do in that case.
> 
> So I think it'd be safe to just drop the entire function and now worry
> about what is the exact gt version. Thoughts?

+1 from me to complete remove it.

Regards,
Bala

> 
> Lucas De Marchi
> 
> > 
> > 
> > Matt
> > 
> > > 
> > > -shekhar
> > > 
> > > > Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > ---
> > > >   drivers/gpu/drm/xe/xe_gt_clock.c | 4 ++++
> > > >   1 file changed, 4 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
> > > > index 4f011d1573c65..26052710be8a7 100644
> > > > --- a/drivers/gpu/drm/xe/xe_gt_clock.c
> > > > +++ b/drivers/gpu/drm/xe/xe_gt_clock.c
> > > > @@ -57,6 +57,10 @@ static void read_crystal_clock(struct xe_gt *gt, u32 rpm_config_reg, u32 *freq,
> > > >   static void check_ctc_mode(struct xe_gt *gt)
> > > >   {
> > > > +	/* CTC_MODE register is removed by Xe3p */
> > > > +	if (GT_VER(gt) >= 35)
> > > > +		return;
> > > > +
> > > >   	/*
> > > >   	 * CTC_MODE[0] = 1 is definitely not supported for Xe2 and later
> > > >   	 * platforms.  In theory it could be a valid setting for pre-Xe2
> > > >
> > 
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation

Re: [PATCH 07/23] drm/xe/xe3p_lpm: Handle MCR steering

[Vivekanandan, Balasubramani]

On 13.10.2025 20:24, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Xe3p_LPM's MCR steering has the same ranges and behavior as Xe3_LPM.
> However one register range that was reserved on Xe3_LPM has now become a
> unicast range (0x384200-0x38427F), so we need to stop consolidating the
> adjacent MCR ranges into a single table entry in the table.  With this
> change to the Xe3_LPM table, we can continue to use the same table for
> both IP families.
> 
> While we're touching this table, take the opportunity to fix a
> whitespace mistake and clarify that one of the other consolidated range
> entries includes a reserved range.
> 
> Bspec: 76445
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

LGTM.

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_gt_mcr.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
> index 8fb1cae917244..e1a2b38fc2a86 100644
> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
> @@ -236,12 +236,13 @@ static const struct xe_mmio_range xe2lpm_instance0_steering_table[] = {
>  };
>  
>  static const struct xe_mmio_range xe3lpm_instance0_steering_table[] = {
> -	{ 0x384000, 0x3847DF },         /* GAM, rsvd, GAM */
> +	{ 0x384000, 0x3841FF },         /* GAM */
> +	{ 0x384400, 0x3847DF },         /* GAM */
>  	{ 0x384900, 0x384AFF },         /* GAM */
>  	{ 0x389560, 0x3895FF },         /* MEDIAINF */
>  	{ 0x38B600, 0x38B8FF },         /* L3BANK */
>  	{ 0x38C800, 0x38D07F },         /* GAM, MEDIAINF */
> -	{ 0x38D0D0, 0x38F0FF },		/* MEDIAINF, GAM */
> +	{ 0x38D0D0, 0x38F0FF },         /* MEDIAINF, rsvd, GAM */
>  	{ 0x393C00, 0x393C7F },         /* MEDIAINF */
>  	{},
>  };
> 
> -- 
> 2.51.0
> 

Re: [PATCH 08/23] drm/xe/xe3p: Stop programming RCU_MODE's fixed slice mode setting

[Vivekanandan, Balasubramani]

On 13.10.2025 20:24, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Since the hardware load balancing is no longer supported, the
> programming in RCU_MODE is no longer necessary.
> 
> Bspec: 60382
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

LGTM

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_hw_engine.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 1cf623b4a5bcc..5544d91c21e8e 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -349,6 +349,13 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
>  static bool xe_hw_engine_match_fixed_cslice_mode(const struct xe_gt *gt,
>  						 const struct xe_hw_engine *hwe)
>  {
> +	/*
> +	 * Xe3p no longer supports load balance mode, so "fixed cslice" mode
> +	 * is automatic and no RCU_MODE programming is required.
> +	 */
> +	if (GRAPHICS_VER(gt_to_xe(gt)) >= 35)
> +		return false;
> +
>  	return xe_gt_ccs_mode_enabled(gt) &&
>  	       xe_rtp_match_first_render_or_compute(gt, hwe);
>  }
> 
> -- 
> 2.51.0
> 

Re: [PATCH 03/23] drm/xe/xe3p_lpm: Configure MAIN_GAMCTRL_QUEUE_SELECT

[Lucas De Marchi]

On Wed, Oct 15, 2025 at 12:06:55PM +0530, Vivekanandan, Balasubramani wrote:
>On 14.10.2025 21:28, Lucas De Marchi wrote:
>> On Tue, Oct 14, 2025 at 09:34:03AM -0700, Matt Roper wrote:
>> > On Mon, Oct 13, 2025 at 08:24:35PM -0700, Lucas De Marchi wrote:
>> > > From: Brian Welty <brian.welty@intel.com>
>> > >
>> > > Starting from Xe3p, there are two different copies of some of the GAM
>> > > registers:  the traditional MCR variant at their old locations, and a
>> > > new unicast copy known as "main_gamctrl."  The Xe driver doesn't use
>> > > these registers directly, but we need to instruct the GuC on which set
>> > > it should use.  Since the new, unicast registers are preferred (since
>> > > they avoid the need for unnecessary MCR synchronization), set a new GuC
>> > > feature flag, GUC_CTL_MAIN_GAMCTRL_QUEUES to convey this decision.  A
>> > > new helper function, xe_guc_using_main_gamctrl_queues(), is added for
>> > > use in the 3 independent places that need to handle configuration of the
>> > > new reporting queues.
>> > >
>> > > The mmio write to enable the main gamctl is only done during the general
>> > > GuC upload.  The gamctrl registers are not accessed by the GuC during
>> > > hwconfig load.
>> > >
>> > > Last, the ADS blob for communicating the queue addresses contains both a
>> > > DPA and GGTT offset. The GuC documentation states that DPA is now MBZ
>> > > when using the MAIN_GAMCTRL queues.
>> > >
>> > > Signed-off-by: Brian Welty <brian.welty@intel.com>
>> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> > > ---
>> > >  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  3 +++
>> > >  drivers/gpu/drm/xe/xe_gt.h           |  6 ++++++
>> > >  drivers/gpu/drm/xe/xe_guc.c          | 27 +++++++++++++++++++++++++++
>> > >  drivers/gpu/drm/xe/xe_guc.h          |  1 +
>> > >  drivers/gpu/drm/xe/xe_guc_ads.c      |  6 +++++-
>> > >  drivers/gpu/drm/xe/xe_guc_fwif.h     |  1 +
>> > >  6 files changed, 43 insertions(+), 1 deletion(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> > > index 51f2a03847f9d..47e13a3fb9072 100644
>> > > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> > > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> > > @@ -545,6 +545,9 @@
>> > >  #define SARB_CHICKEN1				XE_REG_MCR(0xe90c)
>> > >  #define   COMP_CKN_IN				REG_GENMASK(30, 29)
>> > >
>> > > +#define MAIN_GAMCTRL_MODE			XE_REG(0xef00)
>> > > +#define   MAIN_GAMCTRL_QUEUE_SELECT		REG_BIT(0)
>> > > +
>> > >  #define RCU_MODE				XE_REG(0x14800, XE_REG_OPTION_MASKED)
>> > >  #define   RCU_MODE_FIXED_SLICE_CCS_MODE		REG_BIT(1)
>> > >  #define   RCU_MODE_CCS_ENABLE			REG_BIT(0)
>> > > diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h
>> > > index 5df2ffe3ff838..9d710049da455 100644
>> > > --- a/drivers/gpu/drm/xe/xe_gt.h
>> > > +++ b/drivers/gpu/drm/xe/xe_gt.h
>> > > @@ -22,6 +22,12 @@
>> > >
>> > >  #define CCS_MASK(gt) (((gt)->info.engine_mask & XE_HW_ENGINE_CCS_MASK) >> XE_HW_ENGINE_CCS0)
>> > >
>> > > +#define GT_VER(gt) ({ \
>> > > +	typeof(gt) gt_ = (gt); \
>> > > +	struct xe_device *xe = gt_to_xe(gt_); \
>> > > +	xe_gt_is_media_type(gt_) ? MEDIA_VER(xe) : GRAPHICS_VER(xe); \
>> > > +})
>> > > +
>> > >  extern struct fault_attr gt_reset_failure;
>> > >  static inline bool xe_fault_inject_gt_reset(void)
>> > >  {
>> > > diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>> > > index d94490979adc0..37e3735f34e63 100644
>> > > --- a/drivers/gpu/drm/xe/xe_guc.c
>> > > +++ b/drivers/gpu/drm/xe/xe_guc.c
>> > > @@ -91,6 +91,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
>> > >  	if (xe_configfs_get_psmi_enabled(to_pci_dev(xe->drm.dev)))
>> > >  		flags |= GUC_CTL_ENABLE_PSMI_LOGGING;
>> > >
>> > > +	if (xe_guc_using_main_gamctrl_queues(guc))
>> > > +		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
>> > > +
>> > >  	return flags;
>> > >  }
>> > >
>> > > @@ -1255,8 +1258,13 @@ int xe_guc_min_load_for_hwconfig(struct xe_guc *guc)
>> > >
>> > >  int xe_guc_upload(struct xe_guc *guc)
>> > >  {
>> > > +	struct xe_gt *gt = guc_to_gt(guc);
>> > > +
>> > >  	xe_guc_ads_populate(&guc->ads);
>> > >
>> > > +	if (xe_guc_using_main_gamctrl_queues(guc))
>> > > +		xe_mmio_write32(&gt->mmio, MAIN_GAMCTRL_MODE, MAIN_GAMCTRL_QUEUE_SELECT);
>> > > +
>> > >  	return __xe_guc_upload(guc);
>> > >  }
>> > >
>> > > @@ -1657,6 +1665,25 @@ void xe_guc_declare_wedged(struct xe_guc *guc)
>> > >  	xe_guc_submit_wedge(guc);
>> > >  }
>> > >
>> > > +/**
>> > > + * xe_guc_using_main_gamctrl_queues() - Detect which reporting queues to use.
>> > > + * @guc: The GuC object
>> > > + *
>> > > + * For Xe3p and beyond, we want to program the hardware to use the
>> > > + * "Main GAMCTRL queue" rather than the legacy queue before we upload
>> > > + * the GuC firmware.  This will allow the GuC to use a new set of
>> > > + * registers for pagefault handling and avoid some unnecessary
>> > > + * complications with MCR register range handling.
>> > > + *
>> > > + * Return: true if can use new main gamctrl queues.
>> > > + */
>> > > +bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc)
>> > > +{
>> > > +	struct xe_gt *gt = guc_to_gt(guc);
>> > > +
>> > > +	return GT_VER(gt) >= 35;
>> >
>> > Revisiting the spec on this, I'm not sure whether using GT_VER() here is
>> > actually the right thing to do.  As far as I can see, the media GT does
>> > not actually have a "main gamctrl" register range at all (i.e., bspec
>> > 76445 only lists MCR gamctrl ranges, and 0x38EF00-0x38EFFF falls within
>> > a reserved/unused block).  That means that registers like
>>
>> true
>>
>> > MAIN_GAMCTRL_MODE that we're trying to write during xe_guc_upload above
>>
>> We do have MAIN_GAMCTRL_MODE for xe3p_lpm in bspec 73540.
>> The tagging is odd, but there is a reference to the register at
>> 0x38EF00. It wouldn't make sense to have a 0x38xxxx register instance
>> for primary/graphics GT.
>>
>> So either
>>
>> 1) we don't have it like you said
>> 2) we have it and there's something missing in the MCR ranges
>>
>> > don't actually exist for the media GT.  Furthermore, the tagging on the
>> > register detail page 73540 also seems to imply that this only applies to
>> > the primary/graphics GT.
>>
>> so... in that case we'd need to check both the gt type and graphics ver,
>> so we load GuC with those different flags. I will take a shot at that
>> and check if anything breaks.
>>
>> Bala, since you did the patch following this, do you remember of
>> anything related to this?
>
>There seems to be a conflict between the Bspec and the HSD. HSD
>16017994409 and the HAS claim the MainGAMCTRL is supported in Xe3p Media
>IP whereas the Bspec page 73542 and the Steering table show the
>MainGAMCTRL register range as not available for Xe3p Media.
>
>For me it looks like a Bspec update issue. We have tested and verified
>the current implementation which enables MainGAMCTRL for Media.
>I would say lets keep the code as it is though it conflicts with the
>spec and raise a Bspec issue to get it clarified.

I'm circling this back with HW and Spec people. I also did some changes
local changes to test. Although since the old queues are still valid, I
guess it will just pass, but without this optimization. On the other
hand, I'd expect it to not work at all with the current code if it
didn't apply to media.

Another point is that we can delay this patch a little bit, since the
next patch turns this off for media with the special bits set.

thanks
Lucas De Marchi

Re: [PATCH 21/23] drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs

[Lucas De Marchi]

On Wed, Oct 15, 2025 at 08:22:19AM +0530, Shekhar Chauhan wrote:
>
>On 10/14/2025 23:44, Matt Roper wrote:
>>On Tue, Oct 14, 2025 at 01:39:39PM +0530, Shekhar Chauhan wrote:
>>>On 10/14/2025 8:54, Lucas De Marchi wrote:
>>>>From: Matt Roper <matthew.d.roper@intel.com>
>>>>
>>>>The compression overfetch tuning settings only apply to platforms that
>>>>support FlatCCS.  In Xe3p_XPC (and any future IPs that also lack
>>>>compression) some of the registers being adjusted by this tuning will
>>>>not exist or may have been repurposed for something else, so we should
>>>>take care not to try to program them.
>>>>
>>>>Note that our xe_rtp_match_has_flatccs() function will also return false
>>>>on platforms that do have FlatCCS in the hardware design, but have
>>>>compression manually disabled in the BIOS.  On such platforms the
>>>>registers still exist (and it would be fine to continue programming
>>>>them), but they would have no effect, so skipping that tuning is also
>>>>safe.
>>>>
>>>>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>>The patch in itself looks fine to me, but, the patch doesn't specifically
>>>play only around Xe3p_XPC. Maybe we can move this patch out of the current
>>>series, or if we wish to keep it here, can we instead drop the xe3p_xpc from
>>>the prefix? Thoughts?
>>Aside from PVC (which is Xe1 and not relevant to these tuning settings),
>>Xe3p_XPC is the only IP we have without FlatCCS in the design, so at the
>>moment this patch is specific to Xe3p_XPC.  As a general architecture
>>though, if we eventually wind up with other IPs down the road that also
>>lack FlatCCS, then these tuning settings will also not apply to them for
>>the same reasons.
>>
>>
>>Matt
>
>Okay, makes sense, I'm still skeptical on whether this should be named 
>with the prefix Xe3p_XPC if we expect it to carry it's effect to other 
>future platforms as well. For that reason, I believe, the commit title 
>can be 'drm/xe: Skip compression tuning on platforms without flatccs'.

Makes sense changing it, but I don't mind either way since we are also
adding Xe3p_XPC in the same series so it's clear why we are doing so.

Lucas De Marchi

>This in itself engulfs Xe3p_XPC (and any other future platforms). But, 
>consider this feedback as only a nitpick.
>
>Since the changes already look good,
>
>Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
>
>>
>>>>---
>>>>   drivers/gpu/drm/xe/xe_rtp.c    |  6 ++++++
>>>>   drivers/gpu/drm/xe/xe_rtp.h    | 10 ++++++++++
>>>>   drivers/gpu/drm/xe/xe_tuning.c |  9 ++++++---
>>>>   3 files changed, 22 insertions(+), 3 deletions(-)
>>>>
>>>>diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
>>>>index b5f430d59f805..22a879270c1ec 100644
>>>>--- a/drivers/gpu/drm/xe/xe_rtp.c
>>>>+++ b/drivers/gpu/drm/xe/xe_rtp.c
>>>>@@ -376,3 +376,9 @@ bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,
>>>>   {
>>>>   	return xe_gt_has_discontiguous_dss_groups(gt);
>>>>   }
>>>>+
>>>>+bool xe_rtp_match_has_flat_ccs(const struct xe_gt *gt,
>>>>+			      const struct xe_hw_engine *hwe)
>>>>+{
>>>>+	return gt_to_xe(gt)->info.has_flat_ccs;
>>>>+}
>>>>diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
>>>>index ac12ddf6cde6d..92f0d16110dd5 100644
>>>>--- a/drivers/gpu/drm/xe/xe_rtp.h
>>>>+++ b/drivers/gpu/drm/xe/xe_rtp.h
>>>>@@ -483,4 +483,14 @@ bool xe_rtp_match_psmi_enabled(const struct xe_gt *gt,
>>>>   bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,
>>>>   						  const struct xe_hw_engine *hwe);
>>>>+/**
>>>>+ * xe_rtp_match_has_flat_ccs - Match when platform has FlatCCS compression
>>>>+ * @gt: GT structure
>>>>+ * @hwe: Engine instance
>>>>+ *
>>>>+ * Returns: true if platform has FlatCCS compression, false otherwise
>>>>+ */
>>>>+bool xe_rtp_match_has_flat_ccs(const struct xe_gt *gt,
>>>>+			       const struct xe_hw_engine *hwe);
>>>>+
>>>>   #endif
>>>>diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
>>>>index fd58ea5e78bf6..7c140d8cb1e07 100644
>>>>--- a/drivers/gpu/drm/xe/xe_tuning.c
>>>>+++ b/drivers/gpu/drm/xe/xe_tuning.c
>>>>@@ -40,7 +40,8 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>>>>   				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
>>>>   	},
>>>>   	{ XE_RTP_NAME("Tuning: Compression Overfetch"),
>>>>-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
>>>>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
>>>>+		       FUNC(xe_rtp_match_has_flat_ccs)),
>>>>   	  XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
>>>>   			 SET(CCCHKNREG1, L3CMPCTRL))
>>>>   	},
>>>>@@ -58,12 +59,14 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>>>>   	  XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3, COMPPWOVERFETCHEN))
>>>>   	},
>>>>   	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
>>>>-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
>>>>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
>>>>+		       FUNC(xe_rtp_match_has_flat_ccs)),
>>>>   	  XE_RTP_ACTIONS(SET(L3SQCREG2,
>>>>   			     COMPMEMRD256BOVRFETCHEN))
>>>>   	},
>>>>   	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only - media"),
>>>>-	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
>>>>+	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED),
>>>>+		       FUNC(xe_rtp_match_has_flat_ccs)),
>>>>   	  XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
>>>>   			     COMPMEMRD256BOVRFETCHEN))
>>>>   	},
>>>>

Re: [PATCH 03/23] drm/xe/xe3p_lpm: Configure MAIN_GAMCTRL_QUEUE_SELECT

[Matt Roper]

On Tue, Oct 14, 2025 at 09:28:19PM -0500, Lucas De Marchi wrote:
> On Tue, Oct 14, 2025 at 09:34:03AM -0700, Matt Roper wrote:
> > On Mon, Oct 13, 2025 at 08:24:35PM -0700, Lucas De Marchi wrote:
> > > From: Brian Welty <brian.welty@intel.com>
> > > 
> > > Starting from Xe3p, there are two different copies of some of the GAM
> > > registers:  the traditional MCR variant at their old locations, and a
> > > new unicast copy known as "main_gamctrl."  The Xe driver doesn't use
> > > these registers directly, but we need to instruct the GuC on which set
> > > it should use.  Since the new, unicast registers are preferred (since
> > > they avoid the need for unnecessary MCR synchronization), set a new GuC
> > > feature flag, GUC_CTL_MAIN_GAMCTRL_QUEUES to convey this decision.  A
> > > new helper function, xe_guc_using_main_gamctrl_queues(), is added for
> > > use in the 3 independent places that need to handle configuration of the
> > > new reporting queues.
> > > 
> > > The mmio write to enable the main gamctl is only done during the general
> > > GuC upload.  The gamctrl registers are not accessed by the GuC during
> > > hwconfig load.
> > > 
> > > Last, the ADS blob for communicating the queue addresses contains both a
> > > DPA and GGTT offset. The GuC documentation states that DPA is now MBZ
> > > when using the MAIN_GAMCTRL queues.
> > > 
> > > Signed-off-by: Brian Welty <brian.welty@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > >  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  3 +++
> > >  drivers/gpu/drm/xe/xe_gt.h           |  6 ++++++
> > >  drivers/gpu/drm/xe/xe_guc.c          | 27 +++++++++++++++++++++++++++
> > >  drivers/gpu/drm/xe/xe_guc.h          |  1 +
> > >  drivers/gpu/drm/xe/xe_guc_ads.c      |  6 +++++-
> > >  drivers/gpu/drm/xe/xe_guc_fwif.h     |  1 +
> > >  6 files changed, 43 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > > index 51f2a03847f9d..47e13a3fb9072 100644
> > > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > > @@ -545,6 +545,9 @@
> > >  #define SARB_CHICKEN1				XE_REG_MCR(0xe90c)
> > >  #define   COMP_CKN_IN				REG_GENMASK(30, 29)
> > > 
> > > +#define MAIN_GAMCTRL_MODE			XE_REG(0xef00)
> > > +#define   MAIN_GAMCTRL_QUEUE_SELECT		REG_BIT(0)
> > > +
> > >  #define RCU_MODE				XE_REG(0x14800, XE_REG_OPTION_MASKED)
> > >  #define   RCU_MODE_FIXED_SLICE_CCS_MODE		REG_BIT(1)
> > >  #define   RCU_MODE_CCS_ENABLE			REG_BIT(0)
> > > diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h
> > > index 5df2ffe3ff838..9d710049da455 100644
> > > --- a/drivers/gpu/drm/xe/xe_gt.h
> > > +++ b/drivers/gpu/drm/xe/xe_gt.h
> > > @@ -22,6 +22,12 @@
> > > 
> > >  #define CCS_MASK(gt) (((gt)->info.engine_mask & XE_HW_ENGINE_CCS_MASK) >> XE_HW_ENGINE_CCS0)
> > > 
> > > +#define GT_VER(gt) ({ \
> > > +	typeof(gt) gt_ = (gt); \
> > > +	struct xe_device *xe = gt_to_xe(gt_); \
> > > +	xe_gt_is_media_type(gt_) ? MEDIA_VER(xe) : GRAPHICS_VER(xe); \
> > > +})
> > > +
> > >  extern struct fault_attr gt_reset_failure;
> > >  static inline bool xe_fault_inject_gt_reset(void)
> > >  {
> > > diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> > > index d94490979adc0..37e3735f34e63 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc.c
> > > +++ b/drivers/gpu/drm/xe/xe_guc.c
> > > @@ -91,6 +91,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
> > >  	if (xe_configfs_get_psmi_enabled(to_pci_dev(xe->drm.dev)))
> > >  		flags |= GUC_CTL_ENABLE_PSMI_LOGGING;
> > > 
> > > +	if (xe_guc_using_main_gamctrl_queues(guc))
> > > +		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
> > > +
> > >  	return flags;
> > >  }
> > > 
> > > @@ -1255,8 +1258,13 @@ int xe_guc_min_load_for_hwconfig(struct xe_guc *guc)
> > > 
> > >  int xe_guc_upload(struct xe_guc *guc)
> > >  {
> > > +	struct xe_gt *gt = guc_to_gt(guc);
> > > +
> > >  	xe_guc_ads_populate(&guc->ads);
> > > 
> > > +	if (xe_guc_using_main_gamctrl_queues(guc))
> > > +		xe_mmio_write32(&gt->mmio, MAIN_GAMCTRL_MODE, MAIN_GAMCTRL_QUEUE_SELECT);
> > > +
> > >  	return __xe_guc_upload(guc);
> > >  }
> > > 
> > > @@ -1657,6 +1665,25 @@ void xe_guc_declare_wedged(struct xe_guc *guc)
> > >  	xe_guc_submit_wedge(guc);
> > >  }
> > > 
> > > +/**
> > > + * xe_guc_using_main_gamctrl_queues() - Detect which reporting queues to use.
> > > + * @guc: The GuC object
> > > + *
> > > + * For Xe3p and beyond, we want to program the hardware to use the
> > > + * "Main GAMCTRL queue" rather than the legacy queue before we upload
> > > + * the GuC firmware.  This will allow the GuC to use a new set of
> > > + * registers for pagefault handling and avoid some unnecessary
> > > + * complications with MCR register range handling.
> > > + *
> > > + * Return: true if can use new main gamctrl queues.
> > > + */
> > > +bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc)
> > > +{
> > > +	struct xe_gt *gt = guc_to_gt(guc);
> > > +
> > > +	return GT_VER(gt) >= 35;
> > 
> > Revisiting the spec on this, I'm not sure whether using GT_VER() here is
> > actually the right thing to do.  As far as I can see, the media GT does
> > not actually have a "main gamctrl" register range at all (i.e., bspec
> > 76445 only lists MCR gamctrl ranges, and 0x38EF00-0x38EFFF falls within
> > a reserved/unused block).  That means that registers like
> 
> true
> 
> > MAIN_GAMCTRL_MODE that we're trying to write during xe_guc_upload above
> 
> We do have MAIN_GAMCTRL_MODE for xe3p_lpm in bspec 73540.
> The tagging is odd, but there is a reference to the register at
> 0x38EF00. It wouldn't make sense to have a 0x38xxxx register instance
> for primary/graphics GT.

I think this is an artifact of how the bspec's web interface is being
strained beyond its original design considerations.  0x38xxxx copies of
GT registers get listed somewhat automatically, but on platforms where
they've split things into separate "die" designators, the 0x38xxxx
register should be ignored if it _only_ applies to the "graphics" die
and isn't also tagged as existing on the die that actually holds the
media IP.  That's the case here since the media die doesn't show up in
the list of "platforms."

This is unfortunately very non-obvious and confusing.  :-(


Matt

> 
> So either
> 
> 1) we don't have it like you said
> 2) we have it and there's something missing in the MCR range
> 
> > don't actually exist for the media GT.  Furthermore, the tagging on the
> > register detail page 73540 also seems to imply that this only applies to
> > the primary/graphics GT.
> 
> so... in that case we'd need to check both the gt type and graphics ver,
> so we load GuC with those different flags. I will take a shot at that
> and check if anything breaks.
> 
> Bala, since you did the patch following this, do you remember of
> anything related to this?
> 
> Lucas De Marchi
> 
> > 
> > 
> > Matt
> > 
> > > +}
> > > +
> > >  #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
> > >  #include "tests/xe_guc_g2g_test.c"
> > >  #endif
> > > diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h
> > > index 1cca05967e621..e2d4c5f44ae34 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc.h
> > > +++ b/drivers/gpu/drm/xe/xe_guc.h
> > > @@ -52,6 +52,7 @@ void xe_guc_stop_prepare(struct xe_guc *guc);
> > >  void xe_guc_stop(struct xe_guc *guc);
> > >  int xe_guc_start(struct xe_guc *guc);
> > >  void xe_guc_declare_wedged(struct xe_guc *guc);
> > > +bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc);
> > > 
> > >  #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
> > >  int xe_guc_g2g_test_notification(struct xe_guc *guc, u32 *payload, u32 len);
> > > diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> > > index 22ac2a8b74c80..bcb85a1bf26d9 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> > > +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> > > @@ -820,16 +820,20 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
> > >  static void guc_um_init_params(struct xe_guc_ads *ads)
> > >  {
> > >  	u32 um_queue_offset = guc_ads_um_queues_offset(ads);
> > > +	struct xe_guc *guc = ads_to_guc(ads);
> > >  	u64 base_dpa;
> > >  	u32 base_ggtt;
> > > +	bool with_dpa;
> > >  	int i;
> > > 
> > > +	with_dpa = !xe_guc_using_main_gamctrl_queues(guc);
> > > +
> > >  	base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset;
> > >  	base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset;
> > > 
> > >  	for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) {
> > >  		ads_blob_write(ads, um_init_params.queue_params[i].base_dpa,
> > > -			       base_dpa + (i * GUC_UM_QUEUE_SIZE));
> > > +			       with_dpa ? (base_dpa + (i * GUC_UM_QUEUE_SIZE)) : 0);
> > >  		ads_blob_write(ads, um_init_params.queue_params[i].base_ggtt_address,
> > >  			       base_ggtt + (i * GUC_UM_QUEUE_SIZE));
> > >  		ads_blob_write(ads, um_init_params.queue_params[i].size_in_bytes,
> > > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > index 50c4c2406132e..c90dd266e9cf9 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > @@ -113,6 +113,7 @@ struct guc_update_exec_queue_policy {
> > >  #define   GUC_CTL_ENABLE_SLPC		BIT(2)
> > >  #define   GUC_CTL_ENABLE_LITE_RESTORE	BIT(4)
> > >  #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
> > > +#define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
> > >  #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
> > > 
> > >  #define GUC_CTL_DEBUG			3
> > > 
> > > --
> > > 2.51.0
> > > 
> > 
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 05/23] drm/xe/xe3p_lpm: Stop reading the CTC_MODE register

[Matt Roper]

On Wed, Oct 15, 2025 at 02:49:26PM +0530, Vivekanandan, Balasubramani wrote:
> On 14.10.2025 22:41, Lucas De Marchi wrote:
> > On Tue, Oct 14, 2025 at 09:52:11AM -0700, Matt Roper wrote:
> > > On Tue, Oct 14, 2025 at 05:28:48PM +0530, Shekhar Chauhan wrote:
> > > > 
> > > > On 10/14/2025 8:54, Lucas De Marchi wrote:
> > > > > From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > > > >
> > > > > CTC_MODE register is removed by Xe3p.  Stop reading that register on
> > > > > Xe3p and later platforms.
> > > > >
> > > > > Bspec: 62395
> > > > 
> > > > Again, maybe I'm referencing the Bspec in a wrong way, but I do see this
> > > > register existing for IP 35. Maybe a possible tagging issue in the Bspec?
> > > > Can someone comment here, if I'm missing something.
> > > 
> > > So looking a bit closer based on your comment, I think maybe this should
> > > actually be a GRAPHICS_VER() test rather than a GT_VER() test.  It gets
> > > a bit confusing since the bspec website still tries to print stuff out
> > > in a platform-based manner, which makes it hard to follow exactly which
> > > IP versions and GTs are actually relevant.  In this case the first
> > > REMOVEDBY() tag listed is what documents the removal of the CTC_MODE
> > > register, but it appears that tag only applies to primary GT; the media
> > > GT is not included by the change referenced.  And then if you look
> > > through the jumble of platform names that come after that, it does
> > > indeed appear that media is still listed as having the register, but the
> > > primary GT no longer appears in the list for platforms with Xe3p IP.
> > > 
> > > So maybe this is another case where we should be using GRAPHICS_VER
> > > instead of GT_VER.  I'm not sure it really matters too much though since
> > > we don't actually use the register for anything, except to complain
> > > about a condition we expect to never show up.
> > 
> > maybe at this point we should just drop the entire thing?
> > It's not supported for xe2/xe3, it's dropped for xe3p. It's supported
> > for unofficially supported platforms, but we don't really know what to
> > do in that case.
> > 
> > So I think it'd be safe to just drop the entire function and now worry
> > about what is the exact gt version. Thoughts?
> 
> +1 from me to complete remove it.

Ack; just dropping it sounds fine to me.  I don't believe we've ever
seen a log containing the warning that this is set.


Matt

> 
> Regards,
> Bala
> 
> > 
> > Lucas De Marchi
> > 
> > > 
> > > 
> > > Matt
> > > 
> > > > 
> > > > -shekhar
> > > > 
> > > > > Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> > > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > > ---
> > > > >   drivers/gpu/drm/xe/xe_gt_clock.c | 4 ++++
> > > > >   1 file changed, 4 insertions(+)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
> > > > > index 4f011d1573c65..26052710be8a7 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_gt_clock.c
> > > > > +++ b/drivers/gpu/drm/xe/xe_gt_clock.c
> > > > > @@ -57,6 +57,10 @@ static void read_crystal_clock(struct xe_gt *gt, u32 rpm_config_reg, u32 *freq,
> > > > >   static void check_ctc_mode(struct xe_gt *gt)
> > > > >   {
> > > > > +	/* CTC_MODE register is removed by Xe3p */
> > > > > +	if (GT_VER(gt) >= 35)
> > > > > +		return;
> > > > > +
> > > > >   	/*
> > > > >   	 * CTC_MODE[0] = 1 is definitely not supported for Xe2 and later
> > > > >   	 * platforms.  In theory it could be a valid setting for pre-Xe2
> > > > >
> > > 
> > > -- 
> > > Matt Roper
> > > Graphics Software Engineer
> > > Linux GPU Platform Enablement
> > > Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 21/23] drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs

[Shekhar Chauhan]

On 10/15/2025 20:08, Lucas De Marchi wrote:
> On Wed, Oct 15, 2025 at 08:22:19AM +0530, Shekhar Chauhan wrote:
>>
>> On 10/14/2025 23:44, Matt Roper wrote:
>>> On Tue, Oct 14, 2025 at 01:39:39PM +0530, Shekhar Chauhan wrote:
>>>> On 10/14/2025 8:54, Lucas De Marchi wrote:
>>>>> From: Matt Roper <matthew.d.roper@intel.com>
>>>>>
>>>>> The compression overfetch tuning settings only apply to platforms 
>>>>> that
>>>>> support FlatCCS.  In Xe3p_XPC (and any future IPs that also lack
>>>>> compression) some of the registers being adjusted by this tuning will
>>>>> not exist or may have been repurposed for something else, so we 
>>>>> should
>>>>> take care not to try to program them.
>>>>>
>>>>> Note that our xe_rtp_match_has_flatccs() function will also return 
>>>>> false
>>>>> on platforms that do have FlatCCS in the hardware design, but have
>>>>> compression manually disabled in the BIOS.  On such platforms the
>>>>> registers still exist (and it would be fine to continue programming
>>>>> them), but they would have no effect, so skipping that tuning is also
>>>>> safe.
>>>>>
>>>>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>>>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>>> The patch in itself looks fine to me, but, the patch doesn't 
>>>> specifically
>>>> play only around Xe3p_XPC. Maybe we can move this patch out of the 
>>>> current
>>>> series, or if we wish to keep it here, can we instead drop the 
>>>> xe3p_xpc from
>>>> the prefix? Thoughts?
>>> Aside from PVC (which is Xe1 and not relevant to these tuning 
>>> settings),
>>> Xe3p_XPC is the only IP we have without FlatCCS in the design, so at 
>>> the
>>> moment this patch is specific to Xe3p_XPC.  As a general architecture
>>> though, if we eventually wind up with other IPs down the road that also
>>> lack FlatCCS, then these tuning settings will also not apply to them 
>>> for
>>> the same reasons.
>>>
>>>
>>> Matt
>>
>> Okay, makes sense, I'm still skeptical on whether this should be 
>> named with the prefix Xe3p_XPC if we expect it to carry it's effect 
>> to other future platforms as well. For that reason, I believe, the 
>> commit title can be 'drm/xe: Skip compression tuning on platforms 
>> without flatccs'.
>
> Makes sense changing it, but I don't mind either way since we are also
> adding Xe3p_XPC in the same series so it's clear why we are doing so.
>
> Lucas De Marchi

Alright then, let's keep it this way.

-shekhar

>
>> This in itself engulfs Xe3p_XPC (and any other future platforms). 
>> But, consider this feedback as only a nitpick.
>>
>> Since the changes already look good,
>>
>> Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
>>
>>>
>>>>> ---
>>>>>   drivers/gpu/drm/xe/xe_rtp.c    |  6 ++++++
>>>>>   drivers/gpu/drm/xe/xe_rtp.h    | 10 ++++++++++
>>>>>   drivers/gpu/drm/xe/xe_tuning.c |  9 ++++++---
>>>>>   3 files changed, 22 insertions(+), 3 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/xe/xe_rtp.c 
>>>>> b/drivers/gpu/drm/xe/xe_rtp.c
>>>>> index b5f430d59f805..22a879270c1ec 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_rtp.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_rtp.c
>>>>> @@ -376,3 +376,9 @@ bool 
>>>>> xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,
>>>>>   {
>>>>>       return xe_gt_has_discontiguous_dss_groups(gt);
>>>>>   }
>>>>> +
>>>>> +bool xe_rtp_match_has_flat_ccs(const struct xe_gt *gt,
>>>>> +                  const struct xe_hw_engine *hwe)
>>>>> +{
>>>>> +    return gt_to_xe(gt)->info.has_flat_ccs;
>>>>> +}
>>>>> diff --git a/drivers/gpu/drm/xe/xe_rtp.h 
>>>>> b/drivers/gpu/drm/xe/xe_rtp.h
>>>>> index ac12ddf6cde6d..92f0d16110dd5 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_rtp.h
>>>>> +++ b/drivers/gpu/drm/xe/xe_rtp.h
>>>>> @@ -483,4 +483,14 @@ bool xe_rtp_match_psmi_enabled(const struct 
>>>>> xe_gt *gt,
>>>>>   bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct 
>>>>> xe_gt *gt,
>>>>>                             const struct xe_hw_engine *hwe);
>>>>> +/**
>>>>> + * xe_rtp_match_has_flat_ccs - Match when platform has FlatCCS 
>>>>> compression
>>>>> + * @gt: GT structure
>>>>> + * @hwe: Engine instance
>>>>> + *
>>>>> + * Returns: true if platform has FlatCCS compression, false 
>>>>> otherwise
>>>>> + */
>>>>> +bool xe_rtp_match_has_flat_ccs(const struct xe_gt *gt,
>>>>> +                   const struct xe_hw_engine *hwe);
>>>>> +
>>>>>   #endif
>>>>> diff --git a/drivers/gpu/drm/xe/xe_tuning.c 
>>>>> b/drivers/gpu/drm/xe/xe_tuning.c
>>>>> index fd58ea5e78bf6..7c140d8cb1e07 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_tuning.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_tuning.c
>>>>> @@ -40,7 +40,8 @@ static const struct xe_rtp_entry_sr gt_tunings[] 
>>>>> = {
>>>>> REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
>>>>>       },
>>>>>       { XE_RTP_NAME("Tuning: Compression Overfetch"),
>>>>> -      XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 
>>>>> XE_RTP_END_VERSION_UNDEFINED)),
>>>>> +      XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 
>>>>> XE_RTP_END_VERSION_UNDEFINED),
>>>>> +               FUNC(xe_rtp_match_has_flat_ccs)),
>>>>>         XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
>>>>>                SET(CCCHKNREG1, L3CMPCTRL))
>>>>>       },
>>>>> @@ -58,12 +59,14 @@ static const struct xe_rtp_entry_sr 
>>>>> gt_tunings[] = {
>>>>>         XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3, COMPPWOVERFETCHEN))
>>>>>       },
>>>>>       { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
>>>>> -      XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 
>>>>> XE_RTP_END_VERSION_UNDEFINED)),
>>>>> +      XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 
>>>>> XE_RTP_END_VERSION_UNDEFINED),
>>>>> +               FUNC(xe_rtp_match_has_flat_ccs)),
>>>>>         XE_RTP_ACTIONS(SET(L3SQCREG2,
>>>>>                    COMPMEMRD256BOVRFETCHEN))
>>>>>       },
>>>>>       { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only - 
>>>>> media"),
>>>>> -      XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, 
>>>>> XE_RTP_END_VERSION_UNDEFINED)),
>>>>> +      XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, 
>>>>> XE_RTP_END_VERSION_UNDEFINED),
>>>>> +               FUNC(xe_rtp_match_has_flat_ccs)),
>>>>>         XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
>>>>>                    COMPMEMRD256BOVRFETCHEN))
>>>>>       },
>>>>>

Re: [PATCH 20/23] drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx

[Lucas De Marchi]

On Tue, Oct 14, 2025 at 11:07:05AM -0700, Matt Roper wrote:
>On Mon, Oct 13, 2025 at 08:24:52PM -0700, Lucas De Marchi wrote:
>> From: S A Muqthyar Ahmed <syed.abdul.muqthyar.ahmed@intel.com>
>>
>> Current implementation of compute walker has dependency on GPU/SW Stack
>> which requires SW/UMD to wait for event from KMD to indicate
>> PIPE_CONTROL interrup was done. This created latency on SW stack.
>>
>> This feature adds support to generate completion interrupt from GPGPU
>> walker which does not support MSIx and avoid software using Pipe control
>> drain/idle latency.
>>
>> Suggested-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>> Signed-off-by: S A Muqthyar Ahmed <syed.abdul.muqthyar.ahmed@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
>>  drivers/gpu/drm/xe/xe_irq.c           | 4 ++++
>>  2 files changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
>> index 7c2a3a1401424..9c46b5fb81412 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
>> @@ -82,6 +82,7 @@
>>  #define   GSC_ER_COMPLETE			REG_BIT(5)
>>  #define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)
>>  #define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
>> +#define   GT_COMPUTE_WALKER_INTERRUPT		REG_BIT(2)
>>  #define   GT_RENDER_USER_INTERRUPT		REG_BIT(0)
>>
>>  /* irqs for OTHER_KCR_INSTANCE */
>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>> index af519414a4297..e01b158895342 100644
>> --- a/drivers/gpu/drm/xe/xe_irq.c
>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>> @@ -150,6 +150,10 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>>  	if (xe_device_uc_enabled(xe)) {
>>  		irqs = GT_RENDER_USER_INTERRUPT |
>>  			GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
>> +
>> +		/* Enable Compute Walker Interrupt for non-MSIX platforms */
>> +		if (GRAPHICS_VERx100(xe) >= 3511 && !xe_device_has_msix(xe))
>> +			irqs |= GT_COMPUTE_WALKER_INTERRUPT;
>
>This bit only exists in the compute engine interrupt vector (bspec
>62346) and render engine interrupt vector (bspec 62353).  It does not
>exist in the blitter (62345), vcs (62354), vecs (62355), or gsc (63341),
>which makes sense because none of those engines can run compute walkers.
>Should we be making sure we only try to unmask and enable this interrupt
>on supported engine types?

right... but then we also have similar issues about being lazy with
other bits as well. Checking the other interrupt vector structures, bit
2 is not defined for them.

I'm leaning towards we are being lazy in the programming here and this
is not currently a problem. Then we can refactor this on top to stop
being lazy and make the intention of the code clearer (e.g. I don't
really like that use of smask/dmask because engines are bundled together
in a single register).

Lucas De Marchi

>
>
>Matt
>
>>  	} else {
>>  		irqs = GT_RENDER_USER_INTERRUPT |
>>  		       GT_CS_MASTER_ERROR_INTERRUPT |
>>
>> --
>> 2.51.0
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [PATCH 20/23] drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx

[Matt Roper]

On Wed, Oct 15, 2025 at 12:07:47PM -0500, Lucas De Marchi wrote:
> On Tue, Oct 14, 2025 at 11:07:05AM -0700, Matt Roper wrote:
> > On Mon, Oct 13, 2025 at 08:24:52PM -0700, Lucas De Marchi wrote:
> > > From: S A Muqthyar Ahmed <syed.abdul.muqthyar.ahmed@intel.com>
> > > 
> > > Current implementation of compute walker has dependency on GPU/SW Stack
> > > which requires SW/UMD to wait for event from KMD to indicate
> > > PIPE_CONTROL interrup was done. This created latency on SW stack.
> > > 
> > > This feature adds support to generate completion interrupt from GPGPU
> > > walker which does not support MSIx and avoid software using Pipe control
> > > drain/idle latency.
> > > 
> > > Suggested-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> > > Signed-off-by: S A Muqthyar Ahmed <syed.abdul.muqthyar.ahmed@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > >  drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
> > >  drivers/gpu/drm/xe/xe_irq.c           | 4 ++++
> > >  2 files changed, 5 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> > > index 7c2a3a1401424..9c46b5fb81412 100644
> > > --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> > > +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> > > @@ -82,6 +82,7 @@
> > >  #define   GSC_ER_COMPLETE			REG_BIT(5)
> > >  #define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)
> > >  #define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
> > > +#define   GT_COMPUTE_WALKER_INTERRUPT		REG_BIT(2)
> > >  #define   GT_RENDER_USER_INTERRUPT		REG_BIT(0)
> > > 
> > >  /* irqs for OTHER_KCR_INSTANCE */
> > > diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> > > index af519414a4297..e01b158895342 100644
> > > --- a/drivers/gpu/drm/xe/xe_irq.c
> > > +++ b/drivers/gpu/drm/xe/xe_irq.c
> > > @@ -150,6 +150,10 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
> > >  	if (xe_device_uc_enabled(xe)) {
> > >  		irqs = GT_RENDER_USER_INTERRUPT |
> > >  			GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
> > > +
> > > +		/* Enable Compute Walker Interrupt for non-MSIX platforms */
> > > +		if (GRAPHICS_VERx100(xe) >= 3511 && !xe_device_has_msix(xe))
> > > +			irqs |= GT_COMPUTE_WALKER_INTERRUPT;
> > 
> > This bit only exists in the compute engine interrupt vector (bspec
> > 62346) and render engine interrupt vector (bspec 62353).  It does not
> > exist in the blitter (62345), vcs (62354), vecs (62355), or gsc (63341),
> > which makes sense because none of those engines can run compute walkers.
> > Should we be making sure we only try to unmask and enable this interrupt
> > on supported engine types?
> 
> right... but then we also have similar issues about being lazy with
> other bits as well. Checking the other interrupt vector structures, bit
> 2 is not defined for them.
> 
> I'm leaning towards we are being lazy in the programming here and this
> is not currently a problem. Then we can refactor this on top to stop
> being lazy and make the intention of the code clearer (e.g. I don't
> really like that use of smask/dmask because engines are bundled together
> in a single register).

My main worry here is that since different engines do explicitly have
different interrupt vectors, there's more potential for a future
platform to use this "unused" bit for a completely different type of
interrupt on blitter, media, etc.  That would be easy for us to overlook
during early platform bringup.

It's less likely that the enable/mask bits for an engine (for example,
BCS6) would get repurposed on a platform that doesn't have that engine,
because the engine still has reserved register ranges and such in the
architecture, even for individual platforms that don't use it.


Matt

> 
> Lucas De Marchi
> 
> > 
> > 
> > Matt
> > 
> > >  	} else {
> > >  		irqs = GT_RENDER_USER_INTERRUPT |
> > >  		       GT_CS_MASTER_ERROR_INTERRUPT |
> > > 
> > > --
> > > 2.51.0
> > > 
> > 
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 12/23] drm/xe/xe3p: Flush userptr/shrinker bo cachelines manually

[Lucas De Marchi]

On Tue, Oct 14, 2025 at 02:58:55PM +0200, Thomas Hellström wrote:
>Hi,
>
>On Mon, 2025-10-13 at 20:24 -0700, Lucas De Marchi wrote:
>> From: Tejas Upadhyay <tejas.upadhyay@intel.com>
>>
>> Starting with Xe3p, HW will flush cachelines marked with XA only when
>> media is off. We have few cases where kernel will have non-XA
>> cachelines
>> which needs manual flush as we postpone the invalidation.
>
>is XA- and non-XA cachelines described somewhere in the code?

no, not yet. See reply from Matt to "[PATCH 10/23] drm/xe/xe3p: Skip TD
flush".

I will drop this patch and the 2 before this one on next version.

Lucas De Marchi

>
>>
>> Flush asap from correctness POV to ensure non accelerated CPU copy to
>> swap/shmem file will see coherent view of memory, but also from
>> security
>> POV where later flush can't corrupt the next user of those pages.
>>
>> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
>> [ TODO: xe_device_needs_cache_flush() seems a bad name that doesn't
>>   really review the context - it may need to be renamed/localized ]
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
>This worries me. Any dma-fence *must*, when signaled, have flushed all
>caches from data resulting from the operation it marks the completion
>of. The code below indicates that's not the case?
>
>Note also that the wait for idle in xe_bo_trigger_rebind does not
>guarantee that the bo is idle, just that there are no pending bind
>operations.
>
>In fault mode we have a slightly different approach to ensure data is
>flushed before pages are released.
>
>Could you elaborate a bit on how this is intendend to work.
>
>Thanks,
>Thomas
>
>
>> ---
>>  drivers/gpu/drm/xe/xe_bo.c      |  3 ++-
>>  drivers/gpu/drm/xe/xe_device.c  | 20 ++++++++++++++++++++
>>  drivers/gpu/drm/xe/xe_device.h  |  1 +
>>  drivers/gpu/drm/xe/xe_userptr.c |  3 ++-
>>  4 files changed, 25 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
>> index 7b65020818738..05bc61d9e37cf 100644
>> --- a/drivers/gpu/drm/xe/xe_bo.c
>> +++ b/drivers/gpu/drm/xe/xe_bo.c
>> @@ -673,7 +673,8 @@ static int xe_bo_trigger_rebind(struct xe_device
>> *xe, struct xe_bo *bo,
>>  
>>  		if (!xe_vm_in_fault_mode(vm)) {
>>  			drm_gpuvm_bo_evict(vm_bo, true);
>> -			continue;
>> +			if (!xe_device_needs_cache_flush(xe))
>> +				continue;
>>  		}
>>  
>>  		if (!idle) {
>> diff --git a/drivers/gpu/drm/xe/xe_device.c
>> b/drivers/gpu/drm/xe/xe_device.c
>> index 7efa8da9e1069..168a45fe36838 100644
>> --- a/drivers/gpu/drm/xe/xe_device.c
>> +++ b/drivers/gpu/drm/xe/xe_device.c
>> @@ -1081,6 +1081,26 @@ void xe_device_l2_flush(struct xe_device *xe)
>>  	xe_force_wake_put(gt_to_fw(gt), fw_ref);
>>  }
>>  
>> +/**
>> + * xe_device_needs_cache_flush - Whether the cache needs to be
>> flushed
>> + * @xe: The device to check.
>> + *
>> + * Return: true if the device needs cache flush, false otherwise.
>> + */
>> +bool xe_device_needs_cache_flush(struct xe_device *xe)
>> +{
>> +	/*
>> +	 * Xe3p will flush cachelines marked with XA only when media
>> is off. We
>> +	 * have few cases where kernel will have non-XA cachelines
>> which needs
>> +	 * manual flush and this is one of them as we postpone the
>> +	 * invalidation. Flush asap from correctness POV to ensure
>> non
>> +	 * accelerated CPU copy to swap/shmem file will see coherent
>> view of
>> +	 * memory, but also from security POV where later flush
>> can't corrupt
>> +	 * the next user of those pages.
>> +	 */
>> +	return GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe);
>> +}
>> +
>>  /**
>>   * xe_device_td_flush() - Flush transient L3 cache entries
>>   * @xe: The device
>> diff --git a/drivers/gpu/drm/xe/xe_device.h
>> b/drivers/gpu/drm/xe/xe_device.h
>> index 32cc6323b7f64..15e67db44b56c 100644
>> --- a/drivers/gpu/drm/xe/xe_device.h
>> +++ b/drivers/gpu/drm/xe/xe_device.h
>> @@ -179,6 +179,7 @@ void xe_device_snapshot_print(struct xe_device
>> *xe, struct drm_printer *p);
>>  u64 xe_device_canonicalize_addr(struct xe_device *xe, u64 address);
>>  u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64
>> address);
>>  
>> +bool xe_device_needs_cache_flush(struct xe_device *xe);
>>  void xe_device_td_flush(struct xe_device *xe);
>>  void xe_device_l2_flush(struct xe_device *xe);
>>  
>> diff --git a/drivers/gpu/drm/xe/xe_userptr.c
>> b/drivers/gpu/drm/xe/xe_userptr.c
>> index f16e92cd80904..86ce1c3ef41aa 100644
>> --- a/drivers/gpu/drm/xe/xe_userptr.c
>> +++ b/drivers/gpu/drm/xe/xe_userptr.c
>> @@ -112,7 +112,8 @@ static void __vma_userptr_invalidate(struct xe_vm
>> *vm, struct xe_userptr_vma *uv
>>  				    false, MAX_SCHEDULE_TIMEOUT);
>>  	XE_WARN_ON(err <= 0);
>>  
>> -	if (xe_vm_in_fault_mode(vm) && userptr->initial_bind) {
>> +	if ((xe_vm_in_fault_mode(vm) ||
>> xe_device_needs_cache_flush(vm->xe)) &&
>> +	    userptr->initial_bind) {
>>  		err = xe_vm_invalidate_vma(vma);
>>  		XE_WARN_ON(err);
>>  	}
>>
>

Re: [PATCH 15/23] drm/xe/nvls: Define GuC firmware for NVL-S

[Lucas De Marchi]

On Mon, Oct 13, 2025 at 08:24:47PM -0700, Lucas De Marchi wrote:
>From: Matt Roper <matthew.d.roper@intel.com>
>
>Although NVL-S has a similar Xe3 to PTL/WCL, it requires a unique GuC
>firmware.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>---
> drivers/gpu/drm/xe/xe_uc_fw.c | 1 +
> 1 file changed, 1 insertion(+)
>
>diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
>index 6056ecd0b92f5..e589c7e38f125 100644
>--- a/drivers/gpu/drm/xe/xe_uc_fw.c
>+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
>@@ -115,6 +115,7 @@ struct fw_blobs_by_type {
> #define XE_GT_TYPE_ANY XE_GT_TYPE_UNINITIALIZED
>
> #define XE_GUC_FIRMWARE_DEFS(fw_def, mmp_ver, major_ver)					\
>+	fw_def(NOVALAKE_S,	GT_TYPE_ANY,	mmp_ver(xe,	guc,	nvl,	70, 49, 4))	\

just a note that this patch, as a user of mmp_ver() and with no firmware
blob published yet, it's targeting the topic/xe-for-CI branch.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

> 	fw_def(PANTHERLAKE,	GT_TYPE_ANY,	major_ver(xe,	guc,	ptl,	70, 49, 4))	\
> 	fw_def(BATTLEMAGE,	GT_TYPE_ANY,	major_ver(xe,	guc,	bmg,	70, 49, 4))	\
> 	fw_def(LUNARLAKE,	GT_TYPE_ANY,	major_ver(xe,	guc,	lnl,	70, 45, 2))	\
>
>-- 
>2.51.0
>

Re: [PATCH 09/23] drm/xe/xe3p: Determine service copy availability from fuse

[Gustavo Sousa]

Quoting Lucas De Marchi (2025-10-14 00:24:41-03:00)
>From: Matt Roper <matthew.d.roper@intel.com>
>
>Xe3p introduces a dedicated SERVICE_COPY_ENABLE fuse register to reflect
>the availability of the service copy engines (BCS1-BCS8).
>
>Bspec: 74624
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

>---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h |  3 +++
> drivers/gpu/drm/xe/xe_hw_engine.c    | 43 ++++++++++++++++++++++++++++--------
> 2 files changed, 37 insertions(+), 9 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>index 937dc341abe5e..b73efde21119f 100644
>--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>@@ -245,6 +245,9 @@
> #define XE2_GT_GEOMETRY_DSS_1                        XE_REG(0x9150)
> #define XE2_GT_GEOMETRY_DSS_2                        XE_REG(0x9154)
> 
>+#define SERVICE_COPY_ENABLE                        XE_REG(0x9170)
>+#define   FUSE_SERVICE_COPY_ENABLE_MASK                REG_GENMASK(7, 0)
>+
> #define GDRST                                        XE_REG(0x941c)
> #define   GRDOM_GUC                                REG_BIT(3)
> #define   GRDOM_FULL                                REG_BIT(0)
>diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
>index 5544d91c21e8e..275d522d301a3 100644
>--- a/drivers/gpu/drm/xe/xe_hw_engine.c
>+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
>@@ -716,27 +716,52 @@ static void read_media_fuses(struct xe_gt *gt)
>         }
> }
> 
>+static u32 infer_svccopy_from_meml3(struct xe_gt *gt)
>+{
>+        u32 meml3 = REG_FIELD_GET(MEML3_EN_MASK,
>+                                  xe_mmio_read32(&gt->mmio, MIRROR_FUSE3));
>+        u32 svccopy_mask = 0;
>+
>+        /*
>+         * Each of the four meml3 bits determines the fusing of two service
>+         * copy engines.
>+         */
>+        for (int i = 0; i < 4; i++)
>+                svccopy_mask |= (meml3 & BIT(i)) ? 0b11 << 2 * i : 0;
>+
>+        return svccopy_mask;
>+}
>+
>+static u32 read_svccopy_fuses(struct xe_gt *gt)
>+{
>+        return REG_FIELD_GET(FUSE_SERVICE_COPY_ENABLE_MASK,
>+                             xe_mmio_read32(&gt->mmio, SERVICE_COPY_ENABLE));
>+}
>+
> static void read_copy_fuses(struct xe_gt *gt)
> {
>         struct xe_device *xe = gt_to_xe(gt);
>         u32 bcs_mask;
> 
>-        if (GRAPHICS_VERx100(xe) < 1260 || GRAPHICS_VERx100(xe) >= 1270)
>-                return;
>-
>         xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
> 
>-        bcs_mask = xe_mmio_read32(&gt->mmio, MIRROR_FUSE3);
>-        bcs_mask = REG_FIELD_GET(MEML3_EN_MASK, bcs_mask);
>+        if (GRAPHICS_VER(xe) >= 35)
>+                bcs_mask = read_svccopy_fuses(gt);
>+        else if (GRAPHICS_VERx100(xe) == 1260)
>+                bcs_mask = infer_svccopy_from_meml3(gt);
>+        else
>+                return;
> 
>-        /* BCS0 is always present; only BCS1-BCS8 may be fused off */
>-        for (int i = XE_HW_ENGINE_BCS1, j = 0; i <= XE_HW_ENGINE_BCS8; ++i, ++j) {
>+        /* Only BCS1-BCS8 may be fused off */
>+        bcs_mask <<= XE_HW_ENGINE_BCS1;
>+        for (int i = XE_HW_ENGINE_BCS1; i <= XE_HW_ENGINE_BCS8; ++i) {
>                 if (!(gt->info.engine_mask & BIT(i)))
>                         continue;
> 
>-                if (!(BIT(j / 2) & bcs_mask)) {
>+                if (!(bcs_mask & BIT(i))) {
>                         gt->info.engine_mask &= ~BIT(i);
>-                        xe_gt_info(gt, "bcs%u fused off\n", j);
>+                        xe_gt_info(gt, "bcs%u fused off\n",
>+                                   i - XE_HW_ENGINE_BCS0);
>                 }
>         }
> }
>
>-- 
>2.51.0
>

Re: [PATCH 23/23] drm/xe/xe3p: Add xe3p EU stall data format

[Harish Chegondi]

On Tue, Oct 14, 2025 at 12:11:39PM -0700, Matt Roper wrote:
> On Mon, Oct 13, 2025 at 08:24:55PM -0700, Lucas De Marchi wrote:
> > From: Harish Chegondi <harish.chegondi@intel.com>
> > 
> > Starting with Xe3p, IP address in EU stall data is increases to 61 bits.
> 
> As far as I can see, the EU stall format isn't documented anywhere in
> the bspec (which seems like a major oversight!) but the early
> architecture document related to this change seems to indicate that a
> full 64-bit IP was supposed to be written by hardware now
> 
>         "Bit filed[sic] 0-28 is now 0-63"
> 
> Your structure is only using 61 bits (which definitely makes sense if
> the addresses are aligned since the lowest three bits would always be
> 0's); is there somewhere other than the bspec or architecture document
> that we should be looking at to confirm this?
I agree that EU stall is not properly documented in the B-Spec.
I looked up an HSD for Xe3p to confirm and make this change. Also
checked with the architect to confirm this change.
> 
> If you've been working directly with the hardware architects on this
> feature, please poke them about documenting this clearly in the bspec
> (with proper tagging by IP/platform) so that we can verify this is
> handled correctly and also notice if/when the format changes again on
> future platforms.
Sure, I will follow up with the HW architects to make sure the EU stall
data formats are properly documented in the Bspec and are properly
tagged.
> 
> 
> Matt

Thank You
Harish.
> 
> > 
> > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_eu_stall.c | 23 +++++++++++++++++++++++
> >  1 file changed, 23 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
> > index f5cfdf29fde34..2bc6b593ff172 100644
> > --- a/drivers/gpu/drm/xe/xe_eu_stall.c
> > +++ b/drivers/gpu/drm/xe/xe_eu_stall.c
> > @@ -124,6 +124,27 @@ struct xe_eu_stall_data_xe2 {
> >  	__u64 unused[6];
> >  } __packed;
> >  
> > +/*
> > + * EU stall data format for Xe3p arch GPUs.
> > + */
> > +struct xe_eu_stall_data_xe3p {
> > +	__u64 ip_addr:61;	  /* Bits 0  to 60  */
> > +	__u64 tdr_count:8;	  /* Bits 61 to 68  */
> > +	__u64 other_count:8;	  /* Bits 69 to 76  */
> > +	__u64 control_count:8;	  /* Bits 77 to 84  */
> > +	__u64 pipestall_count:8;  /* Bits 85 to 92  */
> > +	__u64 send_count:8;	  /* Bits 93 to 100 */
> > +	__u64 dist_acc_count:8;   /* Bits 101 to 108 */
> > +	__u64 sbid_count:8;	  /* Bits 109 to 116 */
> > +	__u64 sync_count:8;	  /* Bits 117 to 124 */
> > +	__u64 inst_fetch_count:8; /* Bits 125 to 132 */
> > +	__u64 active_count:8;	  /* Bits 133 to 140 */
> > +	__u64 ex_id:3;		  /* Bits 141 to 143 */
> > +	__u64 end_flag:1;	  /* Bit  144 */
> > +	__u64 unused_bits:47;
> > +	__u64 unused[5];
> > +} __packed;
> > +
> >  const u64 eu_stall_sampling_rates[] = {251, 251 * 2, 251 * 3, 251 * 4, 251 * 5, 251 * 6, 251 * 7};
> >  
> >  /**
> > @@ -169,6 +190,8 @@ size_t xe_eu_stall_data_record_size(struct xe_device *xe)
> >  
> >  	if (xe->info.platform == XE_PVC)
> >  		record_size = sizeof(struct xe_eu_stall_data_pvc);
> > +	else if (GRAPHICS_VER(xe) >= 35)
> > +		record_size = sizeof(struct xe_eu_stall_data_xe3p);
> >  	else if (GRAPHICS_VER(xe) >= 20)
> >  		record_size = sizeof(struct xe_eu_stall_data_xe2);
> >  
> > 
> > -- 
> > 2.51.0
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation

Re: [PATCH 22/23] drm/xe/xe3p_xpc: Setup PAT table

[Vivekanandan, Balasubramani]

On 13.10.2025 20:24, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Xe3p_XPC IP requires a new PAT table; note that this table has one fewer
> column than the Xe2/Xe3 tables since compression is not supported.
> There's also no "WT" entry (which we wouldn't have used on a platform
> without display anyway).
> 
> Bspec: 71582
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_pat.c | 96 ++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 95 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
> index 6e48ff84ad0a0..7649b554942aa 100644
> --- a/drivers/gpu/drm/xe/xe_pat.c
> +++ b/drivers/gpu/drm/xe/xe_pat.c
> @@ -154,6 +154,41 @@ static const struct xe_pat_table_entry xe2_pat_table[] = {
>  static const struct xe_pat_table_entry xe2_pat_ats = XE2_PAT( 0, 0, 0, 0, 3, 3 );
>  static const struct xe_pat_table_entry xe2_pat_pta = XE2_PAT( 0, 0, 0, 0, 3, 0 );
>  
> +/*
> + * Xe3p_XPC PAT table uses the same layout as Xe2/Xe3, except that there's no
> + * option for compression.  Also note that the "L3" and "L4" register fields
> + * actually control L2 and L3 cache respectively on this platform.
> + */
> +#define XE3P_XPC_PAT(no_promote, l3clos, l3_policy, l4_policy, __coh_mode) \
> +	XE2_PAT(no_promote, 0, l3clos, l3_policy, l4_policy, __coh_mode)
> +
> +static const struct xe_pat_table_entry xe3p_xpc_pat_ats = XE3P_XPC_PAT( 0, 0, 0, 0, 3 );
> +static const struct xe_pat_table_entry xe3p_xpc_pat_pta = XE3P_XPC_PAT( 0, 0, 0, 0, 0 );
> +
> +static const struct xe_pat_table_entry xe3p_xpc_pat_table[] = {
> +	[ 0] = XE3P_XPC_PAT( 0, 0, 0, 0, 0 ),
> +	[ 1] = XE3P_XPC_PAT( 0, 0, 0, 0, 2 ),
> +	[ 2] = XE3P_XPC_PAT( 0, 0, 0, 0, 3 ),
> +	[ 3] = XE3P_XPC_PAT( 0, 0, 3, 3, 0 ),
> +	[ 4] = XE3P_XPC_PAT( 0, 0, 3, 3, 2 ),
> +	[ 5] = XE3P_XPC_PAT( 0, 0, 3, 0, 0 ),
> +	[ 6] = XE3P_XPC_PAT( 0, 0, 3, 0, 2 ),
> +	[ 7] = XE3P_XPC_PAT( 0, 0, 3, 0, 3 ),
> +	[ 8] = XE3P_XPC_PAT( 0, 0, 0, 3, 0 ),
> +	[ 9] = XE3P_XPC_PAT( 0, 0, 0, 3, 2 ),
> +	[10] = XE3P_XPC_PAT( 0, 0, 0, 3, 3 ),
> +	/* 11..22 are reserved; leave set to all 0's */
> +	[23] = XE3P_XPC_PAT( 0, 1, 0, 0, 0 ),
> +	[24] = XE3P_XPC_PAT( 0, 1, 0, 0, 2 ),
> +	[25] = XE3P_XPC_PAT( 0, 1, 0, 0, 3 ),
> +	[26] = XE3P_XPC_PAT( 0, 2, 0, 0, 0 ),
> +	[27] = XE3P_XPC_PAT( 0, 2, 0, 0, 2 ),
> +	[28] = XE3P_XPC_PAT( 0, 2, 0, 0, 3 ),
> +	[29] = XE3P_XPC_PAT( 0, 3, 0, 0, 0 ),
> +	[30] = XE3P_XPC_PAT( 0, 3, 0, 0, 2 ),
> +	[31] = XE3P_XPC_PAT( 0, 3, 0, 0, 3 ),
> +};
> +
>  u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index)
>  {
>  	WARN_ON(pat_index >= xe->pat.n_entries);
> @@ -380,9 +415,68 @@ static const struct xe_pat_ops xe2_pat_ops = {
>  	.dump = xe2_dump,
>  };
>  
> +static int xe3p_xpc_dump(struct xe_gt *gt, struct drm_printer *p)
> +{
> +	struct xe_device *xe = gt_to_xe(gt);
> +	unsigned int fw_ref;
> +	u32 pat;
> +	int i;
> +
> +	fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
> +	if (!fw_ref)
> +		return -ETIMEDOUT;
> +
> +	drm_printf(p, "PAT table:\n");
> +
> +	for (i = 0; i < xe->pat.n_entries; i++) {
> +		pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));
> +
> +		drm_printf(p, "PAT[%2d] = [ %u, %u, %u, %u, %u ]  (%#8x)\n", i,
> +			   !!(pat & XE2_NO_PROMOTE),
> +			   REG_FIELD_GET(XE2_L3_CLOS, pat),
> +			   REG_FIELD_GET(XE2_L3_POLICY, pat),
> +			   REG_FIELD_GET(XE2_L4_POLICY, pat),
> +			   REG_FIELD_GET(XE2_COH_MODE, pat),
> +			   pat);
> +	}
> +
> +	/*
> +	 * Also print PTA_MODE, which describes how the hardware accesses
> +	 * PPGTT entries.
> +	 */
> +	pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA));
> +
> +	drm_printf(p, "Page Table Access:\n");
> +	drm_printf(p, "PTA_MODE= [ %u, %u, %u, %u, %u ]  (%#8x)\n",
> +		   !!(pat & XE2_NO_PROMOTE),
> +		   REG_FIELD_GET(XE2_L3_CLOS, pat),
> +		   REG_FIELD_GET(XE2_L3_POLICY, pat),
> +		   REG_FIELD_GET(XE2_L4_POLICY, pat),
> +		   REG_FIELD_GET(XE2_COH_MODE, pat),
> +		   pat);

For completeness, we can print the _PTA_ATS register also.
Outside that, patch LGTM.

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

> +
> +	xe_force_wake_put(gt_to_fw(gt), fw_ref);
> +	return 0;
> +}
> +
> +static const struct xe_pat_ops xe3p_xpc_pat_ops = {
> +	.program_graphics = program_pat_mcr,
> +	.program_media = program_pat,
> +	.dump = xe3p_xpc_dump,
> +};
> +
>  void xe_pat_init_early(struct xe_device *xe)
>  {
> -	if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
> +	if (GRAPHICS_VERx100(xe) == 3511) {
> +		xe->pat.ops = &xe3p_xpc_pat_ops;
> +		xe->pat.table = xe3p_xpc_pat_table;
> +		xe->pat.pat_ats = &xe3p_xpc_pat_ats;
> +		xe->pat.pat_pta = &xe3p_xpc_pat_pta;
> +		xe->pat.n_entries = ARRAY_SIZE(xe3p_xpc_pat_table);
> +		xe->pat.idx[XE_CACHE_NONE] = 3;
> +		xe->pat.idx[XE_CACHE_WT] = 3;	/* N/A (no display); use UC */
> +		xe->pat.idx[XE_CACHE_WB] = 2;
> +	} else if (GRAPHICS_VER(xe) == 30 || GRAPHICS_VER(xe) == 20) {
>  		xe->pat.ops = &xe2_pat_ops;
>  		xe->pat.table = xe2_pat_table;
>  		xe->pat.pat_ats = &xe2_pat_ats;
> 
> -- 
> 2.51.0
> 

Re: [PATCH 03/23] drm/xe/xe3p_lpm: Configure MAIN_GAMCTRL_QUEUE_SELECT

[Vivekanandan, Balasubramani]

On 15.10.2025 09:03, Lucas De Marchi wrote:
> On Wed, Oct 15, 2025 at 12:06:55PM +0530, Vivekanandan, Balasubramani wrote:
> > On 14.10.2025 21:28, Lucas De Marchi wrote:
> > > On Tue, Oct 14, 2025 at 09:34:03AM -0700, Matt Roper wrote:
> > > > On Mon, Oct 13, 2025 at 08:24:35PM -0700, Lucas De Marchi wrote:
> > > > > From: Brian Welty <brian.welty@intel.com>
> > > > >
> > > > > Starting from Xe3p, there are two different copies of some of the GAM
> > > > > registers:  the traditional MCR variant at their old locations, and a
> > > > > new unicast copy known as "main_gamctrl."  The Xe driver doesn't use
> > > > > these registers directly, but we need to instruct the GuC on which set
> > > > > it should use.  Since the new, unicast registers are preferred (since
> > > > > they avoid the need for unnecessary MCR synchronization), set a new GuC
> > > > > feature flag, GUC_CTL_MAIN_GAMCTRL_QUEUES to convey this decision.  A
> > > > > new helper function, xe_guc_using_main_gamctrl_queues(), is added for
> > > > > use in the 3 independent places that need to handle configuration of the
> > > > > new reporting queues.
> > > > >
> > > > > The mmio write to enable the main gamctl is only done during the general
> > > > > GuC upload.  The gamctrl registers are not accessed by the GuC during
> > > > > hwconfig load.
> > > > >
> > > > > Last, the ADS blob for communicating the queue addresses contains both a
> > > > > DPA and GGTT offset. The GuC documentation states that DPA is now MBZ
> > > > > when using the MAIN_GAMCTRL queues.
> > > > >
> > > > > Signed-off-by: Brian Welty <brian.welty@intel.com>
> > > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  3 +++
> > > > >  drivers/gpu/drm/xe/xe_gt.h           |  6 ++++++
> > > > >  drivers/gpu/drm/xe/xe_guc.c          | 27 +++++++++++++++++++++++++++
> > > > >  drivers/gpu/drm/xe/xe_guc.h          |  1 +
> > > > >  drivers/gpu/drm/xe/xe_guc_ads.c      |  6 +++++-
> > > > >  drivers/gpu/drm/xe/xe_guc_fwif.h     |  1 +
> > > > >  6 files changed, 43 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > > > > index 51f2a03847f9d..47e13a3fb9072 100644
> > > > > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > > > > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > > > > @@ -545,6 +545,9 @@
> > > > >  #define SARB_CHICKEN1				XE_REG_MCR(0xe90c)
> > > > >  #define   COMP_CKN_IN				REG_GENMASK(30, 29)
> > > > >
> > > > > +#define MAIN_GAMCTRL_MODE			XE_REG(0xef00)
> > > > > +#define   MAIN_GAMCTRL_QUEUE_SELECT		REG_BIT(0)
> > > > > +
> > > > >  #define RCU_MODE				XE_REG(0x14800, XE_REG_OPTION_MASKED)
> > > > >  #define   RCU_MODE_FIXED_SLICE_CCS_MODE		REG_BIT(1)
> > > > >  #define   RCU_MODE_CCS_ENABLE			REG_BIT(0)
> > > > > diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h
> > > > > index 5df2ffe3ff838..9d710049da455 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_gt.h
> > > > > +++ b/drivers/gpu/drm/xe/xe_gt.h
> > > > > @@ -22,6 +22,12 @@
> > > > >
> > > > >  #define CCS_MASK(gt) (((gt)->info.engine_mask & XE_HW_ENGINE_CCS_MASK) >> XE_HW_ENGINE_CCS0)
> > > > >
> > > > > +#define GT_VER(gt) ({ \
> > > > > +	typeof(gt) gt_ = (gt); \
> > > > > +	struct xe_device *xe = gt_to_xe(gt_); \
> > > > > +	xe_gt_is_media_type(gt_) ? MEDIA_VER(xe) : GRAPHICS_VER(xe); \
> > > > > +})
> > > > > +
> > > > >  extern struct fault_attr gt_reset_failure;
> > > > >  static inline bool xe_fault_inject_gt_reset(void)
> > > > >  {
> > > > > diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> > > > > index d94490979adc0..37e3735f34e63 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_guc.c
> > > > > +++ b/drivers/gpu/drm/xe/xe_guc.c
> > > > > @@ -91,6 +91,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
> > > > >  	if (xe_configfs_get_psmi_enabled(to_pci_dev(xe->drm.dev)))
> > > > >  		flags |= GUC_CTL_ENABLE_PSMI_LOGGING;
> > > > >
> > > > > +	if (xe_guc_using_main_gamctrl_queues(guc))
> > > > > +		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
> > > > > +
> > > > >  	return flags;
> > > > >  }
> > > > >
> > > > > @@ -1255,8 +1258,13 @@ int xe_guc_min_load_for_hwconfig(struct xe_guc *guc)
> > > > >
> > > > >  int xe_guc_upload(struct xe_guc *guc)
> > > > >  {
> > > > > +	struct xe_gt *gt = guc_to_gt(guc);
> > > > > +
> > > > >  	xe_guc_ads_populate(&guc->ads);
> > > > >
> > > > > +	if (xe_guc_using_main_gamctrl_queues(guc))
> > > > > +		xe_mmio_write32(&gt->mmio, MAIN_GAMCTRL_MODE, MAIN_GAMCTRL_QUEUE_SELECT);
> > > > > +
> > > > >  	return __xe_guc_upload(guc);
> > > > >  }
> > > > >
> > > > > @@ -1657,6 +1665,25 @@ void xe_guc_declare_wedged(struct xe_guc *guc)
> > > > >  	xe_guc_submit_wedge(guc);
> > > > >  }
> > > > >
> > > > > +/**
> > > > > + * xe_guc_using_main_gamctrl_queues() - Detect which reporting queues to use.
> > > > > + * @guc: The GuC object
> > > > > + *
> > > > > + * For Xe3p and beyond, we want to program the hardware to use the
> > > > > + * "Main GAMCTRL queue" rather than the legacy queue before we upload
> > > > > + * the GuC firmware.  This will allow the GuC to use a new set of
> > > > > + * registers for pagefault handling and avoid some unnecessary
> > > > > + * complications with MCR register range handling.
> > > > > + *
> > > > > + * Return: true if can use new main gamctrl queues.
> > > > > + */
> > > > > +bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc)
> > > > > +{
> > > > > +	struct xe_gt *gt = guc_to_gt(guc);
> > > > > +
> > > > > +	return GT_VER(gt) >= 35;
> > > >
> > > > Revisiting the spec on this, I'm not sure whether using GT_VER() here is
> > > > actually the right thing to do.  As far as I can see, the media GT does
> > > > not actually have a "main gamctrl" register range at all (i.e., bspec
> > > > 76445 only lists MCR gamctrl ranges, and 0x38EF00-0x38EFFF falls within
> > > > a reserved/unused block).  That means that registers like
> > > 
> > > true
> > > 
> > > > MAIN_GAMCTRL_MODE that we're trying to write during xe_guc_upload above
> > > 
> > > We do have MAIN_GAMCTRL_MODE for xe3p_lpm in bspec 73540.
> > > The tagging is odd, but there is a reference to the register at
> > > 0x38EF00. It wouldn't make sense to have a 0x38xxxx register instance
> > > for primary/graphics GT.
> > > 
> > > So either
> > > 
> > > 1) we don't have it like you said
> > > 2) we have it and there's something missing in the MCR ranges
> > > 
> > > > don't actually exist for the media GT.  Furthermore, the tagging on the
> > > > register detail page 73540 also seems to imply that this only applies to
> > > > the primary/graphics GT.
> > > 
> > > so... in that case we'd need to check both the gt type and graphics ver,
> > > so we load GuC with those different flags. I will take a shot at that
> > > and check if anything breaks.
> > > 
> > > Bala, since you did the patch following this, do you remember of
> > > anything related to this?
> > 
> > There seems to be a conflict between the Bspec and the HSD. HSD
> > 16017994409 and the HAS claim the MainGAMCTRL is supported in Xe3p Media
> > IP whereas the Bspec page 73542 and the Steering table show the
> > MainGAMCTRL register range as not available for Xe3p Media.
> > 
> > For me it looks like a Bspec update issue. We have tested and verified
> > the current implementation which enables MainGAMCTRL for Media.
> > I would say lets keep the code as it is though it conflicts with the
> > spec and raise a Bspec issue to get it clarified.
> 
> I'm circling this back with HW and Spec people. I also did some changes
> local changes to test. Although since the old queues are still valid, I
> guess it will just pass, but without this optimization. On the other
> hand, I'd expect it to not work at all with the current code if it
> didn't apply to media.

There is an Bspec update to the steering table yesterday which now lists
the address range 0x38EF00 - 0x38EFFF as non-MCR. But still the Bspec
filtering is not correct. So the register range doesn't show up when
filtered for Xe3p Media.

Regards,
Bala

> 
> Another point is that we can delay this patch a little bit, since the
> next patch turns this off for media with the special bits set.
> 
> thanks
> Lucas De Marchi