[PATCH v4 02/39] dt-bindings: atmel-sysreg: add sam9x7

[PATCH v4 02/39] dt-bindings: atmel-sysreg: add sam9x7

[Varshini Rajendran]

Add RAM controller & SFR DT bindings.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Changes in v4:
- Updated Acked-by tag
---
 Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
index 67a66bf74895..1339298203c6 100644
--- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
@@ -11,7 +11,8 @@ PIT Timer required properties:
   shared across all System Controller members.
 
 PIT64B Timer required properties:
-- compatible: Should be "microchip,sam9x60-pit64b"
+- compatible: Should be "microchip,sam9x60-pit64b" or
+			"microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"
 - reg: Should contain registers location and length
 - interrupts: Should contain interrupt for PIT64B timer
 - clocks: Should contain the available clock sources for PIT64B timer.
@@ -31,7 +32,8 @@ RAMC SDRAM/DDR Controller required properties:
 			"atmel,at91sam9g45-ddramc",
 			"atmel,sama5d3-ddramc",
 			"microchip,sam9x60-ddramc",
-			"microchip,sama7g5-uddrc"
+			"microchip,sama7g5-uddrc",
+			"microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc".
 - reg: Should contain registers location and length
 
 Examples:
@@ -63,6 +65,7 @@ required properties:
 	"atmel,<chip>-sfrbu", "syscon"
   <chip> can be "sama5d3", "sama5d4" or "sama5d2".
   It also can be "microchip,sam9x60-sfr", "syscon".
+  It also can be "microchip,sam9x7-sfr", "microchip,sam9x60-sfr", "syscon".
 - reg: Should contain registers location and length
 
 	sfr@f0038000 {
-- 
2.25.1


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[PATCH v4 03/39] dt-bindings: crypto: add sam9x7 in Atmel AES

[Varshini Rajendran]

Add DT bindings for atmel AES.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v4:
- Updated Acked-by tag
---
 .../devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml   | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml
index 0b7383b3106b..7dc0748444fd 100644
--- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml
+++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml
@@ -12,7 +12,11 @@ maintainers:
 
 properties:
   compatible:
-    const: atmel,at91sam9g46-aes
+    oneOf:
+      - const: atmel,at91sam9g46-aes
+      - items:
+          - const: microchip,sam9x7-aes
+          - const: atmel,at91sam9g46-aes
 
   reg:
     maxItems: 1
-- 
2.25.1


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Re: [PATCH v4 03/39] dt-bindings: crypto: add sam9x7 in Atmel AES

[Tudor Ambarus]

On 23.02.2024 19:23, Varshini Rajendran wrote:
> Add DT bindings for atmel AES.
>

This would have deserved a better commit message, I (we) spent a lot of
time deciding whether this is the correct approach.
https://lore.kernel.org/linux-arm-kernel/342de8f3-852f-9bfa-39c4-4d820f349305@linaro.org/

> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Acked-by: Rob Herring <robh@kernel.org>

Anyway:
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
> ---
> Changes in v4:
> - Updated Acked-by tag
> ---
>  .../devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml   | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml
> index 0b7383b3106b..7dc0748444fd 100644
> --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml
> +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml
> @@ -12,7 +12,11 @@ maintainers:
>  
>  properties:
>    compatible:
> -    const: atmel,at91sam9g46-aes
> +    oneOf:
> +      - const: atmel,at91sam9g46-aes
> +      - items:
> +          - const: microchip,sam9x7-aes
> +          - const: atmel,at91sam9g46-aes
>  
>    reg:
>      maxItems: 1

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[PATCH v4 04/39] dt-bindings: crypto: add sam9x7 in Atmel SHA

[Varshini Rajendran]

Add DT bindings for atmel SHA.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v4:
- Updated Acked-by tag
---
 .../devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml   | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml
index ee2ffb034325..d378c53314dd 100644
--- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml
+++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml
@@ -12,7 +12,11 @@ maintainers:
 
 properties:
   compatible:
-    const: atmel,at91sam9g46-sha
+    oneOf:
+      - const: atmel,at91sam9g46-sha
+      - items:
+          - const: microchip,sam9x7-sha
+          - const: atmel,at91sam9g46-sha
 
   reg:
     maxItems: 1
-- 
2.25.1


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Re: [PATCH v4 04/39] dt-bindings: crypto: add sam9x7 in Atmel SHA

[Tudor Ambarus]

On 23.02.2024 19:23, Varshini Rajendran wrote:
> Add DT bindings for atmel SHA.

This would have deserved a better commit message, I (we) spent a lot of
time deciding whether this is the correct approach.
https://lore.kernel.org/linux-arm-kernel/342de8f3-852f-9bfa-39c4-4d820f349305@linaro.org/

Anyway:
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>

> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> Changes in v4:
> - Updated Acked-by tag
> ---
>  .../devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml   | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml
> index ee2ffb034325..d378c53314dd 100644
> --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml
> +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml
> @@ -12,7 +12,11 @@ maintainers:
>  
>  properties:
>    compatible:
> -    const: atmel,at91sam9g46-sha
> +    oneOf:
> +      - const: atmel,at91sam9g46-sha
> +      - items:
> +          - const: microchip,sam9x7-sha
> +          - const: atmel,at91sam9g46-sha
>  
>    reg:
>      maxItems: 1

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[PATCH v4 05/39] dt-bindings: crypto: add sam9x7 in Atmel TDES

[Varshini Rajendran]

Add DT bindings for atmel TDES.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
---
Changes in v4:
- Updated Acked-by tag
---
 .../devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml  | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml
index 3d6ed24b1b00..6a441f79efea 100644
--- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml
+++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml
@@ -12,7 +12,11 @@ maintainers:
 
 properties:
   compatible:
-    const: atmel,at91sam9g46-tdes
+    oneOf:
+      - const: atmel,at91sam9g46-tdes
+      - items:
+          - const: microchip,sam9x7-tdes
+          - const: atmel,at91sam9g46-tdes
 
   reg:
     maxItems: 1
-- 
2.25.1


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Re: [PATCH v4 05/39] dt-bindings: crypto: add sam9x7 in Atmel TDES

[Conor Dooley]

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On Fri, Feb 23, 2024 at 10:54:45PM +0530, Varshini Rajendran wrote:
> Add DT bindings for atmel TDES.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

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Re: [PATCH v4 05/39] dt-bindings: crypto: add sam9x7 in Atmel TDES

[Tudor Ambarus]

On 23.02.2024 19:24, Varshini Rajendran wrote:
> Add DT bindings for atmel TDES.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>

This would have deserved a better commit message, I (we) spent a lot of
time deciding whether this is the correct approach.
https://lore.kernel.org/linux-arm-kernel/342de8f3-852f-9bfa-39c4-4d820f349305@linaro.org/

Anyway:
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>

> ---
> Changes in v4:
> - Updated Acked-by tag
> ---
>  .../devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml  | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml
> index 3d6ed24b1b00..6a441f79efea 100644
> --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml
> +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml
> @@ -12,7 +12,11 @@ maintainers:
>  
>  properties:
>    compatible:
> -    const: atmel,at91sam9g46-tdes
> +    oneOf:
> +      - const: atmel,at91sam9g46-tdes
> +      - items:
> +          - const: microchip,sam9x7-tdes
> +          - const: atmel,at91sam9g46-tdes
>  
>    reg:
>      maxItems: 1

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[PATCH v4 06/39] dt-bindings: i2c: at91: Add sam9x7 compatible string

[Varshini Rajendran]

Add compatible string for sam9x7.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v4:
- Made sam9x7 compatible as an enum with sama7g5 compatible
- Removed the sam9x7 compatible from allOf section as it was not needed
  like pointed out
---
 Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml b/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml
index 6adedd3ec399..b1c13bab2472 100644
--- a/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml
@@ -25,7 +25,9 @@ properties:
               - atmel,sama5d2-i2c
               - microchip,sam9x60-i2c
       - items:
-          - const: microchip,sama7g5-i2c
+          - enum:
+              - microchip,sama7g5-i2c
+              - microchip,sam9x7-i2c
           - const: microchip,sam9x60-i2c
 
   reg:
-- 
2.25.1


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Re: [PATCH v4 06/39] dt-bindings: i2c: at91: Add sam9x7 compatible string

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1266 bytes --]

On Fri, Feb 23, 2024 at 10:54:59PM +0530, Varshini Rajendran wrote:
> Add compatible string for sam9x7.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

> ---
> Changes in v4:
> - Made sam9x7 compatible as an enum with sama7g5 compatible
> - Removed the sam9x7 compatible from allOf section as it was not needed
>   like pointed out
> ---
>  Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml b/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml
> index 6adedd3ec399..b1c13bab2472 100644
> --- a/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml
> +++ b/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml
> @@ -25,7 +25,9 @@ properties:
>                - atmel,sama5d2-i2c
>                - microchip,sam9x60-i2c
>        - items:
> -          - const: microchip,sama7g5-i2c
> +          - enum:
> +              - microchip,sama7g5-i2c
> +              - microchip,sam9x7-i2c
>            - const: microchip,sam9x60-i2c
>  
>    reg:
> -- 
> 2.25.1
> 

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[PATCH v4 07/39] dt-bindings: atmel-ssc: add microchip,sam9x7-ssc

[Varshini Rajendran]

Add microchip,sam9x7-ssc to DT bindings documentation.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Changes in v4:
- Updated Acked-by tag
---
 Documentation/devicetree/bindings/misc/atmel-ssc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/misc/atmel-ssc.txt b/Documentation/devicetree/bindings/misc/atmel-ssc.txt
index f9fb412642fe..894875826de9 100644
--- a/Documentation/devicetree/bindings/misc/atmel-ssc.txt
+++ b/Documentation/devicetree/bindings/misc/atmel-ssc.txt
@@ -2,6 +2,7 @@
 
 Required properties:
 - compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc"
+	       or "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc"
 	- atmel,at91rm9200-ssc: support pdc transfer
 	- atmel,at91sam9g45-ssc: support dma transfer
 - reg: Should contain SSC registers location and length
-- 
2.25.1


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[PATCH v4 08/39] dt-bindings: atmel-nand: add microchip,sam9x7-pmecc

[Varshini Rajendran]

Add microchip,sam9x7-pmecc to DT bindings documentation.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 Documentation/devicetree/bindings/mtd/atmel-nand.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index 50645828ac20..4598930851d9 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -56,6 +56,7 @@ Required properties:
 	"atmel,sama5d4-pmecc"
 	"atmel,sama5d2-pmecc"
 	"microchip,sam9x60-pmecc"
+	"microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"
 - reg: should contain 2 register ranges. The first one is pointing to the PMECC
        block, and the second one to the PMECC_ERRLOC block.
 
-- 
2.25.1


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Re: [PATCH v4 08/39] dt-bindings: atmel-nand: add microchip,sam9x7-pmecc

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1039 bytes --]

On Fri, Feb 23, 2024 at 10:55:20PM +0530, Varshini Rajendran wrote:
> Add microchip,sam9x7-pmecc to DT bindings documentation.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

> ---
>  Documentation/devicetree/bindings/mtd/atmel-nand.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> index 50645828ac20..4598930851d9 100644
> --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
> @@ -56,6 +56,7 @@ Required properties:
>  	"atmel,sama5d4-pmecc"
>  	"atmel,sama5d2-pmecc"
>  	"microchip,sam9x60-pmecc"
> +	"microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"
>  - reg: should contain 2 register ranges. The first one is pointing to the PMECC
>         block, and the second one to the PMECC_ERRLOC block.
>  
> -- 
> 2.25.1
> 

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Re: [PATCH v4 08/39] dt-bindings: atmel-nand: add microchip,sam9x7-pmecc

[Miquel Raynal]

On Fri, 2024-02-23 at 17:25:20 UTC, Varshini Rajendran wrote:
> Add microchip,sam9x7-pmecc to DT bindings documentation.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>

Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.

Miquel

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[PATCH v4 09/39] dt-bindings: pinctrl: at91: add sam9x7

[Varshini Rajendran]

Add device tree binding for SAM9X7 pin controller.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Changes in v4:
- Updated Acked-by tag
---
 .../devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt          | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index e8abbdad7b5d..0aa1a53012d6 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -20,6 +20,7 @@ such as pull-up, multi drive, etc.
 Required properties for iomux controller:
 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
 		or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
+		or "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl"
 - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
   configured in this periph mode. All the periph and bank need to be describe.
 
@@ -120,6 +121,7 @@ Some requirements for using atmel,at91rm9200-pinctrl binding:
 For each bank the required properties are:
 - compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or
   "microchip,sam9x60-gpio"
+  or "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"
 - reg: physical base address and length of the controller's registers
 - interrupts: interrupt outputs from the controller
 - interrupt-controller: marks the device node as an interrupt controller
-- 
2.25.1


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Re: [PATCH v4 09/39] dt-bindings: pinctrl: at91: add sam9x7

[Linus Walleij]

On Fri, Feb 23, 2024 at 6:25 PM Varshini Rajendran
<varshini.rajendran@microchip.com> wrote:

> Add device tree binding for SAM9X7 pin controller.
>
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

This one patch applied to the pinctrl tree.

Yours,
Linus Walleij

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[PATCH v4 10/39] dt-bindings: rng: atmel,at91-trng: add sam9x7 TRNG

[Varshini Rajendran]

Add compatbile for Microchip sam9x7 TRNG.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Changes in v4:
- Updated Reviewed-by tag
---
 Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml b/Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml
index 3ce45456d867..b38f8252342e 100644
--- a/Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml
+++ b/Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml
@@ -21,6 +21,10 @@ properties:
           - enum:
               - microchip,sama7g5-trng
           - const: atmel,at91sam9g45-trng
+      - items:
+          - enum:
+              - microchip,sam9x7-trng
+          - const: microchip,sam9x60-trng
 
   clocks:
     maxItems: 1
-- 
2.25.1


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[PATCH v4 11/39] dt-bindings: rtt: at91rm9260: add sam9x7 compatible

[Varshini Rajendran]

Add compatible for SAM9X7 RTT.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v4:
- Made sam9x7 compatible as an enum with sam9x60 compatible as
  suggested
---
 .../devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml        | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml
index b80b85c394ac..a7f6c1d1a08a 100644
--- a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml
+++ b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml
@@ -19,7 +19,9 @@ properties:
       - items:
           - const: atmel,at91sam9260-rtt
       - items:
-          - const: microchip,sam9x60-rtt
+          - enum:
+              - microchip,sam9x60-rtt
+              - microchip,sam9x7-rtt
           - const: atmel,at91sam9260-rtt
       - items:
           - const: microchip,sama7g5-rtt
-- 
2.25.1


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Re: [PATCH v4 11/39] dt-bindings: rtt: at91rm9260: add sam9x7 compatible

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1233 bytes --]

On Fri, Feb 23, 2024 at 10:55:52PM +0530, Varshini Rajendran wrote:
> Add compatible for SAM9X7 RTT.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

> ---
> Changes in v4:
> - Made sam9x7 compatible as an enum with sam9x60 compatible as
>   suggested
> ---
>  .../devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml        | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml
> index b80b85c394ac..a7f6c1d1a08a 100644
> --- a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml
> +++ b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml
> @@ -19,7 +19,9 @@ properties:
>        - items:
>            - const: atmel,at91sam9260-rtt
>        - items:
> -          - const: microchip,sam9x60-rtt
> +          - enum:
> +              - microchip,sam9x60-rtt
> +              - microchip,sam9x7-rtt
>            - const: atmel,at91sam9260-rtt
>        - items:
>            - const: microchip,sama7g5-rtt
> -- 
> 2.25.1
> 

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Re: (subset) [PATCH v4 11/39] dt-bindings: rtt: at91rm9260: add sam9x7 compatible

[Alexandre Belloni]

On Fri, 23 Feb 2024 22:55:52 +0530, Varshini Rajendran wrote:
> Add compatible for SAM9X7 RTT.
> 
> 

Applied, thanks!

[11/39] dt-bindings: rtt: at91rm9260: add sam9x7 compatible
        https://git.kernel.org/abelloni/c/16816e6a3693

Best regards,

-- 
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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[PATCH v4 12/39] dt-bindings: serial: atmel,at91-usart: add compatible for sam9x7.

[Varshini Rajendran]

Add sam9x7 compatible to DT bindings documentation.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v4:
- Fixed the wrong addition of compatible
- Added further compatibles that are possible correct (as per DT)
---
 .../devicetree/bindings/serial/atmel,at91-usart.yaml | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
index 65cb2e5c5eee..30af537e8e81 100644
--- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
+++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
@@ -23,11 +23,17 @@ properties:
           - const: atmel,at91sam9260-dbgu
           - const: atmel,at91sam9260-usart
       - items:
-          - const: microchip,sam9x60-usart
+          - enum:
+              - microchip,sam9x60-usart
+              - microchip,sam9x7-usart
           - const: atmel,at91sam9260-usart
       - items:
-          - const: microchip,sam9x60-dbgu
-          - const: microchip,sam9x60-usart
+          - enum:
+              - microchip,sam9x60-dbgu
+              - microchip,sam9x7-dbgu
+          - enum:
+              - microchip,sam9x60-usart
+              - microchip,sam9x7-usart
           - const: atmel,at91sam9260-dbgu
           - const: atmel,at91sam9260-usart
 
-- 
2.25.1


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Re: [PATCH v4 12/39] dt-bindings: serial: atmel,at91-usart: add compatible for sam9x7.

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 2347 bytes --]

On Fri, Feb 23, 2024 at 10:55:59PM +0530, Varshini Rajendran wrote:
> Add sam9x7 compatible to DT bindings documentation.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
> Changes in v4:
> - Fixed the wrong addition of compatible
> - Added further compatibles that are possible correct (as per DT)
> ---
>  .../devicetree/bindings/serial/atmel,at91-usart.yaml | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
> index 65cb2e5c5eee..30af537e8e81 100644
> --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
> +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
> @@ -23,11 +23,17 @@ properties:
>            - const: atmel,at91sam9260-dbgu
>            - const: atmel,at91sam9260-usart
>        - items:
> -          - const: microchip,sam9x60-usart
> +          - enum:
> +              - microchip,sam9x60-usart
> +              - microchip,sam9x7-usart
>            - const: atmel,at91sam9260-usart
>        - items:
> -          - const: microchip,sam9x60-dbgu
> -          - const: microchip,sam9x60-usart
> +          - enum:
> +              - microchip,sam9x60-dbgu
> +              - microchip,sam9x7-dbgu

> +          - enum:
> +              - microchip,sam9x60-usart
> +              - microchip,sam9x7-usart

This doesn't make sense - this enum should be a const.
I don't really understand the idea behind of the original binding here that
allowed:
"microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"

Specifically, I don't get the purpose of the "microchip,sam9x60-usart".
Either make it
      - items:
          - enum:
              - microchip,sam9x60-dbgu
              - microchip,sam9x7-dbgu
          - const: microchip,sam9x60-usart
          - const: atmel,at91sam9260-dbgu
          - const: atmel,at91sam9260-usart
or add
      - items:
          - const: microchip,sam9x60-dbgu
          - const: atmel,at91sam9260-dbgu
          - const: atmel,at91sam9260-usart
or explain exactly why this needs to be
"chipa-dgbu", "chipa-usart", "chipb-dbgu", "chipb-dbgu"

Thanks,
Conor.


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Re: [PATCH v4 12/39] dt-bindings: serial: atmel,at91-usart: add compatible for sam9x7.

[Varshini.Rajendran]

Hi Conor,

On 25/02/24 1:32 am, Conor Dooley wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> On Fri, Feb 23, 2024 at 10:55:59PM +0530, Varshini Rajendran wrote:
>> Add sam9x7 compatible to DT bindings documentation.
>>
>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>> ---
>> Changes in v4:
>> - Fixed the wrong addition of compatible
>> - Added further compatibles that are possible correct (as per DT)
>> ---
>>  .../devicetree/bindings/serial/atmel,at91-usart.yaml | 12 +++++++++---
>>  1 file changed, 9 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
>> index 65cb2e5c5eee..30af537e8e81 100644
>> --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
>> +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
>> @@ -23,11 +23,17 @@ properties:
>>            - const: atmel,at91sam9260-dbgu
>>            - const: atmel,at91sam9260-usart
>>        - items:
>> -          - const: microchip,sam9x60-usart
>> +          - enum:
>> +              - microchip,sam9x60-usart
>> +              - microchip,sam9x7-usart
>>            - const: atmel,at91sam9260-usart
>>        - items:
>> -          - const: microchip,sam9x60-dbgu
>> -          - const: microchip,sam9x60-usart
>> +          - enum:
>> +              - microchip,sam9x60-dbgu
>> +              - microchip,sam9x7-dbgu
> 
>> +          - enum:
>> +              - microchip,sam9x60-usart
>> +              - microchip,sam9x7-usart
> 
> This doesn't make sense - this enum should be a const.
> I don't really understand the idea behind of the original binding here that
> allowed:
> "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"
> 
> Specifically, I don't get the purpose of the "microchip,sam9x60-usart".
> Either make it
>       - items:
>           - enum:
>               - microchip,sam9x60-dbgu
>               - microchip,sam9x7-dbgu
>           - const: microchip,sam9x60-usart
>           - const: atmel,at91sam9260-dbgu
>           - const: atmel,at91sam9260-usart
> or add
>       - items:
>           - const: microchip,sam9x60-dbgu
>           - const: atmel,at91sam9260-dbgu
>           - const: atmel,at91sam9260-usart
> or explain exactly why this needs to be
> "chipa-dgbu", "chipa-usart", "chipb-dbgu", "chipb-dbgu"
The compatible has to be "chipa-usart", "chipb-usart", "chipa-dbgu", 
"chipb-dbgu" for the device to work as a debug console over UART
wher the chipa-<periph> is the device specific compatible
and the chipb-<periph> is the fallback compatible that the driver 
actually uses.

Maybe putting the 2 compatibles as 2 enums is not right. I will rephrase 
it as below.

       - items:
           - const: microchip,sam9x60-dbgu
           - const: microchip,sam9x60-usart
           - const: atmel,at91sam9260-dbgu
           - const: atmel,at91sam9260-usart
       - items:
           - const: microchip,sam9x7-dbgu
           - const: microchip,sam9x7-usart
           - const: atmel,at91sam9260-dbgu
           - const: atmel,at91sam9260-usart

Hope this is fine.
> 
> Thanks,
> Conor.
> 

-- 
Thanks and Regards,
Varshini Rajendran.

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Re: [PATCH v4 12/39] dt-bindings: serial: atmel,at91-usart: add compatible for sam9x7.

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 3562 bytes --]

On Wed, Feb 28, 2024 at 07:03:01AM +0000, Varshini.Rajendran@microchip.com wrote:
> Hi Conor,
> 
> On 25/02/24 1:32 am, Conor Dooley wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > On Fri, Feb 23, 2024 at 10:55:59PM +0530, Varshini Rajendran wrote:
> >> Add sam9x7 compatible to DT bindings documentation.
> >>
> >> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> >> ---
> >> Changes in v4:
> >> - Fixed the wrong addition of compatible
> >> - Added further compatibles that are possible correct (as per DT)
> >> ---
> >>  .../devicetree/bindings/serial/atmel,at91-usart.yaml | 12 +++++++++---
> >>  1 file changed, 9 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
> >> index 65cb2e5c5eee..30af537e8e81 100644
> >> --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
> >> +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
> >> @@ -23,11 +23,17 @@ properties:
> >>            - const: atmel,at91sam9260-dbgu
> >>            - const: atmel,at91sam9260-usart
> >>        - items:
> >> -          - const: microchip,sam9x60-usart
> >> +          - enum:
> >> +              - microchip,sam9x60-usart
> >> +              - microchip,sam9x7-usart
> >>            - const: atmel,at91sam9260-usart
> >>        - items:
> >> -          - const: microchip,sam9x60-dbgu
> >> -          - const: microchip,sam9x60-usart
> >> +          - enum:
> >> +              - microchip,sam9x60-dbgu
> >> +              - microchip,sam9x7-dbgu
> > 
> >> +          - enum:
> >> +              - microchip,sam9x60-usart
> >> +              - microchip,sam9x7-usart
> > 
> > This doesn't make sense - this enum should be a const.
> > I don't really understand the idea behind of the original binding here that
> > allowed:
> > "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"
> > 
> > Specifically, I don't get the purpose of the "microchip,sam9x60-usart".
> > Either make it
> >       - items:
> >           - enum:
> >               - microchip,sam9x60-dbgu
> >               - microchip,sam9x7-dbgu
> >           - const: microchip,sam9x60-usart
> >           - const: atmel,at91sam9260-dbgu
> >           - const: atmel,at91sam9260-usart
> > or add
> >       - items:
> >           - const: microchip,sam9x60-dbgu
> >           - const: atmel,at91sam9260-dbgu
> >           - const: atmel,at91sam9260-usart
> > or explain exactly why this needs to be
> > "chipa-dgbu", "chipa-usart", "chipb-dbgu", "chipb-dbgu"
> The compatible has to be "chipa-usart", "chipb-usart", "chipa-dbgu", 
> "chipb-dbgu" for the device to work as a debug console over UART
> wher the chipa-<periph> is the device specific compatible
> and the chipb-<periph> is the fallback compatible that the driver 
> actually uses.

This examples why you have "microchip,sam9x60-dbgu", "atmel,at91sam9260-dbgu"
and "atmel,at91sam9260-usart".
It does not explain "microchip,sam9x60-usart" though, I don't see what
purpose that serves. If used as a debug uart, you fall back to the
sam9260 debug uart compatible and if not you fall back to the sam9260
usart compatible.

In addition, the current setup implies that sam9x60 usart supports all
the features that the sam9260 debug usart does. I doubt that that is
true.

Thanks,
Conor.

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Re: [PATCH v4 12/39] dt-bindings: serial: atmel,at91-usart: add compatible for sam9x7.

[Varshini.Rajendran]

Hi Conor,

On 28/02/24 5:19 pm, Conor Dooley wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> On Wed, Feb 28, 2024 at 07:03:01AM +0000, Varshini.Rajendran@microchip.com wrote:
>> Hi Conor,
>>
>> On 25/02/24 1:32 am, Conor Dooley wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>> On Fri, Feb 23, 2024 at 10:55:59PM +0530, Varshini Rajendran wrote:
>>>> Add sam9x7 compatible to DT bindings documentation.
>>>>
>>>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>>>> ---
>>>> Changes in v4:
>>>> - Fixed the wrong addition of compatible
>>>> - Added further compatibles that are possible correct (as per DT)
>>>> ---
>>>>  .../devicetree/bindings/serial/atmel,at91-usart.yaml | 12 +++++++++---
>>>>  1 file changed, 9 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
>>>> index 65cb2e5c5eee..30af537e8e81 100644
>>>> --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
>>>> +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
>>>> @@ -23,11 +23,17 @@ properties:
>>>>            - const: atmel,at91sam9260-dbgu
>>>>            - const: atmel,at91sam9260-usart
>>>>        - items:
>>>> -          - const: microchip,sam9x60-usart
>>>> +          - enum:
>>>> +              - microchip,sam9x60-usart
>>>> +              - microchip,sam9x7-usart
>>>>            - const: atmel,at91sam9260-usart
>>>>        - items:
>>>> -          - const: microchip,sam9x60-dbgu
>>>> -          - const: microchip,sam9x60-usart
>>>> +          - enum:
>>>> +              - microchip,sam9x60-dbgu
>>>> +              - microchip,sam9x7-dbgu
>>>
>>>> +          - enum:
>>>> +              - microchip,sam9x60-usart
>>>> +              - microchip,sam9x7-usart
>>>
>>> This doesn't make sense - this enum should be a const.
>>> I don't really understand the idea behind of the original binding here that
>>> allowed:
>>> "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"
>>>
>>> Specifically, I don't get the purpose of the "microchip,sam9x60-usart".
>>> Either make it
>>>       - items:
>>>           - enum:
>>>               - microchip,sam9x60-dbgu
>>>               - microchip,sam9x7-dbgu
>>>           - const: microchip,sam9x60-usart
>>>           - const: atmel,at91sam9260-dbgu
>>>           - const: atmel,at91sam9260-usart
>>> or add
>>>       - items:
>>>           - const: microchip,sam9x60-dbgu
>>>           - const: atmel,at91sam9260-dbgu
>>>           - const: atmel,at91sam9260-usart
>>> or explain exactly why this needs to be
>>> "chipa-dgbu", "chipa-usart", "chipb-dbgu", "chipb-dbgu"
>> The compatible has to be "chipa-usart", "chipb-usart", "chipa-dbgu", 
>> "chipb-dbgu" for the device to work as a debug console over UART
>> wher the chipa-<periph> is the device specific compatible
>> and the chipb-<periph> is the fallback compatible that the driver 
>> actually uses.
> 
> This examples why you have "microchip,sam9x60-dbgu", "atmel,at91sam9260-dbgu"
> and "atmel,at91sam9260-usart".
> It does not explain "microchip,sam9x60-usart" though, I don't see what
> purpose that serves. If used as a debug uart, you fall back to the
> sam9260 debug uart compatible and if not you fall back to the sam9260
> usart compatible.
> 
Here, if it is not used as debug uart it has to fallback to the default 
usart compatible which in this case should have a device specific 
compatible too right?

The common usart compatible looks as follows,

     compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";

meaning the 1st one is the device specific usart compatible and the 2nd 
one is the fallback compatible which the driver actually supports.

The debug uart looks as follows,

compatible = "microchip,sam9x60-dbgu", "atmel,at91sam9260-dbgu", 
"microchip,sam9x60-usart", "atmel,at91sam9260-usart";

In this case, there is a device specific debug uart compatible, a 
fallback tot he debug uart compatible and as you said if not used as a 
debug uart it should fallback and work as a normal uart device which has 
both a device specific compatible and a fallback to work.

In case the device specific compatible is supported with some other 
features in the driver in the future, the debug uart also should get its 
perk. Does this make sense?


> In addition, the current setup implies that sam9x60 usart supports all
> the features that the sam9260 debug usart does. I doubt that that is
> true.
> 
> Thanks,
> Conor.

-- 
Thanks and Regards,
Varshini Rajendran.

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Re: [PATCH v4 12/39] dt-bindings: serial: atmel,at91-usart: add compatible for sam9x7.

[Conor Dooley]

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On Thu, Feb 29, 2024 at 08:55:11AM +0000, Varshini.Rajendran@microchip.com wrote:
> Hi Conor,
> 
> On 28/02/24 5:19 pm, Conor Dooley wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > On Wed, Feb 28, 2024 at 07:03:01AM +0000, Varshini.Rajendran@microchip.com wrote:
> >> Hi Conor,
> >>
> >> On 25/02/24 1:32 am, Conor Dooley wrote:
> >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>> On Fri, Feb 23, 2024 at 10:55:59PM +0530, Varshini Rajendran wrote:
> >>>> Add sam9x7 compatible to DT bindings documentation.
> >>>>
> >>>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> >>>> ---
> >>>> Changes in v4:
> >>>> - Fixed the wrong addition of compatible
> >>>> - Added further compatibles that are possible correct (as per DT)
> >>>> ---
> >>>>  .../devicetree/bindings/serial/atmel,at91-usart.yaml | 12 +++++++++---
> >>>>  1 file changed, 9 insertions(+), 3 deletions(-)
> >>>>
> >>>> diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
> >>>> index 65cb2e5c5eee..30af537e8e81 100644
> >>>> --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
> >>>> +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
> >>>> @@ -23,11 +23,17 @@ properties:
> >>>>            - const: atmel,at91sam9260-dbgu
> >>>>            - const: atmel,at91sam9260-usart
> >>>>        - items:
> >>>> -          - const: microchip,sam9x60-usart
> >>>> +          - enum:
> >>>> +              - microchip,sam9x60-usart
> >>>> +              - microchip,sam9x7-usart
> >>>>            - const: atmel,at91sam9260-usart
> >>>>        - items:
> >>>> -          - const: microchip,sam9x60-dbgu
> >>>> -          - const: microchip,sam9x60-usart
> >>>> +          - enum:
> >>>> +              - microchip,sam9x60-dbgu
> >>>> +              - microchip,sam9x7-dbgu
> >>>
> >>>> +          - enum:
> >>>> +              - microchip,sam9x60-usart
> >>>> +              - microchip,sam9x7-usart
> >>>
> >>> This doesn't make sense - this enum should be a const.
> >>> I don't really understand the idea behind of the original binding here that
> >>> allowed:
> >>> "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"
> >>>
> >>> Specifically, I don't get the purpose of the "microchip,sam9x60-usart".
> >>> Either make it
> >>>       - items:
> >>>           - enum:
> >>>               - microchip,sam9x60-dbgu
> >>>               - microchip,sam9x7-dbgu
> >>>           - const: microchip,sam9x60-usart
> >>>           - const: atmel,at91sam9260-dbgu
> >>>           - const: atmel,at91sam9260-usart
> >>> or add
> >>>       - items:
> >>>           - const: microchip,sam9x60-dbgu
> >>>           - const: atmel,at91sam9260-dbgu
> >>>           - const: atmel,at91sam9260-usart
> >>> or explain exactly why this needs to be
> >>> "chipa-dgbu", "chipa-usart", "chipb-dbgu", "chipb-dbgu"
> >> The compatible has to be "chipa-usart", "chipb-usart", "chipa-dbgu", 
> >> "chipb-dbgu" for the device to work as a debug console over UART
> >> wher the chipa-<periph> is the device specific compatible
> >> and the chipb-<periph> is the fallback compatible that the driver 
> >> actually uses.
> > 
> > This examples why you have "microchip,sam9x60-dbgu", "atmel,at91sam9260-dbgu"
> > and "atmel,at91sam9260-usart".
> > It does not explain "microchip,sam9x60-usart" though, I don't see what
> > purpose that serves. If used as a debug uart, you fall back to the
> > sam9260 debug uart compatible and if not you fall back to the sam9260
> > usart compatible.
> > 
> Here, if it is not used as debug uart it has to fallback to the default 
> usart compatible which in this case should have a device specific 
> compatible too right?
> 
> The common usart compatible looks as follows,
> 
>      compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> 
> meaning the 1st one is the device specific usart compatible and the 2nd 
> one is the fallback compatible which the driver actually supports.
> 
> The debug uart looks as follows,
> 
> compatible = "microchip,sam9x60-dbgu", "atmel,at91sam9260-dbgu", 
> "microchip,sam9x60-usart", "atmel,at91sam9260-usart";

This version here makes a lot more sense than what is currently in use
and what is being added in your original patch. I wouldn't object to
this being used.

> In this case, there is a device specific debug uart compatible, a 
> fallback tot he debug uart compatible and as you said if not used as a 
> debug uart it should fallback and work as a normal uart device which has 
> both a device specific compatible and a fallback to work.
> 
> In case the device specific compatible is supported with some other 
> features in the driver in the future, the debug uart also should get its 
> perk. Does this make sense?
> 
> 
> > In addition, the current setup implies that sam9x60 usart supports all
> > the features that the sam9260 debug usart does. I doubt that that is
> > true.

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[PATCH v4 13/39] ASoC: dt-bindings: atmel-classd: add sam9x7 compatible

[Varshini Rajendran]

Add sam9x7 compatible to DT bindings documentation.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v4:
- Changed the subject prefix matching the subsystem
- Removed unwanted '-items' from the syntax
---
 .../devicetree/bindings/sound/atmel,sama5d2-classd.yaml    | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.yaml b/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.yaml
index 43d04702ac2d..ae3162fcfe02 100644
--- a/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.yaml
+++ b/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.yaml
@@ -18,7 +18,12 @@ description:
 
 properties:
   compatible:
-    const: atmel,sama5d2-classd
+    oneOf:
+      - items:
+          - const: atmel,sama5d2-classd
+      - items:
+          - const: microchip,sam9x7-classd
+          - const: atmel,sama5d2-classd
 
   reg:
     maxItems: 1
-- 
2.25.1


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Re: [PATCH v4 13/39] ASoC: dt-bindings: atmel-classd: add sam9x7 compatible

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1229 bytes --]

On Fri, Feb 23, 2024 at 10:56:08PM +0530, Varshini Rajendran wrote:
> Add sam9x7 compatible to DT bindings documentation.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
> Changes in v4:
> - Changed the subject prefix matching the subsystem

> - Removed unwanted '-items' from the syntax

Did you? The diff looks identical to v3.

Thanks,
Conor.

> ---
>  .../devicetree/bindings/sound/atmel,sama5d2-classd.yaml    | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.yaml b/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.yaml
> index 43d04702ac2d..ae3162fcfe02 100644
> --- a/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.yaml
> +++ b/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.yaml
> @@ -18,7 +18,12 @@ description:
>  
>  properties:
>    compatible:
> -    const: atmel,sama5d2-classd
> +    oneOf:
> +      - items:
> +          - const: atmel,sama5d2-classd
> +      - items:
> +          - const: microchip,sam9x7-classd
> +          - const: atmel,sama5d2-classd
>  
>    reg:
>      maxItems: 1
> -- 
> 2.25.1
> 

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[PATCH v4 14/39] dt-bindings: pwm: at91: Add sam9x7 compatible strings list

[Varshini Rajendran]

Add compatible strings list for SAM9X7.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml b/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml
index d84268b59784..96cd6f3c3546 100644
--- a/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml
@@ -25,6 +25,9 @@ properties:
       - items:
           - const: microchip,sama7g5-pwm
           - const: atmel,sama5d2-pwm
+      - items:
+          - const: microchip,sam9x7-pwm
+          - const: microchip,sam9x60-pwm
 
   reg:
     maxItems: 1
-- 
2.25.1


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Re: [PATCH v4 14/39] dt-bindings: pwm: at91: Add sam9x7 compatible strings list

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1010 bytes --]

On Fri, Feb 23, 2024 at 10:56:19PM +0530, Varshini Rajendran wrote:
> Add compatible strings list for SAM9X7.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

> ---
>  Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml b/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml
> index d84268b59784..96cd6f3c3546 100644
> --- a/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml
> +++ b/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml
> @@ -25,6 +25,9 @@ properties:
>        - items:
>            - const: microchip,sama7g5-pwm
>            - const: atmel,sama5d2-pwm
> +      - items:
> +          - const: microchip,sam9x7-pwm
> +          - const: microchip,sam9x60-pwm
>  
>    reg:
>      maxItems: 1
> -- 
> 2.25.1
> 

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Re: [PATCH v4 14/39] dt-bindings: pwm: at91: Add sam9x7 compatible strings list

[Uwe Kleine-König]

[-- Attachment #1.1: Type: text/plain, Size: 779 bytes --]

Hello,

On Fri, Feb 23, 2024 at 11:42:57PM +0100, Uwe Kleine-König wrote:
> What is the merge plan for this series? I'd expect it to go in
> completely via arm-soc. If you want me to pick up this patch, please
> tell me.

Other maintainers picked some patches from this thread and I didn't get
an answer to my question. To be able to close this thread on my side I
applied this patch now to my for-nexxt branch

	https://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux.git for-nexxt

. This is expected to be rebased once v6.9-rc1 is available, but it
won't get lost this way.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | https://www.pengutronix.de/ |

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[PATCH v4 15/39] dt-bindings: watchdog: sama5d4-wdt: add compatible for sam9x7-wdt

[Varshini Rajendran]

Add compatible microchip,sam9x7-wdt to DT bindings documentation.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v4:
- Removed unnecessary '-items' from the syntax
- Changed enum as const as per the comment
---
 .../bindings/watchdog/atmel,sama5d4-wdt.yaml         | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml b/Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml
index 816f85ee2c77..cdf87db36183 100644
--- a/Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml
@@ -14,10 +14,14 @@ allOf:
 
 properties:
   compatible:
-    enum:
-      - atmel,sama5d4-wdt
-      - microchip,sam9x60-wdt
-      - microchip,sama7g5-wdt
+    oneOf:
+      - enum:
+          - atmel,sama5d4-wdt
+          - microchip,sam9x60-wdt
+          - microchip,sama7g5-wdt
+      - items:
+          - const: microchip,sam9x7-wdt
+          - const: microchip,sam9x60-wdt
 
   reg:
     maxItems: 1
-- 
2.25.1


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Re: [PATCH v4 15/39] dt-bindings: watchdog: sama5d4-wdt: add compatible for sam9x7-wdt

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 288 bytes --]

On Fri, Feb 23, 2024 at 10:56:27PM +0530, Varshini Rajendran wrote:
> Add compatible microchip,sam9x7-wdt to DT bindings documentation.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

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[PATCH v4 16/39] spi: dt-bindings: atmel,at91rm9200-spi: remove 9x60 compatible from list

[Varshini Rajendran]

Remove microchip,sam9x60-spi compatible from the list as the driver used
has the compatible atmel,at91rm9200-spi and sam9x60 devices also use the
same compatible as fallback. So removing the microchip,sam9x60-spi
compatible from the list since it is not needed.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v4:
- Elaborated the explanation in the commit message to justify the patch
---
 Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml | 1 -
 1 file changed, 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml
index 58367587bfbc..32e7c14033c2 100644
--- a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml
@@ -22,7 +22,6 @@ properties:
           - const: atmel,at91rm9200-spi
       - items:
           - const: microchip,sam9x7-spi
-          - const: microchip,sam9x60-spi
           - const: atmel,at91rm9200-spi
 
   reg:
-- 
2.25.1


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Re: [PATCH v4 16/39] spi: dt-bindings: atmel,at91rm9200-spi: remove 9x60 compatible from list

[Tudor Ambarus]

On 23.02.2024 19:26, Varshini Rajendran wrote:
> Remove microchip,sam9x60-spi compatible from the list as the driver used
> has the compatible atmel,at91rm9200-spi and sam9x60 devices also use the
> same compatible as fallback. So removing the microchip,sam9x60-spi
> compatible from the list since it is not needed.
> 

I find this wrong. I though we shall add compatibles for each SoC. Are
the registers and fields the same for the SPI IPs in these 2 SoCs? Even
if they are the same, are you sure the IPs are integrated in the same way?

> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
> Changes in v4:
> - Elaborated the explanation in the commit message to justify the patch
> ---
>  Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml
> index 58367587bfbc..32e7c14033c2 100644
> --- a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml
> +++ b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml
> @@ -22,7 +22,6 @@ properties:
>            - const: atmel,at91rm9200-spi
>        - items:
>            - const: microchip,sam9x7-spi
> -          - const: microchip,sam9x60-spi
>            - const: atmel,at91rm9200-spi
>  
>    reg:

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Re: [PATCH v4 16/39] spi: dt-bindings: atmel,at91rm9200-spi: remove 9x60 compatible from list

[Varshini.Rajendran]

Hi Tudor,

On 26/02/24 2:39 pm, Tudor Ambarus wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 23.02.2024 19:26, Varshini Rajendran wrote:
>> Remove microchip,sam9x60-spi compatible from the list as the driver used
>> has the compatible atmel,at91rm9200-spi and sam9x60 devices also use the
>> same compatible as fallback. So removing the microchip,sam9x60-spi
>> compatible from the list since it is not needed.
>>
> 
> I find this wrong. I though we shall add compatibles for each SoC. Are
> the registers and fields the same for the SPI IPs in these 2 SoCs? Even
> if they are the same, are you sure the IPs are integrated in the same way?

Which two SoCs are you referring to ?
I am not removing the device specific compatible. I am only removing the 
additional fallback compatible.

As in,

compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";

instead of,

compatible = "microchip,sam9x7-spi", "microchip,sam9x60-spi", 
"atmel,at91rm9200-spi";

for the sam9x7 devices.

Hope this is clear. If I have it wrong please let me know.

> 
>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>> ---
>> Changes in v4:
>> - Elaborated the explanation in the commit message to justify the patch
>> ---
>>   Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml | 1 -
>>   1 file changed, 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml
>> index 58367587bfbc..32e7c14033c2 100644
>> --- a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml
>> +++ b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml
>> @@ -22,7 +22,6 @@ properties:
>>             - const: atmel,at91rm9200-spi
>>         - items:
>>             - const: microchip,sam9x7-spi
>> -          - const: microchip,sam9x60-spi
>>             - const: atmel,at91rm9200-spi
>>
>>     reg:

-- 
Thanks and Regards,
Varshini Rajendran.

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Re: [PATCH v4 16/39] spi: dt-bindings: atmel,at91rm9200-spi: remove 9x60 compatible from list

[Tudor Ambarus]

On 2/28/24 09:28, Varshini.Rajendran@microchip.com wrote:
> Hi Tudor,
> 
> On 26/02/24 2:39 pm, Tudor Ambarus wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 23.02.2024 19:26, Varshini Rajendran wrote:
>>> Remove microchip,sam9x60-spi compatible from the list as the driver used
>>> has the compatible atmel,at91rm9200-spi and sam9x60 devices also use the
>>> same compatible as fallback. So removing the microchip,sam9x60-spi
>>> compatible from the list since it is not needed.
>>>
>>
>> I find this wrong. I though we shall add compatibles for each SoC. Are
>> the registers and fields the same for the SPI IPs in these 2 SoCs? Even
>> if they are the same, are you sure the IPs are integrated in the same way?
> 
> Which two SoCs are you referring to ?
> I am not removing the device specific compatible. I am only removing the 
> additional fallback compatible.
> 

ah, I read it wrong, sorry
> As in,
> 
> compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
> 
> instead of,
> 
> compatible = "microchip,sam9x7-spi", "microchip,sam9x60-spi", 
> "atmel,at91rm9200-spi";
> 
> for the sam9x7 devices.
> 
> Hope this is clear. If I have it wrong please let me know.

it's clear now, thanks.

I see in the driver that microchip,sam9x60-spi compatible is not yet
used, thus removing the fallback to "microchip,sam9x60-spi" brings no
functional change. Would have made a difference if sam9x60-spi
implemented additional support that sam9x7-spi could have used as a
fallback. If you think that sam9x7-spi will not fallback to sam9x60-spi
in the future then:

Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>

> 
>>
>>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>>> ---
>>> Changes in v4:
>>> - Elaborated the explanation in the commit message to justify the patch
>>> ---
>>>   Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml | 1 -
>>>   1 file changed, 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml
>>> index 58367587bfbc..32e7c14033c2 100644
>>> --- a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml
>>> +++ b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml
>>> @@ -22,7 +22,6 @@ properties:
>>>             - const: atmel,at91rm9200-spi
>>>         - items:
>>>             - const: microchip,sam9x7-spi
>>> -          - const: microchip,sam9x60-spi
>>>             - const: atmel,at91rm9200-spi
>>>
>>>     reg:
> 

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[PATCH v4 18/39] ARM: at91: pm: add support for sam9x7 SoC family

[Varshini Rajendran]

Add support and pm init config for sam9x7 SoC.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/mach-at91/generic.h |  2 ++
 arch/arm/mach-at91/pm.c      | 35 +++++++++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+)

diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 0c3960a8b3eb..acf0b3c82a30 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -12,6 +12,7 @@
 extern void __init at91rm9200_pm_init(void);
 extern void __init at91sam9_pm_init(void);
 extern void __init sam9x60_pm_init(void);
+extern void __init sam9x7_pm_init(void);
 extern void __init sama5_pm_init(void);
 extern void __init sama5d2_pm_init(void);
 extern void __init sama7_pm_init(void);
@@ -19,6 +20,7 @@ extern void __init sama7_pm_init(void);
 static inline void __init at91rm9200_pm_init(void) { }
 static inline void __init at91sam9_pm_init(void) { }
 static inline void __init sam9x60_pm_init(void) { }
+static inline void __init sam9x7_pm_init(void) { }
 static inline void __init sama5_pm_init(void) { }
 static inline void __init sama5d2_pm_init(void) { }
 static inline void __init sama7_pm_init(void) { }
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 345b91dc6627..b81556387aa3 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -233,6 +233,17 @@ static const struct of_device_id sama7g5_ws_ids[] = {
 	{ /* sentinel */ }
 };
 
+static const struct of_device_id sam9x7_ws_ids[] = {
+	{ .compatible = "microchip,sam9x60-rtc",	.data = &ws_info[1] },
+	{ .compatible = "atmel,at91rm9200-ohci",	.data = &ws_info[2] },
+	{ .compatible = "usb-ohci",			.data = &ws_info[2] },
+	{ .compatible = "atmel,at91sam9g45-ehci",	.data = &ws_info[2] },
+	{ .compatible = "usb-ehci",			.data = &ws_info[2] },
+	{ .compatible = "microchip,sam9x60-rtt",	.data = &ws_info[4] },
+	{ .compatible = "microchip,sam9x7-gem",		.data = &ws_info[5] },
+	{ /* sentinel */ }
+};
+
 static int at91_pm_config_ws(unsigned int pm_mode, bool set)
 {
 	const struct wakeup_source_info *wsi;
@@ -1135,6 +1146,7 @@ static const struct of_device_id gmac_ids[] __initconst = {
 	{ .compatible = "atmel,sama5d2-gem" },
 	{ .compatible = "atmel,sama5d29-gem" },
 	{ .compatible = "microchip,sama7g5-gem" },
+	{ .compatible = "microchip,sam9x7-gem" },
 	{ },
 };
 
@@ -1362,6 +1374,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
 	{ .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
 	{ .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
 	{ .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
+	{ .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
 	{ /* sentinel */ },
 };
 
@@ -1499,6 +1512,28 @@ void __init sam9x60_pm_init(void)
 	soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
 }
 
+void __init sam9x7_pm_init(void)
+{
+	static const int modes[] __initconst = {
+		AT91_PM_STANDBY, AT91_PM_ULP0,
+	};
+
+	int ret;
+
+	if (!IS_ENABLED(CONFIG_SOC_SAM9X7))
+		return;
+
+	at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
+	ret = at91_dt_ramc(false);
+	if (ret)
+		return;
+
+	at91_pm_init(NULL);
+
+	soc_pm.ws_ids = sam9x7_ws_ids;
+	soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
+}
+
 void __init at91sam9_pm_init(void)
 {
 	int ret;
-- 
2.25.1


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Re: [PATCH v4 18/39] ARM: at91: pm: add support for sam9x7 SoC family

[claudiu beznea]

Hi, Varshini,

On 23.02.2024 19:27, Varshini Rajendran wrote:
> Add support and pm init config for sam9x7 SoC.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  arch/arm/mach-at91/generic.h |  2 ++
>  arch/arm/mach-at91/pm.c      | 35 +++++++++++++++++++++++++++++++++++
>  2 files changed, 37 insertions(+)
> 
> diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
> index 0c3960a8b3eb..acf0b3c82a30 100644
> --- a/arch/arm/mach-at91/generic.h
> +++ b/arch/arm/mach-at91/generic.h
> @@ -12,6 +12,7 @@
>  extern void __init at91rm9200_pm_init(void);
>  extern void __init at91sam9_pm_init(void);
>  extern void __init sam9x60_pm_init(void);
> +extern void __init sam9x7_pm_init(void);
>  extern void __init sama5_pm_init(void);
>  extern void __init sama5d2_pm_init(void);
>  extern void __init sama7_pm_init(void);
> @@ -19,6 +20,7 @@ extern void __init sama7_pm_init(void);
>  static inline void __init at91rm9200_pm_init(void) { }
>  static inline void __init at91sam9_pm_init(void) { }
>  static inline void __init sam9x60_pm_init(void) { }
> +static inline void __init sam9x7_pm_init(void) { }
>  static inline void __init sama5_pm_init(void) { }
>  static inline void __init sama5d2_pm_init(void) { }
>  static inline void __init sama7_pm_init(void) { }
> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> index 345b91dc6627..b81556387aa3 100644
> --- a/arch/arm/mach-at91/pm.c
> +++ b/arch/arm/mach-at91/pm.c
> @@ -233,6 +233,17 @@ static const struct of_device_id sama7g5_ws_ids[] = {
>  	{ /* sentinel */ }
>  };
>  
> +static const struct of_device_id sam9x7_ws_ids[] = {
> +	{ .compatible = "microchip,sam9x60-rtc",	.data = &ws_info[1] },

microchip,sam9x7-rtc

> +	{ .compatible = "atmel,at91rm9200-ohci",	.data = &ws_info[2] },
> +	{ .compatible = "usb-ohci",			.data = &ws_info[2] },
> +	{ .compatible = "atmel,at91sam9g45-ehci",	.data = &ws_info[2] },
> +	{ .compatible = "usb-ehci",			.data = &ws_info[2] },

These 4 are not present in the sam9x7 dtsi.

> +	{ .compatible = "microchip,sam9x60-rtt",	.data = &ws_info[4] },

microchip,sam9x7-rtt

> +	{ .compatible = "microchip,sam9x7-gem",		.data = &ws_info[5] },
> +	{ /* sentinel */ }
> +};
> +
>  static int at91_pm_config_ws(unsigned int pm_mode, bool set)
>  {
>  	const struct wakeup_source_info *wsi;
> @@ -1135,6 +1146,7 @@ static const struct of_device_id gmac_ids[] __initconst = {
>  	{ .compatible = "atmel,sama5d2-gem" },
>  	{ .compatible = "atmel,sama5d29-gem" },
>  	{ .compatible = "microchip,sama7g5-gem" },
> +	{ .compatible = "microchip,sam9x7-gem" },

AT91_PM_IOMAP(ETHC) is not in the list of any PM mode iomaps, thus, this is
not used at the moment. You can remove it and add (proper compatibles)
when needed, if any.

>  	{ },
>  };
>  
> @@ -1362,6 +1374,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
>  	{ .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
>  	{ .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
>  	{ .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
> +	{ .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
>  	{ /* sentinel */ },
>  };
>  
> @@ -1499,6 +1512,28 @@ void __init sam9x60_pm_init(void)
>  	soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
>  }
>  
> +void __init sam9x7_pm_init(void)
> +{
> +	static const int modes[] __initconst = {
> +		AT91_PM_STANDBY, AT91_PM_ULP0,
> +	};
> +

You can remove this blank line.

> +	int ret;
> +
> +	if (!IS_ENABLED(CONFIG_SOC_SAM9X7))
> +		return;
> +
> +	at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
> +	ret = at91_dt_ramc(false);
> +	if (ret)
> +		return;
> +
> +	at91_pm_init(NULL);
> +
> +	soc_pm.ws_ids = sam9x7_ws_ids;
> +	soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
> +}
> +
>  void __init at91sam9_pm_init(void)
>  {
>  	int ret;

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[PATCH v4 19/39] ARM: at91: pm: add sam9x7 SoC init config

[Varshini Rajendran]

Add SoC init config for sam9x7 family.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 arch/arm/mach-at91/Makefile |  1 +
 arch/arm/mach-at91/sam9x7.c | 34 ++++++++++++++++++++++++++++++++++
 2 files changed, 35 insertions(+)
 create mode 100644 arch/arm/mach-at91/sam9x7.c

diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 794bd12ab0a8..7d8a7bc44e65 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -7,6 +7,7 @@
 obj-$(CONFIG_SOC_AT91RM9200)	+= at91rm9200.o
 obj-$(CONFIG_SOC_AT91SAM9)	+= at91sam9.o
 obj-$(CONFIG_SOC_SAM9X60)	+= sam9x60.o
+obj-$(CONFIG_SOC_SAM9X7)	+= sam9x7.o
 obj-$(CONFIG_SOC_SAMA5)		+= sama5.o sam_secure.o
 obj-$(CONFIG_SOC_SAMA7)		+= sama7.o
 obj-$(CONFIG_SOC_SAMV7)		+= samv7.o
diff --git a/arch/arm/mach-at91/sam9x7.c b/arch/arm/mach-at91/sam9x7.c
new file mode 100644
index 000000000000..d998fb327860
--- /dev/null
+++ b/arch/arm/mach-at91/sam9x7.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Setup code for SAM9X7.
+ *
+ * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
+ */
+
+#include <linux/of.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach/arch.h>
+#include <asm/system_misc.h>
+
+#include "generic.h"
+
+static void __init sam9x7_init(void)
+{
+	of_platform_default_populate(NULL, NULL, NULL);
+
+	sam9x7_pm_init();
+}
+
+static const char *const sam9x7_dt_board_compat[] __initconst = {
+	"microchip,sam9x7",
+	NULL
+};
+
+DT_MACHINE_START(sam9x7_dt, "Microchip SAM9X7")
+	/* Maintainer: Microchip */
+	.init_machine	= sam9x7_init,
+	.dt_compat	= sam9x7_dt_board_compat,
+MACHINE_END
-- 
2.25.1


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Re: [PATCH v4 19/39] ARM: at91: pm: add sam9x7 SoC init config

[claudiu beznea]

On 23.02.2024 19:27, Varshini Rajendran wrote:
> Add SoC init config for sam9x7 family.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  arch/arm/mach-at91/Makefile |  1 +
>  arch/arm/mach-at91/sam9x7.c | 34 ++++++++++++++++++++++++++++++++++
>  2 files changed, 35 insertions(+)
>  create mode 100644 arch/arm/mach-at91/sam9x7.c
> 
> diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
> index 794bd12ab0a8..7d8a7bc44e65 100644
> --- a/arch/arm/mach-at91/Makefile
> +++ b/arch/arm/mach-at91/Makefile
> @@ -7,6 +7,7 @@
>  obj-$(CONFIG_SOC_AT91RM9200)	+= at91rm9200.o
>  obj-$(CONFIG_SOC_AT91SAM9)	+= at91sam9.o
>  obj-$(CONFIG_SOC_SAM9X60)	+= sam9x60.o
> +obj-$(CONFIG_SOC_SAM9X7)	+= sam9x7.o
>  obj-$(CONFIG_SOC_SAMA5)		+= sama5.o sam_secure.o
>  obj-$(CONFIG_SOC_SAMA7)		+= sama7.o
>  obj-$(CONFIG_SOC_SAMV7)		+= samv7.o
> diff --git a/arch/arm/mach-at91/sam9x7.c b/arch/arm/mach-at91/sam9x7.c
> new file mode 100644
> index 000000000000..d998fb327860
> --- /dev/null
> +++ b/arch/arm/mach-at91/sam9x7.c
> @@ -0,0 +1,34 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Setup code for SAM9X7.
> + *
> + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
> + */
> +
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +
> +#include <asm/mach/arch.h>
> +#include <asm/system_misc.h>

This one could be removed.

> +
> +#include "generic.h"
> +
> +static void __init sam9x7_init(void)
> +{
> +	of_platform_default_populate(NULL, NULL, NULL);
> +
> +	sam9x7_pm_init();
> +}
> +
> +static const char *const sam9x7_dt_board_compat[] __initconst = {

you can add a space after * for clarity, e.g.:

static const char * const sam9x7_dt_board_compat[] __initconst = {

> +	"microchip,sam9x7",
> +	NULL
> +};
> +
> +DT_MACHINE_START(sam9x7_dt, "Microchip SAM9X7")
> +	/* Maintainer: Microchip */
> +	.init_machine	= sam9x7_init,
> +	.dt_compat	= sam9x7_dt_board_compat,
> +MACHINE_END

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[PATCH v4 20/39] ARM: at91: add support in SoC driver for new sam9x7

[Varshini Rajendran]

Add support for SAM9X7 SoC in the SoC driver.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
Changes in v4:
- Sorted the entries alphabetically as per comment from Claudiu
- Updated EXID
Note: Did not remove the Reviewed-by tag since the changes were only
cosmetic and did not affect functionality
---
 drivers/soc/atmel/soc.c | 23 +++++++++++++++++++++++
 drivers/soc/atmel/soc.h |  9 +++++++++
 2 files changed, 32 insertions(+)

diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c
index cc9a3e107479..cae3452cbc60 100644
--- a/drivers/soc/atmel/soc.c
+++ b/drivers/soc/atmel/soc.c
@@ -101,6 +101,29 @@ static const struct at91_soc socs[] __initconst = {
 		 AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH,
 		 "sam9x60 8MiB SDRAM SiP", "sam9x60"),
 #endif
+#ifdef CONFIG_SOC_SAM9X7
+	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+		 "sam9x75", "sam9x7"),
+	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+		 AT91_CIDR_VERSION_MASK, SAM9X72_EXID_MATCH,
+		 "sam9x72", "sam9x7"),
+	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+		 AT91_CIDR_VERSION_MASK, SAM9X70_EXID_MATCH,
+		 "sam9x70", "sam9x7"),
+	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1G_EXID_MATCH,
+		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+		 "sam9x75 1Gb DDR3L SiP ", "sam9x7"),
+	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D5M_EXID_MATCH,
+		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+		 "sam9x75 512Mb DDR2 SiP", "sam9x7"),
+	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1M_EXID_MATCH,
+		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+		 "sam9x75 128Mb DDR2 SiP", "sam9x7"),
+	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D2G_EXID_MATCH,
+		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+		 "sam9x75 2Gb DDR3L SiP", "sam9x7"),
+#endif
 #ifdef CONFIG_SOC_SAMA5
 	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 		 AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH,
diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h
index 7a9f47ce85fb..fc4157c5f6e3 100644
--- a/drivers/soc/atmel/soc.h
+++ b/drivers/soc/atmel/soc.h
@@ -44,6 +44,7 @@ at91_soc_init(const struct at91_soc *socs);
 #define AT91SAM9X5_CIDR_MATCH		0x019a05a0
 #define AT91SAM9N12_CIDR_MATCH		0x019a07a0
 #define SAM9X60_CIDR_MATCH		0x019b35a0
+#define SAM9X7_CIDR_MATCH		0x09750020
 #define SAMA7G5_CIDR_MATCH		0x00162100
 
 #define AT91SAM9M11_EXID_MATCH		0x00000001
@@ -74,6 +75,14 @@ at91_soc_init(const struct at91_soc *socs);
 #define SAMA7G54_D2G_EXID_MATCH		0x00000020
 #define SAMA7G54_D4G_EXID_MATCH		0x00000028
 
+#define SAM9X70_EXID_MATCH		0x00000005
+#define SAM9X72_EXID_MATCH		0x00000004
+#define SAM9X75_D1G_EXID_MATCH		0x00000018
+#define SAM9X75_D2G_EXID_MATCH		0x00000020
+#define SAM9X75_D1M_EXID_MATCH		0x00000003
+#define SAM9X75_D5M_EXID_MATCH		0x00000010
+#define SAM9X75_EXID_MATCH		0x00000000
+
 #define AT91SAM9XE128_CIDR_MATCH	0x329973a0
 #define AT91SAM9XE256_CIDR_MATCH	0x329a93a0
 #define AT91SAM9XE512_CIDR_MATCH	0x329aa3a0
-- 
2.25.1


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Re: [PATCH v4 20/39] ARM: at91: add support in SoC driver for new sam9x7

[Nicolas Ferre]

On 23/02/2024 at 18:27, Varshini Rajendran - I67070 wrote:
> Add support for SAM9X7 SoC in the SoC driver.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
> Changes in v4:
> - Sorted the entries alphabetically as per comment from Claudiu
> - Updated EXID
> Note: Did not remove the Reviewed-by tag since the changes were only
> cosmetic and did not affect functionality
> ---
>   drivers/soc/atmel/soc.c | 23 +++++++++++++++++++++++
>   drivers/soc/atmel/soc.h |  9 +++++++++
>   2 files changed, 32 insertions(+)
> 
> diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c
> index cc9a3e107479..cae3452cbc60 100644
> --- a/drivers/soc/atmel/soc.c
> +++ b/drivers/soc/atmel/soc.c
> @@ -101,6 +101,29 @@ static const struct at91_soc socs[] __initconst = {
>   		 AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH,
>   		 "sam9x60 8MiB SDRAM SiP", "sam9x60"),
>   #endif
> +#ifdef CONFIG_SOC_SAM9X7
> +	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
> +		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
> +		 "sam9x75", "sam9x7"),
> +	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
> +		 AT91_CIDR_VERSION_MASK, SAM9X72_EXID_MATCH,
> +		 "sam9x72", "sam9x7"),
> +	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
> +		 AT91_CIDR_VERSION_MASK, SAM9X70_EXID_MATCH,
> +		 "sam9x70", "sam9x7"),
> +	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1G_EXID_MATCH,
> +		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
> +		 "sam9x75 1Gb DDR3L SiP ", "sam9x7"),
> +	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D5M_EXID_MATCH,
> +		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
> +		 "sam9x75 512Mb DDR2 SiP", "sam9x7"),
> +	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1M_EXID_MATCH,
> +		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
> +		 "sam9x75 128Mb DDR2 SiP", "sam9x7"),
> +	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D2G_EXID_MATCH,
> +		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
> +		 "sam9x75 2Gb DDR3L SiP", "sam9x7"),

(as highlighted in previous review of this patch):
https://lore.kernel.org/linux-arm-kernel/20230728102905.267131-1-varshini.rajendran@microchip.com/T/#m2dac0ce9e1991c3d714785062a76ccdce11a02a6

I want RAM size in Bytes.

Sorry but NACK.

Best regards,
   Nicolas

> +#endif
>   #ifdef CONFIG_SOC_SAMA5
>   	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
>   		 AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH,
> diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h
> index 7a9f47ce85fb..fc4157c5f6e3 100644
> --- a/drivers/soc/atmel/soc.h
> +++ b/drivers/soc/atmel/soc.h
> @@ -44,6 +44,7 @@ at91_soc_init(const struct at91_soc *socs);
>   #define AT91SAM9X5_CIDR_MATCH		0x019a05a0
>   #define AT91SAM9N12_CIDR_MATCH		0x019a07a0
>   #define SAM9X60_CIDR_MATCH		0x019b35a0
> +#define SAM9X7_CIDR_MATCH		0x09750020
>   #define SAMA7G5_CIDR_MATCH		0x00162100
>   
>   #define AT91SAM9M11_EXID_MATCH		0x00000001
> @@ -74,6 +75,14 @@ at91_soc_init(const struct at91_soc *socs);
>   #define SAMA7G54_D2G_EXID_MATCH		0x00000020
>   #define SAMA7G54_D4G_EXID_MATCH		0x00000028
>   
> +#define SAM9X70_EXID_MATCH		0x00000005
> +#define SAM9X72_EXID_MATCH		0x00000004
> +#define SAM9X75_D1G_EXID_MATCH		0x00000018
> +#define SAM9X75_D2G_EXID_MATCH		0x00000020
> +#define SAM9X75_D1M_EXID_MATCH		0x00000003
> +#define SAM9X75_D5M_EXID_MATCH		0x00000010
> +#define SAM9X75_EXID_MATCH		0x00000000
> +
>   #define AT91SAM9XE128_CIDR_MATCH	0x329973a0
>   #define AT91SAM9XE256_CIDR_MATCH	0x329a93a0
>   #define AT91SAM9XE512_CIDR_MATCH	0x329aa3a0


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Re: [PATCH v4 20/39] ARM: at91: add support in SoC driver for new sam9x7

[claudiu beznea]

On 23.02.2024 19:27, Varshini Rajendran wrote:
> Add support for SAM9X7 SoC in the SoC driver.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
> Changes in v4:
> - Sorted the entries alphabetically as per comment from Claudiu
> - Updated EXID
> Note: Did not remove the Reviewed-by tag since the changes were only
> cosmetic and did not affect functionality
> ---
>  drivers/soc/atmel/soc.c | 23 +++++++++++++++++++++++
>  drivers/soc/atmel/soc.h |  9 +++++++++
>  2 files changed, 32 insertions(+)
> 
> diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c
> index cc9a3e107479..cae3452cbc60 100644
> --- a/drivers/soc/atmel/soc.c
> +++ b/drivers/soc/atmel/soc.c
> @@ -101,6 +101,29 @@ static const struct at91_soc socs[] __initconst = {
>  		 AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH,
>  		 "sam9x60 8MiB SDRAM SiP", "sam9x60"),
>  #endif
> +#ifdef CONFIG_SOC_SAM9X7
> +	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
> +		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
> +		 "sam9x75", "sam9x7"),
> +	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
> +		 AT91_CIDR_VERSION_MASK, SAM9X72_EXID_MATCH,
> +		 "sam9x72", "sam9x7"),
> +	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
> +		 AT91_CIDR_VERSION_MASK, SAM9X70_EXID_MATCH,
> +		 "sam9x70", "sam9x7"),
> +	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1G_EXID_MATCH,
> +		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
> +		 "sam9x75 1Gb DDR3L SiP ", "sam9x7"),
> +	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D5M_EXID_MATCH,
> +		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
> +		 "sam9x75 512Mb DDR2 SiP", "sam9x7"),
> +	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1M_EXID_MATCH,
> +		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
> +		 "sam9x75 128Mb DDR2 SiP", "sam9x7"),
> +	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D2G_EXID_MATCH,
> +		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
> +		 "sam9x75 2Gb DDR3L SiP", "sam9x7"),

Could you keep these sorted after SoC name and memory size? E.g. see
sama7g5 entries, sama5dX entries.

> +#endif
>  #ifdef CONFIG_SOC_SAMA5
>  	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
>  		 AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH,
> diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h
> index 7a9f47ce85fb..fc4157c5f6e3 100644
> --- a/drivers/soc/atmel/soc.h
> +++ b/drivers/soc/atmel/soc.h
> @@ -44,6 +44,7 @@ at91_soc_init(const struct at91_soc *socs);
>  #define AT91SAM9X5_CIDR_MATCH		0x019a05a0
>  #define AT91SAM9N12_CIDR_MATCH		0x019a07a0
>  #define SAM9X60_CIDR_MATCH		0x019b35a0
> +#define SAM9X7_CIDR_MATCH		0x09750020
>  #define SAMA7G5_CIDR_MATCH		0x00162100
>  
>  #define AT91SAM9M11_EXID_MATCH		0x00000001
> @@ -74,6 +75,14 @@ at91_soc_init(const struct at91_soc *socs);
>  #define SAMA7G54_D2G_EXID_MATCH		0x00000020
>  #define SAMA7G54_D4G_EXID_MATCH		0x00000028
>  
> +#define SAM9X70_EXID_MATCH		0x00000005
> +#define SAM9X72_EXID_MATCH		0x00000004
> +#define SAM9X75_D1G_EXID_MATCH		0x00000018
> +#define SAM9X75_D2G_EXID_MATCH		0x00000020
> +#define SAM9X75_D1M_EXID_MATCH		0x00000003
> +#define SAM9X75_D5M_EXID_MATCH		0x00000010
> +#define SAM9X75_EXID_MATCH		0x00000000

Could you keep this chunk after SAM9X60_* one to have some kind of
alphanumerical sort?

> +
>  #define AT91SAM9XE128_CIDR_MATCH	0x329973a0
>  #define AT91SAM9XE256_CIDR_MATCH	0x329a93a0
>  #define AT91SAM9XE512_CIDR_MATCH	0x329aa3a0

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[PATCH v4 21/39] dt-bindings: clk: at91: add sam9x7

[Varshini Rajendran]

Add bindings for SAM9X7's slow clock controller.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v4:
- Added sam9x7 compatible as an enum with sama7g5 compatible as per the
  review comment
---
 .../devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml      | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
index 7be29877e6d2..ab81f0b55ad5 100644
--- a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
+++ b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
@@ -18,7 +18,9 @@ properties:
           - atmel,sama5d4-sckc
           - microchip,sam9x60-sckc
       - items:
-          - const: microchip,sama7g5-sckc
+          - enum:
+              - microchip,sama7g5-sckc
+              - microchip,sam9x7-sckc
           - const: microchip,sam9x60-sckc
 
   reg:
-- 
2.25.1


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Re: [PATCH v4 21/39] dt-bindings: clk: at91: add sam9x7

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1239 bytes --]

On Fri, Feb 23, 2024 at 10:57:32PM +0530, Varshini Rajendran wrote:
> Add bindings for SAM9X7's slow clock controller.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

> ---
> Changes in v4:
> - Added sam9x7 compatible as an enum with sama7g5 compatible as per the
>   review comment
> ---
>  .../devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml      | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
> index 7be29877e6d2..ab81f0b55ad5 100644
> --- a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
> +++ b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
> @@ -18,7 +18,9 @@ properties:
>            - atmel,sama5d4-sckc
>            - microchip,sam9x60-sckc
>        - items:
> -          - const: microchip,sama7g5-sckc
> +          - enum:
> +              - microchip,sama7g5-sckc
> +              - microchip,sam9x7-sckc
>            - const: microchip,sam9x60-sckc
>  
>    reg:
> -- 
> 2.25.1
> 

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Re: [PATCH v4 21/39] dt-bindings: clk: at91: add sam9x7

[claudiu beznea]

s/dt-bindings: clk: at91/dt-bindings: clocks: at91sam9x5-sckc

or

s/dt-bindings: clk: at91/dt-bindings: clocks:  atmel,at91sam9x5-sckc

in patch title

On 23.02.2024 19:27, Varshini Rajendran wrote:
> Add bindings for SAM9X7's slow clock controller.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
> Changes in v4:
> - Added sam9x7 compatible as an enum with sama7g5 compatible as per the
>   review comment
> ---
>  .../devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml      | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
> index 7be29877e6d2..ab81f0b55ad5 100644
> --- a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
> +++ b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
> @@ -18,7 +18,9 @@ properties:
>            - atmel,sama5d4-sckc
>            - microchip,sam9x60-sckc
>        - items:
> -          - const: microchip,sama7g5-sckc
> +          - enum:
> +              - microchip,sama7g5-sckc
> +              - microchip,sam9x7-sckc

Alphanumerically sorted?

>            - const: microchip,sam9x60-sckc
>  
>    reg:

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[PATCH v4 22/39] dt-bindings: clk: at91: add sam9x7 clock controller

[Varshini Rajendran]

Add bindings for SAM9X7's pmc.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v4:
- Added the sam9x7 compatible in the allOf section
---
 .../devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml         | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
index c1bdcd9058ed..eb5cd33ea9aa 100644
--- a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
+++ b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
@@ -43,6 +43,7 @@ properties:
               - atmel,sama5d4-pmc
               - microchip,sam9x60-pmc
               - microchip,sama7g5-pmc
+              - microchip,sam9x7-pmc
           - const: syscon
 
   reg:
@@ -89,6 +90,7 @@ allOf:
             enum:
               - microchip,sam9x60-pmc
               - microchip,sama7g5-pmc
+              - microchip,sam9x7-pmc
     then:
       properties:
         clocks:
-- 
2.25.1


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Re: [PATCH v4 22/39] dt-bindings: clk: at91: add sam9x7 clock controller

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 253 bytes --]

On Fri, Feb 23, 2024 at 10:57:41PM +0530, Varshini Rajendran wrote:
> Add bindings for SAM9X7's pmc.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

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Re: [PATCH v4 22/39] dt-bindings: clk: at91: add sam9x7 clock controller

[claudiu beznea]

s/dt-bindings: clocks: at91/dt-bindings: clocks: atmel,at91rm9200-pmc

in patch title.

On 23.02.2024 19:27, Varshini Rajendran wrote:
> Add bindings for SAM9X7's pmc.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
> Changes in v4:
> - Added the sam9x7 compatible in the allOf section
> ---
>  .../devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml         | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
> index c1bdcd9058ed..eb5cd33ea9aa 100644
> --- a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
> +++ b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
> @@ -43,6 +43,7 @@ properties:
>                - atmel,sama5d4-pmc
>                - microchip,sam9x60-pmc
>                - microchip,sama7g5-pmc
> +              - microchip,sam9x7-pmc

These used to be alphanumerically sorted

>            - const: syscon
>  
>    reg:
> @@ -89,6 +90,7 @@ allOf:
>              enum:
>                - microchip,sam9x60-pmc
>                - microchip,sama7g5-pmc
> +              - microchip,sam9x7-pmc

Same here.

>      then:
>        properties:
>          clocks:

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[PATCH v4 23/39] clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs

[Varshini Rajendran]

SAM9X7 SoC family supports different core output frequencies for
different PLL IDs. To handle the same in the PLL driver, a separate
parameter core_output is added. The sam9x60 and sama7g5 SoC PMC drivers
are aligned to the PLL driver by adding the core output freq range in
the PLL characteristics configurations.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/clk/at91/clk-sam9x60-pll.c | 12 ++++++------
 drivers/clk/at91/pmc.h             |  1 +
 drivers/clk/at91/sam9x60.c         |  7 +++++++
 drivers/clk/at91/sama7g5.c         |  7 +++++++
 4 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
index ff65f7b916f0..b0314dfd7393 100644
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -23,9 +23,6 @@
 #define UPLL_DIV		2
 #define PLL_MUL_MAX		(FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
 
-#define FCORE_MIN		(600000000)
-#define FCORE_MAX		(1200000000)
-
 #define PLL_MAX_ID		7
 
 struct sam9x60_pll_core {
@@ -194,7 +191,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,
 	unsigned long nmul = 0;
 	unsigned long nfrac = 0;
 
-	if (rate < FCORE_MIN || rate > FCORE_MAX)
+	if (rate < core->characteristics->core_output[0].min ||
+	    rate > core->characteristics->core_output[0].max)
 		return -ERANGE;
 
 	/*
@@ -214,7 +212,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,
 	}
 
 	/* Check if resulted rate is a valid.  */
-	if (tmprate < FCORE_MIN || tmprate > FCORE_MAX)
+	if (tmprate < core->characteristics->core_output[0].min ||
+	    tmprate > core->characteristics->core_output[0].max)
 		return -ERANGE;
 
 	if (update) {
@@ -669,7 +668,8 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
 			goto free;
 		}
 
-		ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN,
+		ret = sam9x60_frac_pll_compute_mul_frac(&frac->core,
+							characteristics->core_output[0].min,
 							parent_rate, true);
 		if (ret < 0) {
 			hw = ERR_PTR(ret);
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 0f52e80bcd49..bb9da35198d9 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -75,6 +75,7 @@ struct clk_pll_characteristics {
 	struct clk_range input;
 	int num_output;
 	const struct clk_range *output;
+	const struct clk_range *core_output;
 	u16 *icpll;
 	u8 *out;
 	u8 upll : 1;
diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
index e309cbf3cb9a..db6db9e2073e 100644
--- a/drivers/clk/at91/sam9x60.c
+++ b/drivers/clk/at91/sam9x60.c
@@ -26,10 +26,16 @@ static const struct clk_range plla_outputs[] = {
 	{ .min = 2343750, .max = 1200000000 },
 };
 
+/* Fractional PLL core output range. */
+static const struct clk_range core_outputs[] = {
+	{ .min = 600000000, .max = 1200000000 },
+};
+
 static const struct clk_pll_characteristics plla_characteristics = {
 	.input = { .min = 12000000, .max = 48000000 },
 	.num_output = ARRAY_SIZE(plla_outputs),
 	.output = plla_outputs,
+	.core_output = core_outputs,
 };
 
 static const struct clk_range upll_outputs[] = {
@@ -40,6 +46,7 @@ static const struct clk_pll_characteristics upll_characteristics = {
 	.input = { .min = 12000000, .max = 48000000 },
 	.num_output = ARRAY_SIZE(upll_outputs),
 	.output = upll_outputs,
+	.core_output = core_outputs,
 	.upll = true,
 };
 
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index 91b5c6f14819..e6eb5afba93d 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -116,11 +116,17 @@ static const struct clk_range pll_outputs[] = {
 	{ .min = 2343750, .max = 1200000000 },
 };
 
+/* Fractional PLL core output range. */
+static const struct clk_range core_outputs[] = {
+	{ .min = 600000000, .max = 1200000000 },
+};
+
 /* CPU PLL characteristics. */
 static const struct clk_pll_characteristics cpu_pll_characteristics = {
 	.input = { .min = 12000000, .max = 50000000 },
 	.num_output = ARRAY_SIZE(cpu_pll_outputs),
 	.output = cpu_pll_outputs,
+	.core_output = core_outputs,
 };
 
 /* PLL characteristics. */
@@ -128,6 +134,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
 	.input = { .min = 12000000, .max = 50000000 },
 	.num_output = ARRAY_SIZE(pll_outputs),
 	.output = pll_outputs,
+	.core_output = core_outputs,
 };
 
 /*
-- 
2.25.1


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[PATCH v4 24/39] clk: at91: sam9x7: add support for HW PLL freq dividers

[Varshini Rajendran]

Add support for hardware dividers for PLL IDs in sam9x7 SoC. The system
PLL - PLLA and the system PLL divided by 2 - PLLADIV2 with PLL ID 0 and
4 respectively, both have a hardware divider /2. This has to taken into
account in the software to obtain the right frequencies. Support for the
same is added in the PLL driver.

fcorepllack -----> HW Div = 2 -+--> fpllack
                               |
                               +--> HW Div = 2 ---> fplladiv2ck

In this case the corepll freq is 1600 MHz. So, the plla freq is 800 MHz
after the hardware divider and the plladiv2 freq is 400 MHz after the
hardware divider (Given that the DIVPMC is 0).

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/clk/at91/clk-sam9x60-pll.c | 38 ++++++++++++++++++++++++++----
 drivers/clk/at91/pmc.h             |  1 +
 2 files changed, 34 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
index b0314dfd7393..1f80759309c0 100644
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -73,9 +73,15 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
 {
 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 	struct sam9x60_frac *frac = to_sam9x60_frac(core);
+	unsigned long freq;
 
-	return parent_rate * (frac->mul + 1) +
+	freq = parent_rate * (frac->mul + 1) +
 		DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
+
+	if (core->layout->div2)
+		freq >>= 1;
+
+	return freq;
 }
 
 static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
@@ -432,6 +438,12 @@ static unsigned long sam9x60_div_pll_recalc_rate(struct clk_hw *hw,
 	return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1));
 }
 
+static unsigned long sam9x60_fixed_div_pll_recalc_rate(struct clk_hw *hw,
+						       unsigned long parent_rate)
+{
+	return parent_rate >> 1;
+}
+
 static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core,
 					unsigned long *parent_rate,
 					unsigned long rate)
@@ -606,6 +618,16 @@ static const struct clk_ops sam9x60_div_pll_ops_chg = {
 	.restore_context = sam9x60_div_pll_restore_context,
 };
 
+static const struct clk_ops sam9x60_fixed_div_pll_ops = {
+	.prepare = sam9x60_div_pll_prepare,
+	.unprepare = sam9x60_div_pll_unprepare,
+	.is_prepared = sam9x60_div_pll_is_prepared,
+	.recalc_rate = sam9x60_fixed_div_pll_recalc_rate,
+	.round_rate = sam9x60_div_pll_round_rate,
+	.save_context = sam9x60_div_pll_save_context,
+	.restore_context = sam9x60_div_pll_restore_context,
+};
+
 struct clk_hw * __init
 sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
 			      const char *name, const char *parent_name,
@@ -725,10 +747,16 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
 	else
 		init.parent_names = &parent_name;
 	init.num_parents = 1;
-	if (flags & CLK_SET_RATE_GATE)
-		init.ops = &sam9x60_div_pll_ops;
-	else
-		init.ops = &sam9x60_div_pll_ops_chg;
+
+	if (layout->div2) {
+		init.ops = &sam9x60_fixed_div_pll_ops;
+	} else {
+		if (flags & CLK_SET_RATE_GATE)
+			init.ops = &sam9x60_div_pll_ops;
+		else
+			init.ops = &sam9x60_div_pll_ops_chg;
+	}
+
 	init.flags = flags;
 
 	div->core.id = id;
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index bb9da35198d9..91d1c6305d95 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -64,6 +64,7 @@ struct clk_pll_layout {
 	u8 frac_shift;
 	u8 div_shift;
 	u8 endiv_shift;
+	u8 div2;
 };
 
 extern const struct clk_pll_layout at91rm9200_pll_layout;
-- 
2.25.1


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Re: [PATCH v4 24/39] clk: at91: sam9x7: add support for HW PLL freq dividers

[claudiu beznea]

On 23.02.2024 19:27, Varshini Rajendran wrote:
> Add support for hardware dividers for PLL IDs in sam9x7 SoC. The system
> PLL - PLLA and the system PLL divided by 2 - PLLADIV2 with PLL ID 0 and
> 4 respectively, both have a hardware divider /2. This has to taken into

to be taken

> account in the software to obtain the right frequencies. Support for the
> same is added in the PLL driver.
> 
> fcorepllack -----> HW Div = 2 -+--> fpllack
>                                |
>                                +--> HW Div = 2 ---> fplladiv2ck
> 
> In this case the corepll freq is 1600 MHz. So, the plla freq is 800 MHz
> after the hardware divider and the plladiv2 freq is 400 MHz after the
> hardware divider (Given that the DIVPMC is 0).

s/Given/given

> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  drivers/clk/at91/clk-sam9x60-pll.c | 38 ++++++++++++++++++++++++++----
>  drivers/clk/at91/pmc.h             |  1 +
>  2 files changed, 34 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
> index b0314dfd7393..1f80759309c0 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -73,9 +73,15 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
>  {
>  	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
>  	struct sam9x60_frac *frac = to_sam9x60_frac(core);
> +	unsigned long freq;
>  
> -	return parent_rate * (frac->mul + 1) +
> +	freq = parent_rate * (frac->mul + 1) +
>  		DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
> +
> +	if (core->layout->div2)
> +		freq >>= 1;
> +
> +	return freq;
>  }
>  
>  static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
> @@ -432,6 +438,12 @@ static unsigned long sam9x60_div_pll_recalc_rate(struct clk_hw *hw,
>  	return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1));
>  }
>  
> +static unsigned long sam9x60_fixed_div_pll_recalc_rate(struct clk_hw *hw,
> +						       unsigned long parent_rate)
> +{
> +	return parent_rate >> 1;
> +}
> +
>  static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core,
>  					unsigned long *parent_rate,
>  					unsigned long rate)
> @@ -606,6 +618,16 @@ static const struct clk_ops sam9x60_div_pll_ops_chg = {
>  	.restore_context = sam9x60_div_pll_restore_context,
>  };
>  
> +static const struct clk_ops sam9x60_fixed_div_pll_ops = {
> +	.prepare = sam9x60_div_pll_prepare,
> +	.unprepare = sam9x60_div_pll_unprepare,
> +	.is_prepared = sam9x60_div_pll_is_prepared,
> +	.recalc_rate = sam9x60_fixed_div_pll_recalc_rate,
> +	.round_rate = sam9x60_div_pll_round_rate,
> +	.save_context = sam9x60_div_pll_save_context,
> +	.restore_context = sam9x60_div_pll_restore_context,
> +};
> +
>  struct clk_hw * __init
>  sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
>  			      const char *name, const char *parent_name,
> @@ -725,10 +747,16 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
>  	else
>  		init.parent_names = &parent_name;
>  	init.num_parents = 1;
> -	if (flags & CLK_SET_RATE_GATE)
> -		init.ops = &sam9x60_div_pll_ops;
> -	else
> -		init.ops = &sam9x60_div_pll_ops_chg;
> +
> +	if (layout->div2) {
> +		init.ops = &sam9x60_fixed_div_pll_ops;
> +	} else {
> +		if (flags & CLK_SET_RATE_GATE)
> +			init.ops = &sam9x60_div_pll_ops;
> +		else
> +			init.ops = &sam9x60_div_pll_ops_chg;
> +	}
> +

can't it be something like:

	if (layout->div2)
		// ...
	else if (flags & CLK_SET_RATE_GATE)
		// ...
	else
		//

?
>  	init.flags = flags;
>  
>  	div->core.id = id;
> diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
> index bb9da35198d9..91d1c6305d95 100644
> --- a/drivers/clk/at91/pmc.h
> +++ b/drivers/clk/at91/pmc.h
> @@ -64,6 +64,7 @@ struct clk_pll_layout {
>  	u8 frac_shift;
>  	u8 div_shift;
>  	u8 endiv_shift;
> +	u8 div2;
>  };
>  
>  extern const struct clk_pll_layout at91rm9200_pll_layout;

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[PATCH v4 25/39] clk: at91: sama7g5: move mux table macros to header file

[Varshini Rajendran]

Move the mux table init and fill macro function definitions from the
sama7g5 pmc driver to the pmc.h header file since they will be used
by other SoC's pmc drivers as well like sam9x7.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/clk/at91/pmc.h     | 16 ++++++++++++++++
 drivers/clk/at91/sama7g5.c | 35 ++++++++++-------------------------
 2 files changed, 26 insertions(+), 25 deletions(-)

diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 91d1c6305d95..4fb29ca111f7 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -121,6 +121,22 @@ struct at91_clk_pms {
 
 #define ndck(a, s) (a[s - 1].id + 1)
 #define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1)
+
+#define PMC_INIT_TABLE(_table, _count)			\
+	do {						\
+		u8 _i;					\
+		for (_i = 0; _i < (_count); _i++)	\
+			(_table)[_i] = _i;		\
+	} while (0)
+
+#define PMC_FILL_TABLE(_to, _from, _count)		\
+	do {						\
+		u8 _i;					\
+		for (_i = 0; _i < (_count); _i++) {	\
+			(_to)[_i] = (_from)[_i];	\
+		}					\
+	} while (0)
+
 struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
 				   unsigned int nperiph, unsigned int ngck,
 				   unsigned int npck);
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index e6eb5afba93d..6706d1305baa 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -16,21 +16,6 @@
 
 #include "pmc.h"
 
-#define SAMA7G5_INIT_TABLE(_table, _count)		\
-	do {						\
-		u8 _i;					\
-		for (_i = 0; _i < (_count); _i++)	\
-			(_table)[_i] = _i;		\
-	} while (0)
-
-#define SAMA7G5_FILL_TABLE(_to, _from, _count)		\
-	do {						\
-		u8 _i;					\
-		for (_i = 0; _i < (_count); _i++) {	\
-			(_to)[_i] = (_from)[_i];	\
-		}					\
-	} while (0)
-
 static DEFINE_SPINLOCK(pmc_pll_lock);
 static DEFINE_SPINLOCK(pmc_mck0_lock);
 static DEFINE_SPINLOCK(pmc_mckX_lock);
@@ -1119,17 +1104,17 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
 		if (!mux_table)
 			goto err_free;
 
-		SAMA7G5_INIT_TABLE(mux_table, 3);
-		SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table,
-				   sama7g5_mckx[i].ep_count);
+		PMC_INIT_TABLE(mux_table, 3);
+		PMC_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table,
+			       sama7g5_mckx[i].ep_count);
 		for (j = 0; j < sama7g5_mckx[i].ep_count; j++) {
 			u8 pll_id = sama7g5_mckx[i].ep[j].pll_id;
 			u8 pll_compid = sama7g5_mckx[i].ep[j].pll_compid;
 
 			tmp_parent_hws[j] = sama7g5_plls[pll_id][pll_compid].hw;
 		}
-		SAMA7G5_FILL_TABLE(&parent_hws[3], tmp_parent_hws,
-				   sama7g5_mckx[i].ep_count);
+		PMC_FILL_TABLE(&parent_hws[3], tmp_parent_hws,
+			       sama7g5_mckx[i].ep_count);
 
 		hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n,
 				   num_parents, NULL, parent_hws, mux_table,
@@ -1215,17 +1200,17 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
 		if (!mux_table)
 			goto err_free;
 
-		SAMA7G5_INIT_TABLE(mux_table, 3);
-		SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table,
-				   sama7g5_gck[i].pp_count);
+		PMC_INIT_TABLE(mux_table, 3);
+		PMC_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table,
+			       sama7g5_gck[i].pp_count);
 		for (j = 0; j < sama7g5_gck[i].pp_count; j++) {
 			u8 pll_id = sama7g5_gck[i].pp[j].pll_id;
 			u8 pll_compid = sama7g5_gck[i].pp[j].pll_compid;
 
 			tmp_parent_hws[j] = sama7g5_plls[pll_id][pll_compid].hw;
 		}
-		SAMA7G5_FILL_TABLE(&parent_hws[3], tmp_parent_hws,
-				   sama7g5_gck[i].pp_count);
+		PMC_FILL_TABLE(&parent_hws[3], tmp_parent_hws,
+			       sama7g5_gck[i].pp_count);
 
 		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
 						 &sama7g5_pcr_layout,
-- 
2.25.1


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[PATCH v4 26/39] dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT

[Varshini Rajendran]

Allow PLLADIV2 and LVDSPLL to be referenced as a PMC_TYPE_CORE
clock from phandle in DT for sam9x7 SoC family.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 include/dt-bindings/clock/at91.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
index 3e3972a814c1..6ede88c3992d 100644
--- a/include/dt-bindings/clock/at91.h
+++ b/include/dt-bindings/clock/at91.h
@@ -38,6 +38,10 @@
 #define PMC_CPU			(PMC_MAIN + 9)
 #define PMC_MCK1		(PMC_MAIN + 10)
 
+/* SAM9X7 */
+#define PMC_PLLADIV2		(PMC_MAIN + 11)
+#define PMC_LVDSPLL		(PMC_MAIN + 12)
+
 #ifndef AT91_PMC_MOSCS
 #define AT91_PMC_MOSCS		0		/* MOSCS Flag */
 #define AT91_PMC_LOCKA		1		/* PLLA Lock */
-- 
2.25.1


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Re: [PATCH v4 26/39] dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT

[Rob Herring]

On Fri, 23 Feb 2024 22:58:22 +0530, Varshini Rajendran wrote:
> Allow PLLADIV2 and LVDSPLL to be referenced as a PMC_TYPE_CORE
> clock from phandle in DT for sam9x7 SoC family.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  include/dt-bindings/clock/at91.h | 4 ++++
>  1 file changed, 4 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>


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[PATCH v4 27/39] clk: at91: sam9x7: add sam9x7 pmc driver

[Varshini Rajendran]

Add a driver for the PMC clocks of sam9x7 Soc family.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v4:
- Changed variable name alloc_mem to clk_mux_buffer to be more
  suggestive
- Changed description of @f structure member appropriately
---
 drivers/clk/at91/Makefile |   1 +
 drivers/clk/at91/sam9x7.c | 946 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 947 insertions(+)
 create mode 100644 drivers/clk/at91/sam9x7.c

diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 89061b85e7d2..8e3684ba2c74 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o at91sam9rl.o at91sam9x5.o dt-compat.
 obj-$(CONFIG_SOC_AT91SAM9) += at91sam9g45.o dt-compat.o
 obj-$(CONFIG_SOC_AT91SAM9) += at91sam9n12.o at91sam9x5.o dt-compat.o
 obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o
+obj-$(CONFIG_SOC_SAM9X7) += sam9x7.o
 obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o dt-compat.o
 obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o dt-compat.o
 obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o dt-compat.o
diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
new file mode 100644
index 000000000000..d03387d2e35a
--- /dev/null
+++ b/drivers/clk/at91/sam9x7.c
@@ -0,0 +1,946 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SAM9X7 PMC code.
+ *
+ * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
+ *
+ */
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/at91.h>
+
+#include "pmc.h"
+
+static DEFINE_SPINLOCK(pmc_pll_lock);
+static DEFINE_SPINLOCK(mck_lock);
+
+/**
+ * enum pll_ids - PLL clocks identifiers
+ * @PLL_ID_PLLA:	PLLA identifier
+ * @PLL_ID_UPLL:	UPLL identifier
+ * @PLL_ID_AUDIO:	Audio PLL identifier
+ * @PLL_ID_LVDS:	LVDS PLL identifier
+ * @PLL_ID_PLLA_DIV2:	PLLA DIV2 identifier
+ * @PLL_ID_MAX:		Max PLL Identifier
+ */
+enum pll_ids {
+	PLL_ID_PLLA,
+	PLL_ID_UPLL,
+	PLL_ID_AUDIO,
+	PLL_ID_LVDS,
+	PLL_ID_PLLA_DIV2,
+	PLL_ID_MAX,
+};
+
+/**
+ * enum pll_type - PLL type identifiers
+ * @PLL_TYPE_FRAC:	fractional PLL identifier
+ * @PLL_TYPE_DIV:	divider PLL identifier
+ */
+enum pll_type {
+	PLL_TYPE_FRAC,
+	PLL_TYPE_DIV,
+};
+
+static const struct clk_master_characteristics mck_characteristics = {
+	.output = { .min = 32000000, .max = 266666667 },
+	.divisors = { 1, 2, 4, 3, 5},
+	.have_div3_pres = 1,
+};
+
+static const struct clk_master_layout sam9x7_master_layout = {
+	.mask = 0x373,
+	.pres_shift = 4,
+	.offset = 0x28,
+};
+
+/* Fractional PLL core output range. */
+static const struct clk_range plla_core_outputs[] = {
+	{ .min = 375000000, .max = 1600000000 },
+};
+
+static const struct clk_range upll_core_outputs[] = {
+	{ .min = 600000000, .max = 1200000000 },
+};
+
+static const struct clk_range lvdspll_core_outputs[] = {
+	{ .min = 400000000, .max = 800000000 },
+};
+
+static const struct clk_range audiopll_core_outputs[] = {
+	{ .min = 400000000, .max = 800000000 },
+};
+
+static const struct clk_range plladiv2_core_outputs[] = {
+	{ .min = 375000000, .max = 1600000000 },
+};
+
+/* Fractional PLL output range. */
+static const struct clk_range plla_outputs[] = {
+	{ .min = 732421, .max = 800000000 },
+};
+
+static const struct clk_range upll_outputs[] = {
+	{ .min = 300000000, .max = 600000000 },
+};
+
+static const struct clk_range lvdspll_outputs[] = {
+	{ .min = 10000000, .max = 800000000 },
+};
+
+static const struct clk_range audiopll_outputs[] = {
+	{ .min = 10000000, .max = 800000000 },
+};
+
+static const struct clk_range plladiv2_outputs[] = {
+	{ .min = 366210, .max = 400000000 },
+};
+
+/* PLL characteristics. */
+static const struct clk_pll_characteristics plla_characteristics = {
+	.input = { .min = 20000000, .max = 50000000 },
+	.num_output = ARRAY_SIZE(plla_outputs),
+	.output = plla_outputs,
+	.core_output = plla_core_outputs,
+};
+
+static const struct clk_pll_characteristics upll_characteristics = {
+	.input = { .min = 20000000, .max = 50000000 },
+	.num_output = ARRAY_SIZE(upll_outputs),
+	.output = upll_outputs,
+	.core_output = upll_core_outputs,
+	.upll = true,
+};
+
+static const struct clk_pll_characteristics lvdspll_characteristics = {
+	.input = { .min = 20000000, .max = 50000000 },
+	.num_output = ARRAY_SIZE(lvdspll_outputs),
+	.output = lvdspll_outputs,
+	.core_output = lvdspll_core_outputs,
+};
+
+static const struct clk_pll_characteristics audiopll_characteristics = {
+	.input = { .min = 20000000, .max = 50000000 },
+	.num_output = ARRAY_SIZE(audiopll_outputs),
+	.output = audiopll_outputs,
+	.core_output = audiopll_core_outputs,
+};
+
+static const struct clk_pll_characteristics plladiv2_characteristics = {
+	.input = { .min = 20000000, .max = 50000000 },
+	.num_output = ARRAY_SIZE(plladiv2_outputs),
+	.output = plladiv2_outputs,
+	.core_output = plladiv2_core_outputs,
+};
+
+/* Layout for fractional PLL ID PLLA. */
+static const struct clk_pll_layout plla_frac_layout = {
+	.mul_mask = GENMASK(31, 24),
+	.frac_mask = GENMASK(21, 0),
+	.mul_shift = 24,
+	.frac_shift = 0,
+	.div2 = 1,
+};
+
+/* Layout for fractional PLLs. */
+static const struct clk_pll_layout pll_frac_layout = {
+	.mul_mask = GENMASK(31, 24),
+	.frac_mask = GENMASK(21, 0),
+	.mul_shift = 24,
+	.frac_shift = 0,
+};
+
+/* Layout for DIV PLLs. */
+static const struct clk_pll_layout pll_divpmc_layout = {
+	.div_mask = GENMASK(7, 0),
+	.endiv_mask = BIT(29),
+	.div_shift = 0,
+	.endiv_shift = 29,
+};
+
+/* Layout for DIV PLL ID PLLADIV2. */
+static const struct clk_pll_layout plladiv2_divpmc_layout = {
+	.div_mask = GENMASK(7, 0),
+	.endiv_mask = BIT(29),
+	.div_shift = 0,
+	.endiv_shift = 29,
+	.div2 = 1,
+};
+
+/* Layout for DIVIO dividers. */
+static const struct clk_pll_layout pll_divio_layout = {
+	.div_mask	= GENMASK(19, 12),
+	.endiv_mask	= BIT(30),
+	.div_shift	= 12,
+	.endiv_shift	= 30,
+};
+
+/*
+ * PLL clocks description
+ * @n:		clock name
+ * @p:		clock parent
+ * @l:		clock layout
+ * @t:		clock type
+ * @c:		pll characteristics
+ * @f:		clock flags
+ * @eid:	export index in sam9x7->chws[] array
+ */
+static const struct {
+	const char *n;
+	const char *p;
+	const struct clk_pll_layout *l;
+	u8 t;
+	const struct clk_pll_characteristics *c;
+	unsigned long f;
+	u8 eid;
+} sam9x7_plls[][PLL_ID_MAX] = {
+	[PLL_ID_PLLA] = {
+		{
+			.n = "plla_fracck",
+			.p = "mainck",
+			.l = &plla_frac_layout,
+			.t = PLL_TYPE_FRAC,
+			/*
+			 * This feeds plla_divpmcck which feeds CPU. It should
+			 * not be disabled.
+			 */
+			.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
+			.c = &plla_characteristics,
+		},
+
+		{
+			.n = "plla_divpmcck",
+			.p = "plla_fracck",
+			.l = &pll_divpmc_layout,
+			.t = PLL_TYPE_DIV,
+			/* This feeds CPU. It should not be disabled */
+			.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
+			.eid = PMC_PLLACK,
+			.c = &plla_characteristics,
+		},
+	},
+
+	[PLL_ID_UPLL] = {
+		{
+			.n = "upll_fracck",
+			.p = "main_osc",
+			.l = &pll_frac_layout,
+			.t = PLL_TYPE_FRAC,
+			.f = CLK_SET_RATE_GATE,
+			.c = &upll_characteristics,
+		},
+
+		{
+			.n = "upll_divpmcck",
+			.p = "upll_fracck",
+			.l = &pll_divpmc_layout,
+			.t = PLL_TYPE_DIV,
+			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+			     CLK_SET_RATE_PARENT,
+			.eid = PMC_UTMI,
+			.c = &upll_characteristics,
+		},
+	},
+
+	[PLL_ID_AUDIO] = {
+		{
+			.n = "audiopll_fracck",
+			.p = "main_osc",
+			.l = &pll_frac_layout,
+			.f = CLK_SET_RATE_GATE,
+			.c = &audiopll_characteristics,
+			.t = PLL_TYPE_FRAC,
+		},
+
+		{
+			.n = "audiopll_divpmcck",
+			.p = "audiopll_fracck",
+			.l = &pll_divpmc_layout,
+			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+			     CLK_SET_RATE_PARENT,
+			.c = &audiopll_characteristics,
+			.eid = PMC_AUDIOPMCPLL,
+			.t = PLL_TYPE_DIV,
+		},
+
+		{
+			.n = "audiopll_diviock",
+			.p = "audiopll_fracck",
+			.l = &pll_divio_layout,
+			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+			     CLK_SET_RATE_PARENT,
+			.c = &audiopll_characteristics,
+			.eid = PMC_AUDIOIOPLL,
+			.t = PLL_TYPE_DIV,
+		},
+	},
+
+	[PLL_ID_LVDS] = {
+		{
+			.n = "lvdspll_fracck",
+			.p = "main_osc",
+			.l = &pll_frac_layout,
+			.f = CLK_SET_RATE_GATE,
+			.c = &lvdspll_characteristics,
+			.t = PLL_TYPE_FRAC,
+		},
+
+		{
+			.n = "lvdspll_divpmcck",
+			.p = "lvdspll_fracck",
+			.l = &pll_divpmc_layout,
+			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+			     CLK_SET_RATE_PARENT,
+			.c = &lvdspll_characteristics,
+			.eid = PMC_LVDSPLL,
+			.t = PLL_TYPE_DIV,
+		},
+	},
+
+	[PLL_ID_PLLA_DIV2] = {
+		{
+			.n = "plla_div2pmcck",
+			.p = "plla_fracck",
+			.l = &plladiv2_divpmc_layout,
+			/*
+			 * This may feed critical parts of the system like timers.
+			 * It should not be disabled.
+			 */
+			.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
+			.c = &plladiv2_characteristics,
+			.eid = PMC_PLLADIV2,
+			.t = PLL_TYPE_DIV,
+		},
+	},
+};
+
+static const struct clk_programmable_layout sam9x7_programmable_layout = {
+	.pres_mask = 0xff,
+	.pres_shift = 8,
+	.css_mask = 0x1f,
+	.have_slck_mck = 0,
+	.is_pres_direct = 1,
+};
+
+static const struct clk_pcr_layout sam9x7_pcr_layout = {
+	.offset = 0x88,
+	.cmd = BIT(31),
+	.gckcss_mask = GENMASK(12, 8),
+	.pid_mask = GENMASK(6, 0),
+};
+
+static const struct {
+	char *n;
+	char *p;
+	u8 id;
+	unsigned long flags;
+} sam9x7_systemck[] = {
+	/*
+	 * ddrck feeds DDR controller and is enabled by bootloader thus we need
+	 * to keep it enabled in case there is no Linux consumer for it.
+	 */
+	{ .n = "ddrck",		.p = "masterck_div",	.id = 2,	.flags = CLK_IS_CRITICAL },
+	{ .n = "uhpck",		.p = "usbck",		.id = 6 },
+	{ .n = "pck0",		.p = "prog0",		.id = 8 },
+	{ .n = "pck1",		.p = "prog1",		.id = 9 },
+};
+
+/*
+ * Peripheral clocks description
+ * @n:		clock name
+ * @f:		clock flags
+ * @id:		peripheral id
+ */
+static const struct {
+	char *n;
+	unsigned long f;
+	u8 id;
+} sam9x7_periphck[] = {
+	{ .n = "pioA_clk",	.id = 2, },
+	{ .n = "pioB_clk",	.id = 3, },
+	{ .n = "pioC_clk",	.id = 4, },
+	{ .n = "flex0_clk",	.id = 5, },
+	{ .n = "flex1_clk",	.id = 6, },
+	{ .n = "flex2_clk",	.id = 7, },
+	{ .n = "flex3_clk",	.id = 8, },
+	{ .n = "flex6_clk",	.id = 9, },
+	{ .n = "flex7_clk",	.id = 10, },
+	{ .n = "flex8_clk",	.id = 11, },
+	{ .n = "sdmmc0_clk",	.id = 12, },
+	{ .n = "flex4_clk",	.id = 13, },
+	{ .n = "flex5_clk",	.id = 14, },
+	{ .n = "flex9_clk",	.id = 15, },
+	{ .n = "flex10_clk",	.id = 16, },
+	{ .n = "tcb0_clk",	.id = 17, },
+	{ .n = "pwm_clk",	.id = 18, },
+	{ .n = "adc_clk",	.id = 19, },
+	{ .n = "dma0_clk",	.id = 20, },
+	{ .n = "uhphs_clk",	.id = 22, },
+	{ .n = "udphs_clk",	.id = 23, },
+	{ .n = "macb0_clk",	.id = 24, },
+	{ .n = "lcd_clk",	.id = 25, },
+	{ .n = "sdmmc1_clk",	.id = 26, },
+	{ .n = "ssc_clk",	.id = 28, },
+	{ .n = "can0_clk",	.id = 29, },
+	{ .n = "can1_clk",	.id = 30, },
+	{ .n = "flex11_clk",	.id = 32, },
+	{ .n = "flex12_clk",	.id = 33, },
+	{ .n = "i2s_clk",	.id = 34, },
+	{ .n = "qspi_clk",	.id = 35, },
+	{ .n = "gfx2d_clk",	.id = 36, },
+	{ .n = "pit64b0_clk",	.id = 37, },
+	{ .n = "trng_clk",	.id = 38, },
+	{ .n = "aes_clk",	.id = 39, },
+	{ .n = "tdes_clk",	.id = 40, },
+	{ .n = "sha_clk",	.id = 41, },
+	{ .n = "classd_clk",	.id = 42, },
+	{ .n = "isi_clk",	.id = 43, },
+	{ .n = "pioD_clk",	.id = 44, },
+	{ .n = "tcb1_clk",	.id = 45, },
+	{ .n = "dbgu_clk",	.id = 47, },
+	/*
+	 * mpddr_clk feeds DDR controller and is enabled by bootloader thus we
+	 * need to keep it enabled in case there is no Linux consumer for it.
+	 */
+	{ .n = "mpddr_clk",	.id = 49,	.f = CLK_IS_CRITICAL },
+	{ .n = "csi2dc_clk",	.id = 52, },
+	{ .n = "csi4l_clk",	.id = 53, },
+	{ .n = "dsi4l_clk",	.id = 54, },
+	{ .n = "lvdsc_clk",	.id = 56, },
+	{ .n = "pit64b1_clk",	.id = 58, },
+	{ .n = "puf_clk",	.id = 59, },
+	{ .n = "gmactsu_clk",	.id = 67, },
+};
+
+/*
+ * Generic clock description
+ * @n:			clock name
+ * @pp:			PLL parents
+ * @pp_mux_table:	PLL parents mux table
+ * @r:			clock output range
+ * @pp_chg_id:		id in parent array of changeable PLL parent
+ * @pp_count:		PLL parents count
+ * @id:			clock id
+ */
+static const struct {
+	const char *n;
+	const char *pp[8];
+	const char pp_mux_table[8];
+	struct clk_range r;
+	int pp_chg_id;
+	u8 pp_count;
+	u8 id;
+} sam9x7_gck[] = {
+	{
+		.n = "flex0_gclk",
+		.id = 5,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex1_gclk",
+		.id = 6,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex2_gclk",
+		.id = 7,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex3_gclk",
+		.id = 8,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex6_gclk",
+		.id = 9,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex7_gclk",
+		.id = 10,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex8_gclk",
+		.id = 11,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "sdmmc0_gclk",
+		.id = 12,
+		.r = { .max = 105000000 },
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex4_gclk",
+		.id = 13,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex5_gclk",
+		.id = 14,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex9_gclk",
+		.id = 15,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex10_gclk",
+		.id = 16,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "tcb0_gclk",
+		.id = 17,
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "adc_gclk",
+		.id = 19,
+		.pp = { "upll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 5, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "lcd_gclk",
+		.id = 25,
+		.r = { .max = 75000000 },
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "sdmmc1_gclk",
+		.id = 26,
+		.r = { .max = 105000000 },
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "mcan0_gclk",
+		.id = 29,
+		.r = { .max = 80000000 },
+		.pp = { "upll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 5, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "mcan1_gclk",
+		.id = 30,
+		.r = { .max = 80000000 },
+		.pp = { "upll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 5, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex11_gclk",
+		.id = 32,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex12_gclk",
+		.id = 33,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "i2s_gclk",
+		.id = 34,
+		.r = { .max = 100000000 },
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "qspi_gclk",
+		.id = 35,
+		.r = { .max = 20000000 },
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "pit64b0_gclk",
+		.id = 37,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "classd_gclk",
+		.id = 42,
+		.r = { .max = 100000000 },
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "tcb1_gclk",
+		.id = 45,
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "dbgu_gclk",
+		.id = 47,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "mipiphy_gclk",
+		.id = 55,
+		.r = { .max = 27000000 },
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "pit64b1_gclk",
+		.id = 58,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "gmac_gclk",
+		.id = 67,
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+};
+
+static void __init sam9x7_pmc_setup(struct device_node *np)
+{
+	struct clk_range range = CLK_RANGE(0, 0);
+	const char *td_slck_name, *md_slck_name, *mainxtal_name;
+	struct pmc_data *sam9x7_pmc;
+	const char *parent_names[9];
+	void **clk_mux_buffer = NULL;
+	int clk_mux_buffer_size = 0;
+	struct clk_hw *main_osc_hw;
+	struct regmap *regmap;
+	struct clk_hw *hw;
+	int i, j;
+
+	i = of_property_match_string(np, "clock-names", "td_slck");
+	if (i < 0)
+		return;
+
+	td_slck_name = of_clk_get_parent_name(np, i);
+
+	i = of_property_match_string(np, "clock-names", "md_slck");
+	if (i < 0)
+		return;
+
+	md_slck_name = of_clk_get_parent_name(np, i);
+
+	i = of_property_match_string(np, "clock-names", "main_xtal");
+	if (i < 0)
+		return;
+	mainxtal_name = of_clk_get_parent_name(np, i);
+
+	regmap = device_node_to_regmap(np);
+	if (IS_ERR(regmap))
+		return;
+
+	sam9x7_pmc = pmc_data_allocate(PMC_LVDSPLL + 1,
+				       nck(sam9x7_systemck),
+				       nck(sam9x7_periphck),
+				       nck(sam9x7_gck), 8);
+	if (!sam9x7_pmc)
+		return;
+
+	clk_mux_buffer = kmalloc(sizeof(void *) *
+				 (ARRAY_SIZE(sam9x7_gck)),
+				 GFP_KERNEL);
+	if (!clk_mux_buffer)
+		goto err_free;
+
+	hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
+					   50000000);
+	if (IS_ERR(hw))
+		goto err_free;
+
+	hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, 0);
+	if (IS_ERR(hw))
+		goto err_free;
+	main_osc_hw = hw;
+
+	parent_names[0] = "main_rc_osc";
+	parent_names[1] = "main_osc";
+	hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
+	if (IS_ERR(hw))
+		goto err_free;
+
+	sam9x7_pmc->chws[PMC_MAIN] = hw;
+
+	for (i = 0; i < PLL_ID_MAX; i++) {
+		for (j = 0; j < 3; j++) {
+			struct clk_hw *parent_hw;
+
+			if (!sam9x7_plls[i][j].n)
+				continue;
+
+			switch (sam9x7_plls[i][j].t) {
+			case PLL_TYPE_FRAC:
+				if (!strcmp(sam9x7_plls[i][j].p, "mainck"))
+					parent_hw = sam9x7_pmc->chws[PMC_MAIN];
+				else if (!strcmp(sam9x7_plls[i][j].p, "main_osc"))
+					parent_hw = main_osc_hw;
+				else
+					parent_hw = __clk_get_hw(of_clk_get_by_name
+								 (np, sam9x7_plls[i][j].p));
+
+				hw = sam9x60_clk_register_frac_pll(regmap,
+								   &pmc_pll_lock,
+								   sam9x7_plls[i][j].n,
+								   sam9x7_plls[i][j].p,
+								   parent_hw, i,
+								   sam9x7_plls[i][j].c,
+								   sam9x7_plls[i][j].l,
+								   sam9x7_plls[i][j].f);
+				break;
+
+			case PLL_TYPE_DIV:
+				hw = sam9x60_clk_register_div_pll(regmap,
+								  &pmc_pll_lock,
+								  sam9x7_plls[i][j].n,
+								  sam9x7_plls[i][j].p, NULL, i,
+								  sam9x7_plls[i][j].c,
+								  sam9x7_plls[i][j].l,
+								  sam9x7_plls[i][j].f, 0);
+				break;
+
+			default:
+				continue;
+			}
+
+			if (IS_ERR(hw))
+				goto err_free;
+
+			if (sam9x7_plls[i][j].eid)
+				sam9x7_pmc->chws[sam9x7_plls[i][j].eid] = hw;
+		}
+	}
+
+	parent_names[0] = md_slck_name;
+	parent_names[1] = "mainck";
+	parent_names[2] = "plla_divpmcck";
+	parent_names[3] = "upll_divpmcck";
+	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
+					   parent_names, NULL, &sam9x7_master_layout,
+					   &mck_characteristics, &mck_lock);
+	if (IS_ERR(hw))
+		goto err_free;
+
+	hw = at91_clk_register_master_div(regmap, "masterck_div",
+					  "masterck_pres", NULL, &sam9x7_master_layout,
+					  &mck_characteristics, &mck_lock,
+					  CLK_SET_RATE_GATE, 0);
+	if (IS_ERR(hw))
+		goto err_free;
+
+	sam9x7_pmc->chws[PMC_MCK] = hw;
+
+	parent_names[0] = "plla_divpmcck";
+	parent_names[1] = "upll_divpmcck";
+	parent_names[2] = "main_osc";
+	hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3);
+	if (IS_ERR(hw))
+		goto err_free;
+
+	parent_names[0] = md_slck_name;
+	parent_names[1] = td_slck_name;
+	parent_names[2] = "mainck";
+	parent_names[3] = "masterck_div";
+	parent_names[4] = "plla_divpmcck";
+	parent_names[5] = "upll_divpmcck";
+	parent_names[6] = "audiopll_divpmcck";
+	for (i = 0; i < 2; i++) {
+		char name[6];
+
+		snprintf(name, sizeof(name), "prog%d", i);
+
+		hw = at91_clk_register_programmable(regmap, name,
+						    parent_names, NULL, 7, i,
+						    &sam9x7_programmable_layout,
+						    NULL);
+		if (IS_ERR(hw))
+			goto err_free;
+
+		sam9x7_pmc->pchws[i] = hw;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(sam9x7_systemck); i++) {
+		hw = at91_clk_register_system(regmap, sam9x7_systemck[i].n,
+					      sam9x7_systemck[i].p, NULL,
+					      sam9x7_systemck[i].id,
+					      sam9x7_systemck[i].flags);
+		if (IS_ERR(hw))
+			goto err_free;
+
+		sam9x7_pmc->shws[sam9x7_systemck[i].id] = hw;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(sam9x7_periphck); i++) {
+		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
+							 &sam9x7_pcr_layout,
+							 sam9x7_periphck[i].n,
+							 "masterck_div", NULL,
+							 sam9x7_periphck[i].id,
+							 &range, INT_MIN,
+							 sam9x7_periphck[i].f);
+		if (IS_ERR(hw))
+			goto err_free;
+
+		sam9x7_pmc->phws[sam9x7_periphck[i].id] = hw;
+	}
+
+	parent_names[0] = md_slck_name;
+	parent_names[1] = td_slck_name;
+	parent_names[2] = "mainck";
+	parent_names[3] = "masterck_div";
+	for (i = 0; i < ARRAY_SIZE(sam9x7_gck); i++) {
+		u8 num_parents = 4 + sam9x7_gck[i].pp_count;
+		u32 *mux_table;
+
+		mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
+					  GFP_KERNEL);
+		if (!mux_table)
+			goto err_free;
+
+		PMC_INIT_TABLE(mux_table, 4);
+		PMC_FILL_TABLE(&mux_table[4], sam9x7_gck[i].pp_mux_table,
+			       sam9x7_gck[i].pp_count);
+		PMC_FILL_TABLE(&parent_names[4], sam9x7_gck[i].pp,
+			       sam9x7_gck[i].pp_count);
+
+		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
+						 &sam9x7_pcr_layout,
+						 sam9x7_gck[i].n,
+						 parent_names, NULL, mux_table,
+						 num_parents,
+						 sam9x7_gck[i].id,
+						 &sam9x7_gck[i].r,
+						 sam9x7_gck[i].pp_chg_id);
+		if (IS_ERR(hw))
+			goto err_free;
+
+		sam9x7_pmc->ghws[sam9x7_gck[i].id] = hw;
+		clk_mux_buffer[clk_mux_buffer_size++] = mux_table;
+	}
+
+	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x7_pmc);
+	kfree(clk_mux_buffer);
+
+	return;
+
+err_free:
+	if (clk_mux_buffer) {
+		for (i = 0; i < clk_mux_buffer_size; i++)
+			kfree(clk_mux_buffer[i]);
+		kfree(clk_mux_buffer);
+	}
+	kfree(sam9x7_pmc);
+}
+
+/* Some clks are used for a clocksource */
+CLK_OF_DECLARE(sam9x7_pmc, "microchip,sam9x7-pmc", sam9x7_pmc_setup);
-- 
2.25.1


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Re: [PATCH v4 27/39] clk: at91: sam9x7: add sam9x7 pmc driver

[claudiu beznea]

On 23.02.2024 19:28, Varshini Rajendran wrote:
> Add a driver for the PMC clocks of sam9x7 Soc family.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
> Changes in v4:
> - Changed variable name alloc_mem to clk_mux_buffer to be more
>   suggestive
> - Changed description of @f structure member appropriately
> ---
>  drivers/clk/at91/Makefile |   1 +
>  drivers/clk/at91/sam9x7.c | 946 ++++++++++++++++++++++++++++++++++++++
>  2 files changed, 947 insertions(+)
>  create mode 100644 drivers/clk/at91/sam9x7.c
> 
> diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
> index 89061b85e7d2..8e3684ba2c74 100644
> --- a/drivers/clk/at91/Makefile
> +++ b/drivers/clk/at91/Makefile
> @@ -20,6 +20,7 @@ obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o at91sam9rl.o at91sam9x5.o dt-compat.
>  obj-$(CONFIG_SOC_AT91SAM9) += at91sam9g45.o dt-compat.o
>  obj-$(CONFIG_SOC_AT91SAM9) += at91sam9n12.o at91sam9x5.o dt-compat.o
>  obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o
> +obj-$(CONFIG_SOC_SAM9X7) += sam9x7.o
>  obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o dt-compat.o
>  obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o dt-compat.o
>  obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o dt-compat.o
> diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
> new file mode 100644
> index 000000000000..d03387d2e35a
> --- /dev/null
> +++ b/drivers/clk/at91/sam9x7.c
> @@ -0,0 +1,946 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SAM9X7 PMC code.
> + *
> + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
> + *
> + */
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/slab.h>
> +
> +#include <dt-bindings/clock/at91.h>
> +
> +#include "pmc.h"
> +
> +static DEFINE_SPINLOCK(pmc_pll_lock);
> +static DEFINE_SPINLOCK(mck_lock);
> +
> +/**
> + * enum pll_ids - PLL clocks identifiers
> + * @PLL_ID_PLLA:	PLLA identifier
> + * @PLL_ID_UPLL:	UPLL identifier
> + * @PLL_ID_AUDIO:	Audio PLL identifier
> + * @PLL_ID_LVDS:	LVDS PLL identifier
> + * @PLL_ID_PLLA_DIV2:	PLLA DIV2 identifier
> + * @PLL_ID_MAX:		Max PLL Identifier
> + */
> +enum pll_ids {
> +	PLL_ID_PLLA,
> +	PLL_ID_UPLL,
> +	PLL_ID_AUDIO,
> +	PLL_ID_LVDS,
> +	PLL_ID_PLLA_DIV2,
> +	PLL_ID_MAX,
> +};
> +
> +/**
> + * enum pll_type - PLL type identifiers
> + * @PLL_TYPE_FRAC:	fractional PLL identifier
> + * @PLL_TYPE_DIV:	divider PLL identifier
> + */
> +enum pll_type {
> +	PLL_TYPE_FRAC,
> +	PLL_TYPE_DIV,
> +};
> +
> +static const struct clk_master_characteristics mck_characteristics = {
> +	.output = { .min = 32000000, .max = 266666667 },
> +	.divisors = { 1, 2, 4, 3, 5},
> +	.have_div3_pres = 1,
> +};
> +
> +static const struct clk_master_layout sam9x7_master_layout = {
> +	.mask = 0x373,
> +	.pres_shift = 4,
> +	.offset = 0x28,
> +};
> +
> +/* Fractional PLL core output range. */
> +static const struct clk_range plla_core_outputs[] = {
> +	{ .min = 375000000, .max = 1600000000 },
> +};
> +
> +static const struct clk_range upll_core_outputs[] = {
> +	{ .min = 600000000, .max = 1200000000 },
> +};
> +
> +static const struct clk_range lvdspll_core_outputs[] = {
> +	{ .min = 400000000, .max = 800000000 },
> +};
> +
> +static const struct clk_range audiopll_core_outputs[] = {
> +	{ .min = 400000000, .max = 800000000 },
> +};
> +
> +static const struct clk_range plladiv2_core_outputs[] = {
> +	{ .min = 375000000, .max = 1600000000 },
> +};
> +
> +/* Fractional PLL output range. */
> +static const struct clk_range plla_outputs[] = {
> +	{ .min = 732421, .max = 800000000 },
> +};
> +
> +static const struct clk_range upll_outputs[] = {
> +	{ .min = 300000000, .max = 600000000 },
> +};
> +
> +static const struct clk_range lvdspll_outputs[] = {
> +	{ .min = 10000000, .max = 800000000 },
> +};
> +
> +static const struct clk_range audiopll_outputs[] = {
> +	{ .min = 10000000, .max = 800000000 },
> +};
> +
> +static const struct clk_range plladiv2_outputs[] = {
> +	{ .min = 366210, .max = 400000000 },
> +};
> +
> +/* PLL characteristics. */
> +static const struct clk_pll_characteristics plla_characteristics = {
> +	.input = { .min = 20000000, .max = 50000000 },
> +	.num_output = ARRAY_SIZE(plla_outputs),
> +	.output = plla_outputs,
> +	.core_output = plla_core_outputs,
> +};
> +
> +static const struct clk_pll_characteristics upll_characteristics = {
> +	.input = { .min = 20000000, .max = 50000000 },
> +	.num_output = ARRAY_SIZE(upll_outputs),
> +	.output = upll_outputs,
> +	.core_output = upll_core_outputs,
> +	.upll = true,
> +};
> +
> +static const struct clk_pll_characteristics lvdspll_characteristics = {
> +	.input = { .min = 20000000, .max = 50000000 },
> +	.num_output = ARRAY_SIZE(lvdspll_outputs),
> +	.output = lvdspll_outputs,
> +	.core_output = lvdspll_core_outputs,
> +};
> +
> +static const struct clk_pll_characteristics audiopll_characteristics = {
> +	.input = { .min = 20000000, .max = 50000000 },
> +	.num_output = ARRAY_SIZE(audiopll_outputs),
> +	.output = audiopll_outputs,
> +	.core_output = audiopll_core_outputs,
> +};
> +
> +static const struct clk_pll_characteristics plladiv2_characteristics = {
> +	.input = { .min = 20000000, .max = 50000000 },
> +	.num_output = ARRAY_SIZE(plladiv2_outputs),
> +	.output = plladiv2_outputs,
> +	.core_output = plladiv2_core_outputs,
> +};
> +
> +/* Layout for fractional PLL ID PLLA. */
> +static const struct clk_pll_layout plla_frac_layout = {
> +	.mul_mask = GENMASK(31, 24),
> +	.frac_mask = GENMASK(21, 0),
> +	.mul_shift = 24,
> +	.frac_shift = 0,
> +	.div2 = 1,

It seems to me that this is not taken into account (see below).

> +};
> +
> +/* Layout for fractional PLLs. */
> +static const struct clk_pll_layout pll_frac_layout = {
> +	.mul_mask = GENMASK(31, 24),
> +	.frac_mask = GENMASK(21, 0),
> +	.mul_shift = 24,
> +	.frac_shift = 0,
> +};
> +
> +/* Layout for DIV PLLs. */
> +static const struct clk_pll_layout pll_divpmc_layout = {
> +	.div_mask = GENMASK(7, 0),
> +	.endiv_mask = BIT(29),
> +	.div_shift = 0,
> +	.endiv_shift = 29,
> +};
> +
> +/* Layout for DIV PLL ID PLLADIV2. */
> +static const struct clk_pll_layout plladiv2_divpmc_layout = {
> +	.div_mask = GENMASK(7, 0),
> +	.endiv_mask = BIT(29),
> +	.div_shift = 0,
> +	.endiv_shift = 29,
> +	.div2 = 1,
> +};
> +
> +/* Layout for DIVIO dividers. */
> +static const struct clk_pll_layout pll_divio_layout = {
> +	.div_mask	= GENMASK(19, 12),
> +	.endiv_mask	= BIT(30),
> +	.div_shift	= 12,
> +	.endiv_shift	= 30,
> +};
> +
> +/*
> + * PLL clocks description
> + * @n:		clock name
> + * @p:		clock parent
> + * @l:		clock layout
> + * @t:		clock type
> + * @c:		pll characteristics
> + * @f:		clock flags
> + * @eid:	export index in sam9x7->chws[] array
> + */
> +static const struct {
> +	const char *n;
> +	const char *p;
> +	const struct clk_pll_layout *l;
> +	u8 t;
> +	const struct clk_pll_characteristics *c;
> +	unsigned long f;
> +	u8 eid;
> +} sam9x7_plls[][PLL_ID_MAX] = {
> +	[PLL_ID_PLLA] = {
> +		{
> +			.n = "plla_fracck",
> +			.p = "mainck",
> +			.l = &plla_frac_layout,
> +			.t = PLL_TYPE_FRAC,
> +			/*
> +			 * This feeds plla_divpmcck which feeds CPU. It should
> +			 * not be disabled.
> +			 */
> +			.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
> +			.c = &plla_characteristics,
> +		},
> +
> +		{
> +			.n = "plla_divpmcck",
> +			.p = "plla_fracck",
> +			.l = &pll_divpmc_layout,

You mentioned in "[PATCH v4 24/39] clk: at91: sam9x7: add support for HW
PLL freq dividers" that this has div2 but it is registered w/ a layout that
has .div2 = 0.



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Re: [PATCH v4 27/39] clk: at91: sam9x7: add sam9x7 pmc driver

[Varshini.Rajendran]

Hi Claudiu,

On 11/03/24 11:28 am, claudiu beznea wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 23.02.2024 19:28, Varshini Rajendran wrote:
>> Add a driver for the PMC clocks of sam9x7 Soc family.
>>
>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>> ---
>> Changes in v4:
>> - Changed variable name alloc_mem to clk_mux_buffer to be more
>>    suggestive
>> - Changed description of @f structure member appropriately
>> ---
>>   drivers/clk/at91/Makefile |   1 +
>>   drivers/clk/at91/sam9x7.c | 946 ++++++++++++++++++++++++++++++++++++++
>>   2 files changed, 947 insertions(+)
>>   create mode 100644 drivers/clk/at91/sam9x7.c
>>
>> diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
>> index 89061b85e7d2..8e3684ba2c74 100644
>> --- a/drivers/clk/at91/Makefile
>> +++ b/drivers/clk/at91/Makefile
>> @@ -20,6 +20,7 @@ obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o at91sam9rl.o at91sam9x5.o dt-compat.
>>   obj-$(CONFIG_SOC_AT91SAM9) += at91sam9g45.o dt-compat.o
>>   obj-$(CONFIG_SOC_AT91SAM9) += at91sam9n12.o at91sam9x5.o dt-compat.o
>>   obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o
>> +obj-$(CONFIG_SOC_SAM9X7) += sam9x7.o
>>   obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o dt-compat.o
>>   obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o dt-compat.o
>>   obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o dt-compat.o
>> diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
>> new file mode 100644
>> index 000000000000..d03387d2e35a
>> --- /dev/null
>> +++ b/drivers/clk/at91/sam9x7.c
>> @@ -0,0 +1,946 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * SAM9X7 PMC code.
>> + *
>> + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
>> + *
>> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
>> + *
>> + */
>> +#include <linux/clk.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/slab.h>
>> +
>> +#include <dt-bindings/clock/at91.h>
>> +
>> +#include "pmc.h"
>> +
>> +static DEFINE_SPINLOCK(pmc_pll_lock);
>> +static DEFINE_SPINLOCK(mck_lock);
>> +
>> +/**
>> + * enum pll_ids - PLL clocks identifiers
>> + * @PLL_ID_PLLA:     PLLA identifier
>> + * @PLL_ID_UPLL:     UPLL identifier
>> + * @PLL_ID_AUDIO:    Audio PLL identifier
>> + * @PLL_ID_LVDS:     LVDS PLL identifier
>> + * @PLL_ID_PLLA_DIV2:        PLLA DIV2 identifier
>> + * @PLL_ID_MAX:              Max PLL Identifier
>> + */
>> +enum pll_ids {
>> +     PLL_ID_PLLA,
>> +     PLL_ID_UPLL,
>> +     PLL_ID_AUDIO,
>> +     PLL_ID_LVDS,
>> +     PLL_ID_PLLA_DIV2,
>> +     PLL_ID_MAX,
>> +};
>> +
>> +/**
>> + * enum pll_type - PLL type identifiers
>> + * @PLL_TYPE_FRAC:   fractional PLL identifier
>> + * @PLL_TYPE_DIV:    divider PLL identifier
>> + */
>> +enum pll_type {
>> +     PLL_TYPE_FRAC,
>> +     PLL_TYPE_DIV,
>> +};
>> +
>> +static const struct clk_master_characteristics mck_characteristics = {
>> +     .output = { .min = 32000000, .max = 266666667 },
>> +     .divisors = { 1, 2, 4, 3, 5},
>> +     .have_div3_pres = 1,
>> +};
>> +
>> +static const struct clk_master_layout sam9x7_master_layout = {
>> +     .mask = 0x373,
>> +     .pres_shift = 4,
>> +     .offset = 0x28,
>> +};
>> +
>> +/* Fractional PLL core output range. */
>> +static const struct clk_range plla_core_outputs[] = {
>> +     { .min = 375000000, .max = 1600000000 },
>> +};
>> +
>> +static const struct clk_range upll_core_outputs[] = {
>> +     { .min = 600000000, .max = 1200000000 },
>> +};
>> +
>> +static const struct clk_range lvdspll_core_outputs[] = {
>> +     { .min = 400000000, .max = 800000000 },
>> +};
>> +
>> +static const struct clk_range audiopll_core_outputs[] = {
>> +     { .min = 400000000, .max = 800000000 },
>> +};
>> +
>> +static const struct clk_range plladiv2_core_outputs[] = {
>> +     { .min = 375000000, .max = 1600000000 },
>> +};
>> +
>> +/* Fractional PLL output range. */
>> +static const struct clk_range plla_outputs[] = {
>> +     { .min = 732421, .max = 800000000 },
>> +};
>> +
>> +static const struct clk_range upll_outputs[] = {
>> +     { .min = 300000000, .max = 600000000 },
>> +};
>> +
>> +static const struct clk_range lvdspll_outputs[] = {
>> +     { .min = 10000000, .max = 800000000 },
>> +};
>> +
>> +static const struct clk_range audiopll_outputs[] = {
>> +     { .min = 10000000, .max = 800000000 },
>> +};
>> +
>> +static const struct clk_range plladiv2_outputs[] = {
>> +     { .min = 366210, .max = 400000000 },
>> +};
>> +
>> +/* PLL characteristics. */
>> +static const struct clk_pll_characteristics plla_characteristics = {
>> +     .input = { .min = 20000000, .max = 50000000 },
>> +     .num_output = ARRAY_SIZE(plla_outputs),
>> +     .output = plla_outputs,
>> +     .core_output = plla_core_outputs,
>> +};
>> +
>> +static const struct clk_pll_characteristics upll_characteristics = {
>> +     .input = { .min = 20000000, .max = 50000000 },
>> +     .num_output = ARRAY_SIZE(upll_outputs),
>> +     .output = upll_outputs,
>> +     .core_output = upll_core_outputs,
>> +     .upll = true,
>> +};
>> +
>> +static const struct clk_pll_characteristics lvdspll_characteristics = {
>> +     .input = { .min = 20000000, .max = 50000000 },
>> +     .num_output = ARRAY_SIZE(lvdspll_outputs),
>> +     .output = lvdspll_outputs,
>> +     .core_output = lvdspll_core_outputs,
>> +};
>> +
>> +static const struct clk_pll_characteristics audiopll_characteristics = {
>> +     .input = { .min = 20000000, .max = 50000000 },
>> +     .num_output = ARRAY_SIZE(audiopll_outputs),
>> +     .output = audiopll_outputs,
>> +     .core_output = audiopll_core_outputs,
>> +};
>> +
>> +static const struct clk_pll_characteristics plladiv2_characteristics = {
>> +     .input = { .min = 20000000, .max = 50000000 },
>> +     .num_output = ARRAY_SIZE(plladiv2_outputs),
>> +     .output = plladiv2_outputs,
>> +     .core_output = plladiv2_core_outputs,
>> +};
>> +
>> +/* Layout for fractional PLL ID PLLA. */
>> +static const struct clk_pll_layout plla_frac_layout = {
>> +     .mul_mask = GENMASK(31, 24),
>> +     .frac_mask = GENMASK(21, 0),
>> +     .mul_shift = 24,
>> +     .frac_shift = 0,
>> +     .div2 = 1,
> 
> It seems to me that this is not taken into account (see below).
> 
>> +};
>> +
>> +/* Layout for fractional PLLs. */
>> +static const struct clk_pll_layout pll_frac_layout = {
>> +     .mul_mask = GENMASK(31, 24),
>> +     .frac_mask = GENMASK(21, 0),
>> +     .mul_shift = 24,
>> +     .frac_shift = 0,
>> +};
>> +
>> +/* Layout for DIV PLLs. */
>> +static const struct clk_pll_layout pll_divpmc_layout = {
>> +     .div_mask = GENMASK(7, 0),
>> +     .endiv_mask = BIT(29),
>> +     .div_shift = 0,
>> +     .endiv_shift = 29,
>> +};
>> +
>> +/* Layout for DIV PLL ID PLLADIV2. */
>> +static const struct clk_pll_layout plladiv2_divpmc_layout = {
>> +     .div_mask = GENMASK(7, 0),
>> +     .endiv_mask = BIT(29),
>> +     .div_shift = 0,
>> +     .endiv_shift = 29,
>> +     .div2 = 1,
>> +};
>> +
>> +/* Layout for DIVIO dividers. */
>> +static const struct clk_pll_layout pll_divio_layout = {
>> +     .div_mask       = GENMASK(19, 12),
>> +     .endiv_mask     = BIT(30),
>> +     .div_shift      = 12,
>> +     .endiv_shift    = 30,
>> +};
>> +
>> +/*
>> + * PLL clocks description
>> + * @n:               clock name
>> + * @p:               clock parent
>> + * @l:               clock layout
>> + * @t:               clock type
>> + * @c:               pll characteristics
>> + * @f:               clock flags
>> + * @eid:     export index in sam9x7->chws[] array
>> + */
>> +static const struct {
>> +     const char *n;
>> +     const char *p;
>> +     const struct clk_pll_layout *l;
>> +     u8 t;
>> +     const struct clk_pll_characteristics *c;
>> +     unsigned long f;
>> +     u8 eid;
>> +} sam9x7_plls[][PLL_ID_MAX] = {
>> +     [PLL_ID_PLLA] = {
>> +             {
>> +                     .n = "plla_fracck",
>> +                     .p = "mainck",
>> +                     .l = &plla_frac_layout,
>> +                     .t = PLL_TYPE_FRAC,
>> +                     /*
>> +                      * This feeds plla_divpmcck which feeds CPU. It should
>> +                      * not be disabled.
>> +                      */
>> +                     .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
>> +                     .c = &plla_characteristics,
>> +             },
>> +
>> +             {
>> +                     .n = "plla_divpmcck",
>> +                     .p = "plla_fracck",
>> +                     .l = &pll_divpmc_layout,
> 
> You mentioned in "[PATCH v4 24/39] clk: at91: sam9x7: add support for HW
> PLL freq dividers" that this has div2 but it is registered w/ a layout that
> has .div2 = 0.

This is handled in the above plla_fracck fractional part as defined in 
the plla_frac_layout.
> 
> 

-- 
Thanks and Regards,
Varshini Rajendran.

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Re: [PATCH v4 27/39] clk: at91: sam9x7: add sam9x7 pmc driver

[claudiu beznea]

On 18.03.2024 11:25, Varshini.Rajendran@microchip.com wrote:
> Hi Claudiu,
> 
> On 11/03/24 11:28 am, claudiu beznea wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 23.02.2024 19:28, Varshini Rajendran wrote:
>>> Add a driver for the PMC clocks of sam9x7 Soc family.
>>>
>>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>>> ---
>>> Changes in v4:
>>> - Changed variable name alloc_mem to clk_mux_buffer to be more
>>>    suggestive
>>> - Changed description of @f structure member appropriately
>>> ---
>>>   drivers/clk/at91/Makefile |   1 +
>>>   drivers/clk/at91/sam9x7.c | 946 ++++++++++++++++++++++++++++++++++++++
>>>   2 files changed, 947 insertions(+)
>>>   create mode 100644 drivers/clk/at91/sam9x7.c
>>>
>>> diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
>>> index 89061b85e7d2..8e3684ba2c74 100644
>>> --- a/drivers/clk/at91/Makefile
>>> +++ b/drivers/clk/at91/Makefile
[ ... ]

>>> +static const struct {
>>> +     const char *n;
>>> +     const char *p;
>>> +     const struct clk_pll_layout *l;
>>> +     u8 t;
>>> +     const struct clk_pll_characteristics *c;
>>> +     unsigned long f;
>>> +     u8 eid;
>>> +} sam9x7_plls[][PLL_ID_MAX] = {
>>> +     [PLL_ID_PLLA] = {
>>> +             {
>>> +                     .n = "plla_fracck",
>>> +                     .p = "mainck",
>>> +                     .l = &plla_frac_layout,
>>> +                     .t = PLL_TYPE_FRAC,
>>> +                     /*
>>> +                      * This feeds plla_divpmcck which feeds CPU. It should
>>> +                      * not be disabled.
>>> +                      */
>>> +                     .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
>>> +                     .c = &plla_characteristics,
>>> +             },
>>> +
>>> +             {
>>> +                     .n = "plla_divpmcck",
>>> +                     .p = "plla_fracck",
>>> +                     .l = &pll_divpmc_layout,
>>
>> You mentioned in "[PATCH v4 24/39] clk: at91: sam9x7: add support for HW
>> PLL freq dividers" that this has div2 but it is registered w/ a layout that
>> has .div2 = 0.
> 
> This is handled in the above plla_fracck fractional part as defined in 
> the plla_frac_layout.

Ah, right. I missed the changes in sam9x60_frac_pll_recalc_rate().


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[PATCH v4 28/39] dt-bindings: irqchip/atmel-aic5: Add support for sam9x7 aic

[Varshini Rajendran]

Document the support added for the Advanced interrupt controller(AIC)
chip in the sam9x7 SoC family.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Changes in v4:
- Updated Acked-by tag.
---
 .../devicetree/bindings/interrupt-controller/atmel,aic.txt      | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
index 7079d44bf3ba..5fb9366c94a1 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
@@ -4,7 +4,7 @@ Required properties:
 - compatible: Should be:
     - "atmel,<chip>-aic" where  <chip> can be "at91rm9200", "sama5d2",
       "sama5d3" or "sama5d4"
-    - "microchip,<chip>-aic" where <chip> can be "sam9x60"
+    - "microchip,<chip>-aic" where <chip> can be "sam9x60" or "sam9x7"
 
 - interrupt-controller: Identifies the node as an interrupt controller.
 - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
-- 
2.25.1


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[PATCH v4 29/39] irqchip/atmel-aic5: Add support to get nirqs from DT for sam9x60 & sam9x7

[Varshini Rajendran]

Add support to get number of IRQs from the respective DT node for sam9x60
and sam9x7 devices. Since only this factor differs between the two SoCs,
this patch adds support for the same. Adapt the sam9x60 dtsi
accordingly.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v4:
- Changed the implementation to fetch the NIRQs from DT as per the
  comment to avoid introducing a new compatible when this is the only
  difference between the SoCs related to this IP.
---
 arch/arm/boot/dts/microchip/sam9x60.dtsi |  1 +
 drivers/irqchip/irq-atmel-aic5.c         | 11 ++++++++---
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi
index 73d570a17269..e405f68c9f54 100644
--- a/arch/arm/boot/dts/microchip/sam9x60.dtsi
+++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi
@@ -1201,6 +1201,7 @@ aic: interrupt-controller@fffff100 {
 				interrupt-controller;
 				reg = <0xfffff100 0x100>;
 				atmel,external-irqs = <31>;
+				microchip,nr-irqs = <50>;
 			};
 
 			dbgu: serial@fffff200 {
diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c
index 145535bd7560..5d96ad8860d3 100644
--- a/drivers/irqchip/irq-atmel-aic5.c
+++ b/drivers/irqchip/irq-atmel-aic5.c
@@ -398,11 +398,16 @@ static int __init sama5d4_aic5_of_init(struct device_node *node,
 }
 IRQCHIP_DECLARE(sama5d4_aic5, "atmel,sama5d4-aic", sama5d4_aic5_of_init);
 
-#define NR_SAM9X60_IRQS		50
-
 static int __init sam9x60_aic5_of_init(struct device_node *node,
 				       struct device_node *parent)
 {
-	return aic5_of_init(node, parent, NR_SAM9X60_IRQS);
+	int ret, nr_irqs;
+
+	ret = of_property_read_u32(node, "microchip,nr-irqs", &nr_irqs);
+	if (ret) {
+		pr_err("Not found microchip,nr-irqs property\n");
+		return ret;
+	}
+	return aic5_of_init(node, parent, nr_irqs);
 }
 IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_init);
-- 
2.25.1


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Re: [PATCH v4 29/39] irqchip/atmel-aic5: Add support to get nirqs from DT for sam9x60 & sam9x7

[claudiu beznea]

On 23.02.2024 19:29, Varshini Rajendran wrote:
> Add support to get number of IRQs from the respective DT node for sam9x60
> and sam9x7 devices. Since only this factor differs between the two SoCs,
> this patch adds support for the same. Adapt the sam9x60 dtsi
> accordingly.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
> Changes in v4:
> - Changed the implementation to fetch the NIRQs from DT as per the
>   comment to avoid introducing a new compatible when this is the only
>   difference between the SoCs related to this IP.
> ---
>  arch/arm/boot/dts/microchip/sam9x60.dtsi |  1 +
>  drivers/irqchip/irq-atmel-aic5.c         | 11 ++++++++---
>  2 files changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi
> index 73d570a17269..e405f68c9f54 100644
> --- a/arch/arm/boot/dts/microchip/sam9x60.dtsi
> +++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi
> @@ -1201,6 +1201,7 @@ aic: interrupt-controller@fffff100 {
>  				interrupt-controller;
>  				reg = <0xfffff100 0x100>;
>  				atmel,external-irqs = <31>;
> +				microchip,nr-irqs = <50>;
>  			};
>  
>  			dbgu: serial@fffff200 {
> diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c
> index 145535bd7560..5d96ad8860d3 100644
> --- a/drivers/irqchip/irq-atmel-aic5.c
> +++ b/drivers/irqchip/irq-atmel-aic5.c
> @@ -398,11 +398,16 @@ static int __init sama5d4_aic5_of_init(struct device_node *node,
>  }
>  IRQCHIP_DECLARE(sama5d4_aic5, "atmel,sama5d4-aic", sama5d4_aic5_of_init);
>  
> -#define NR_SAM9X60_IRQS		50
> -
>  static int __init sam9x60_aic5_of_init(struct device_node *node,
>  				       struct device_node *parent)
>  {
> -	return aic5_of_init(node, parent, NR_SAM9X60_IRQS);
> +	int ret, nr_irqs;
> +
> +	ret = of_property_read_u32(node, "microchip,nr-irqs", &nr_irqs);
> +	if (ret) {
> +		pr_err("Not found microchip,nr-irqs property\n");

This breaks the ABI. You should ensure old device trees are still working
with this patch.

> +		return ret;
> +	}
> +	return aic5_of_init(node, parent, nr_irqs);
>  }
>  IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_init);

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Re: [PATCH v4 29/39] irqchip/atmel-aic5: Add support to get nirqs from DT for sam9x60 & sam9x7

[Varshini.Rajendran]

On 03/03/24 5:51 pm, claudiu beznea wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 23.02.2024 19:29, Varshini Rajendran wrote:
>> Add support to get number of IRQs from the respective DT node for sam9x60
>> and sam9x7 devices. Since only this factor differs between the two SoCs,
>> this patch adds support for the same. Adapt the sam9x60 dtsi
>> accordingly.
>>
>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>> ---
>> Changes in v4:
>> - Changed the implementation to fetch the NIRQs from DT as per the
>>    comment to avoid introducing a new compatible when this is the only
>>    difference between the SoCs related to this IP.
>> ---
>>   arch/arm/boot/dts/microchip/sam9x60.dtsi |  1 +
>>   drivers/irqchip/irq-atmel-aic5.c         | 11 ++++++++---
>>   2 files changed, 9 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi
>> index 73d570a17269..e405f68c9f54 100644
>> --- a/arch/arm/boot/dts/microchip/sam9x60.dtsi
>> +++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi
>> @@ -1201,6 +1201,7 @@ aic: interrupt-controller@fffff100 {
>>                                interrupt-controller;
>>                                reg = <0xfffff100 0x100>;
>>                                atmel,external-irqs = <31>;
>> +                             microchip,nr-irqs = <50>;
>>                        };
>>
>>                        dbgu: serial@fffff200 {
>> diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c
>> index 145535bd7560..5d96ad8860d3 100644
>> --- a/drivers/irqchip/irq-atmel-aic5.c
>> +++ b/drivers/irqchip/irq-atmel-aic5.c
>> @@ -398,11 +398,16 @@ static int __init sama5d4_aic5_of_init(struct device_node *node,
>>   }
>>   IRQCHIP_DECLARE(sama5d4_aic5, "atmel,sama5d4-aic", sama5d4_aic5_of_init);
>>
>> -#define NR_SAM9X60_IRQS              50
>> -
>>   static int __init sam9x60_aic5_of_init(struct device_node *node,
>>                                       struct device_node *parent)
>>   {
>> -     return aic5_of_init(node, parent, NR_SAM9X60_IRQS);
>> +     int ret, nr_irqs;
>> +
>> +     ret = of_property_read_u32(node, "microchip,nr-irqs", &nr_irqs);
>> +     if (ret) {
>> +             pr_err("Not found microchip,nr-irqs property\n");
> 
> This breaks the ABI. You should ensure old device trees are still working
> with this patch.

The only older device that uses this API is sam9x60 and the newly added 
sam9x7. This change has been tested to be working fine in both the 
devices. If you still want me to use the macros as a fallback in the 
failure case I can do it. But this change was proposed to avoid adding 
macros in the first place. I can remove the error check just like they 
do while getting other device tree properties. Or if this is just a 
concern of the old devices working with the new change, then sam9x60 
works. Please let me know how to proceed.
> 
>> +             return ret;
>> +     }
>> +     return aic5_of_init(node, parent, nr_irqs);
>>   }
>>   IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_init);

-- 
Thanks and Regards,
Varshini Rajendran.

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Re: [PATCH v4 29/39] irqchip/atmel-aic5: Add support to get nirqs from DT for sam9x60 & sam9x7

[Conor Dooley]

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On Fri, Mar 08, 2024 at 08:50:43AM +0000, Varshini.Rajendran@microchip.com wrote:
> On 03/03/24 5:51 pm, claudiu beznea wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > On 23.02.2024 19:29, Varshini Rajendran wrote:
> >> Add support to get number of IRQs from the respective DT node for sam9x60
> >> and sam9x7 devices. Since only this factor differs between the two SoCs,
> >> this patch adds support for the same. Adapt the sam9x60 dtsi
> >> accordingly.
> >>
> >> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> >> ---
> >> Changes in v4:
> >> - Changed the implementation to fetch the NIRQs from DT as per the
> >>    comment to avoid introducing a new compatible when this is the only
> >>    difference between the SoCs related to this IP.
> >> ---
> >>   arch/arm/boot/dts/microchip/sam9x60.dtsi |  1 +
> >>   drivers/irqchip/irq-atmel-aic5.c         | 11 ++++++++---

Driver and binding changes should be in different patches. Having them
in the same patch is usually a red flag for ABI breakage.

> >>   2 files changed, 9 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi
> >> index 73d570a17269..e405f68c9f54 100644
> >> --- a/arch/arm/boot/dts/microchip/sam9x60.dtsi
> >> +++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi
> >> @@ -1201,6 +1201,7 @@ aic: interrupt-controller@fffff100 {
> >>                                interrupt-controller;
> >>                                reg = <0xfffff100 0x100>;
> >>                                atmel,external-irqs = <31>;
> >> +                             microchip,nr-irqs = <50>;
> >>                        };
> >>
> >>                        dbgu: serial@fffff200 {
> >> diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c
> >> index 145535bd7560..5d96ad8860d3 100644
> >> --- a/drivers/irqchip/irq-atmel-aic5.c
> >> +++ b/drivers/irqchip/irq-atmel-aic5.c
> >> @@ -398,11 +398,16 @@ static int __init sama5d4_aic5_of_init(struct device_node *node,
> >>   }
> >>   IRQCHIP_DECLARE(sama5d4_aic5, "atmel,sama5d4-aic", sama5d4_aic5_of_init);
> >>
> >> -#define NR_SAM9X60_IRQS              50
> >> -
> >>   static int __init sam9x60_aic5_of_init(struct device_node *node,
> >>                                       struct device_node *parent)
> >>   {
> >> -     return aic5_of_init(node, parent, NR_SAM9X60_IRQS);
> >> +     int ret, nr_irqs;
> >> +
> >> +     ret = of_property_read_u32(node, "microchip,nr-irqs", &nr_irqs);
> >> +     if (ret) {
> >> +             pr_err("Not found microchip,nr-irqs property\n");
> > 
> > This breaks the ABI. You should ensure old device trees are still working
> > with this patch.
> 
> The only older device that uses this API is sam9x60 and the newly added 
> sam9x7. This change has been tested to be working fine in both the 
> devices.

Does it still work for a sam9x60 that does not have "microchip,nr-irqs"?
I can't see how it would, because you remove the define and return an
error. That's a pretty clear ABI breakage to me and I don't think it is
justified.

> If you still want me to use the macros as a fallback in the 
> failure case I can do it. But this change was proposed to avoid adding 
> macros in the first place. I can remove the error check just like they 
> do while getting other device tree properties. Or if this is just a 
> concern of the old devices working with the new change, then sam9x60 
> works. Please let me know how to proceed.

I just noticed that this property is not documented in a binding. The
first thing you would will be asked when trying to add that is "why can
this not be determined based on the compatible", which means back to
having a define in the driver.
That said, having specific $soc_aic5_of_init() functions for each SoC
seems silly when usually only the number of interrupts changes. The
number of IRQs could be in the match data and you could use
aic5_of_init in your IRQCHIP_DECLARE directly.

> >> +             return ret;
> >> +     }
> >> +     return aic5_of_init(node, parent, nr_irqs);
> >>   }
> >>   IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_init);
> 
> -- 
> Thanks and Regards,
> Varshini Rajendran.
> 

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Re: [PATCH v4 29/39] irqchip/atmel-aic5: Add support to get nirqs from DT for sam9x60 & sam9x7

[claudiu beznea]

On 08.03.2024 10:50, Varshini.Rajendran@microchip.com wrote:
> On 03/03/24 5:51 pm, claudiu beznea wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 23.02.2024 19:29, Varshini Rajendran wrote:
>>> Add support to get number of IRQs from the respective DT node for sam9x60
>>> and sam9x7 devices. Since only this factor differs between the two SoCs,
>>> this patch adds support for the same. Adapt the sam9x60 dtsi
>>> accordingly.
>>>
>>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>>> ---
>>> Changes in v4:
>>> - Changed the implementation to fetch the NIRQs from DT as per the
>>>    comment to avoid introducing a new compatible when this is the only
>>>    difference between the SoCs related to this IP.
>>> ---
>>>   arch/arm/boot/dts/microchip/sam9x60.dtsi |  1 +
>>>   drivers/irqchip/irq-atmel-aic5.c         | 11 ++++++++---
>>>   2 files changed, 9 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi
>>> index 73d570a17269..e405f68c9f54 100644
>>> --- a/arch/arm/boot/dts/microchip/sam9x60.dtsi
>>> +++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi
>>> @@ -1201,6 +1201,7 @@ aic: interrupt-controller@fffff100 {
>>>                                interrupt-controller;
>>>                                reg = <0xfffff100 0x100>;
>>>                                atmel,external-irqs = <31>;
>>> +                             microchip,nr-irqs = <50>;
>>>                        };
>>>
>>>                        dbgu: serial@fffff200 {
>>> diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c
>>> index 145535bd7560..5d96ad8860d3 100644
>>> --- a/drivers/irqchip/irq-atmel-aic5.c
>>> +++ b/drivers/irqchip/irq-atmel-aic5.c
>>> @@ -398,11 +398,16 @@ static int __init sama5d4_aic5_of_init(struct device_node *node,
>>>   }
>>>   IRQCHIP_DECLARE(sama5d4_aic5, "atmel,sama5d4-aic", sama5d4_aic5_of_init);
>>>
>>> -#define NR_SAM9X60_IRQS              50
>>> -
>>>   static int __init sam9x60_aic5_of_init(struct device_node *node,
>>>                                       struct device_node *parent)
>>>   {
>>> -     return aic5_of_init(node, parent, NR_SAM9X60_IRQS);
>>> +     int ret, nr_irqs;
>>> +
>>> +     ret = of_property_read_u32(node, "microchip,nr-irqs", &nr_irqs);
>>> +     if (ret) {
>>> +             pr_err("Not found microchip,nr-irqs property\n");
>>
>> This breaks the ABI. You should ensure old device trees are still working
>> with this patch.
> 
> The only older device that uses this API is sam9x60 and the newly added 
> sam9x7. This change has been tested to be working fine in both the 
> devices.

As Conor explained, the code in this patch should work with device trees
from previous kernel releases (thus not having microchip,nr-irqs DT binding).

> If you still want me to use the macros as a fallback in the 
> failure case I can do it. But this change was proposed to avoid adding 
> macros in the first place. I can remove the error check just like they 
> do while getting other device tree properties. Or if this is just a 
> concern of the old devices working with the new change, then sam9x60 
> works. Please let me know how to proceed.
>>
>>> +             return ret;
>>> +     }
>>> +     return aic5_of_init(node, parent, nr_irqs);
>>>   }
>>>   IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_init);
> 

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[PATCH v4 30/39] power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7

[Varshini Rajendran]

Use sam9x7 pmc's compatible to lookup for in the SHDWC driver.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
Changes in v4:
- Updated Acked-by tag
---
 drivers/power/reset/at91-sama5d2_shdwc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c
index 959ce0dbe91d..2121d7e74e12 100644
--- a/drivers/power/reset/at91-sama5d2_shdwc.c
+++ b/drivers/power/reset/at91-sama5d2_shdwc.c
@@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] = {
 	{ .compatible = "atmel,sama5d2-pmc" },
 	{ .compatible = "microchip,sam9x60-pmc" },
 	{ .compatible = "microchip,sama7g5-pmc" },
+	{ .compatible = "microchip,sam9x7-pmc" },
 	{ /* Sentinel. */ }
 };
 
-- 
2.25.1


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Re: [PATCH v4 30/39] power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7

[claudiu beznea]

On 23.02.2024 19:29, Varshini Rajendran wrote:
> Use sam9x7 pmc's compatible to lookup for in the SHDWC driver.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
> Changes in v4:
> - Updated Acked-by tag
> ---
>  drivers/power/reset/at91-sama5d2_shdwc.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c
> index 959ce0dbe91d..2121d7e74e12 100644
> --- a/drivers/power/reset/at91-sama5d2_shdwc.c
> +++ b/drivers/power/reset/at91-sama5d2_shdwc.c
> @@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] = {
>  	{ .compatible = "atmel,sama5d2-pmc" },
>  	{ .compatible = "microchip,sam9x60-pmc" },
>  	{ .compatible = "microchip,sama7g5-pmc" },
> +	{ .compatible = "microchip,sam9x7-pmc" },

Maybe would be better to add a phandle in DT instead of continuing
populating this array. But then the backward compatibility should be
preserved. I leave this to Sebastian.

>  	{ /* Sentinel. */ }
>  };
>  

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[PATCH v4 33/39] dt-bindings: reset: atmel,at91sam9260-reset: add sam9x7

[Varshini Rajendran]

Add documentation for SAM9X7 reset controller.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
---
Changes in v4:
- Updated Acked-by and Reviewed-by tags.
---
 .../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml    | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
index 98465d26949e..c3b33bbc7319 100644
--- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
@@ -26,6 +26,10 @@ properties:
       - items:
           - const: atmel,sama5d3-rstc
           - const: atmel,at91sam9g45-rstc
+      - items:
+          - enum:
+              - microchip,sam9x7-rstc
+          - const: microchip,sam9x60-rstc
 
   reg:
     minItems: 1
-- 
2.25.1


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[PATCH v4 34/39] dt-bindings: power: reset: atmel,sama5d2-shdwc: add sam9x7

[Varshini Rajendran]

Add shutdown controller DT bindings.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
Changes in v4:
- Updated Acked-by and Reviewed-by tags
---
 .../devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml   | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml
index 8c58e12cdb60..0735ceb7c103 100644
--- a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml
+++ b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml
@@ -22,6 +22,9 @@ properties:
       - enum:
           - atmel,sama5d2-shdwc
           - microchip,sam9x60-shdwc
+      - items:
+          - const: microchip,sam9x7-shdwc
+          - const: microchip,sam9x60-shdwc
 
   reg:
     maxItems: 1
-- 
2.25.1


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[PATCH v4 35/39] ARM: at91: Kconfig: add config flag for SAM9X7 SoC

[Varshini Rajendran]

Add config flag for sam9x7 SoC.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
---
Changes in v4:
- Updated Reviewed-by tag
---
 arch/arm/mach-at91/Kconfig | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index a8c022b4c053..49d38a3a47de 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -141,11 +141,28 @@ config SOC_SAM9X60
 	help
 	  Select this if you are using Microchip's SAM9X60 SoC
 
+config SOC_SAM9X7
+	bool "SAM9X7"
+	depends on ARCH_MULTI_V5
+	select ATMEL_AIC5_IRQ
+	select ATMEL_PM if PM
+	select ATMEL_SDRAMC
+	select CPU_ARM926T
+	select HAVE_AT91_USB_CLK
+	select HAVE_AT91_GENERATED_CLK
+	select HAVE_AT91_SAM9X60_PLL
+	select MEMORY
+	select PINCTRL_AT91
+	select SOC_SAM_V4_V5
+	select SRAM if PM
+	help
+	  Select this if you are using Microchip's SAM9X7 SoC
+
 comment "Clocksource driver selection"
 
 config ATMEL_CLOCKSOURCE_PIT
 	bool "Periodic Interval Timer (PIT) support"
-	depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
+	depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5
 	default SOC_AT91SAM9 || SOC_SAMA5
 	select ATMEL_PIT
 	help
@@ -155,7 +172,7 @@ config ATMEL_CLOCKSOURCE_PIT
 
 config ATMEL_CLOCKSOURCE_TCB
 	bool "Timer Counter Blocks (TCB) support"
-	default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
+	default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5
 	select ATMEL_TCB_CLKSRC
 	help
 	  Select this to get a high precision clocksource based on a
@@ -166,7 +183,7 @@ config ATMEL_CLOCKSOURCE_TCB
 
 config MICROCHIP_CLOCKSOURCE_PIT64B
 	bool "64-bit Periodic Interval Timer (PIT64B) support"
-	default SOC_SAM9X60 || SOC_SAMA7
+	default SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA7
 	select MICROCHIP_PIT64B
 	help
 	  Select this to get a high resolution clockevent (SAM9X60) or
-- 
2.25.1


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Re: [PATCH v4 35/39] ARM: at91: Kconfig: add config flag for SAM9X7 SoC

[claudiu beznea]

On 23.02.2024 19:30, Varshini Rajendran wrote:
> Add config flag for sam9x7 SoC.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
> ---
> Changes in v4:
> - Updated Reviewed-by tag
> ---
>  arch/arm/mach-at91/Kconfig | 23 ++++++++++++++++++++---
>  1 file changed, 20 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
> index a8c022b4c053..49d38a3a47de 100644
> --- a/arch/arm/mach-at91/Kconfig
> +++ b/arch/arm/mach-at91/Kconfig
> @@ -141,11 +141,28 @@ config SOC_SAM9X60
>  	help
>  	  Select this if you are using Microchip's SAM9X60 SoC
>  
> +config SOC_SAM9X7
> +	bool "SAM9X7"
> +	depends on ARCH_MULTI_V5
> +	select ATMEL_AIC5_IRQ
> +	select ATMEL_PM if PM
> +	select ATMEL_SDRAMC

This flag doesn't exist anymore.

> +	select CPU_ARM926T
> +	select HAVE_AT91_USB_CLK
> +	select HAVE_AT91_GENERATED_CLK
> +	select HAVE_AT91_SAM9X60_PLL
> +	select MEMORY
> +	select PINCTRL_AT91
> +	select SOC_SAM_V4_V5
> +	select SRAM if PM
> +	help
> +	  Select this if you are using Microchip's SAM9X7 SoC
> +
>  comment "Clocksource driver selection"
>  
>  config ATMEL_CLOCKSOURCE_PIT
>  	bool "Periodic Interval Timer (PIT) support"
> -	depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
> +	depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5
>  	default SOC_AT91SAM9 || SOC_SAMA5
>  	select ATMEL_PIT
>  	help
> @@ -155,7 +172,7 @@ config ATMEL_CLOCKSOURCE_PIT
>  
>  config ATMEL_CLOCKSOURCE_TCB
>  	bool "Timer Counter Blocks (TCB) support"
> -	default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
> +	default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5
>  	select ATMEL_TCB_CLKSRC
>  	help
>  	  Select this to get a high precision clocksource based on a
> @@ -166,7 +183,7 @@ config ATMEL_CLOCKSOURCE_TCB
>  
>  config MICROCHIP_CLOCKSOURCE_PIT64B
>  	bool "64-bit Periodic Interval Timer (PIT64B) support"
> -	default SOC_SAM9X60 || SOC_SAMA7
> +	default SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA7
>  	select MICROCHIP_PIT64B
>  	help
>  	  Select this to get a high resolution clockevent (SAM9X60) or

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[PATCH v4 36/39] ARM: configs: at91: enable config flags for sam9x7 SoC family

[Varshini Rajendran]

Enable config flags for SAM9X7 SoC for the sam9x7 SoC family.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 arch/arm/configs/at91_dt_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 1d53aec4c836..880f0c0f4cc3 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -16,6 +16,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_SOC_AT91RM9200=y
 CONFIG_SOC_AT91SAM9=y
 CONFIG_SOC_SAM9X60=y
+CONFIG_SOC_SAM9X7=y
 # CONFIG_ATMEL_CLOCKSOURCE_PIT is not set
 CONFIG_AEABI=y
 CONFIG_UACCESS_WITH_MEMCPY=y
-- 
2.25.1


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[PATCH v4 38/39] dt-bindings: arm: add sam9x75 curiosity board

[Varshini Rajendran]

Add documentation for SAM9X75 Curiosity board.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
index 89d75fbb1de4..d74d3a4701ac 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
@@ -106,6 +106,12 @@ properties:
           - const: microchip,sam9x60
           - const: atmel,at91sam9
 
+      - description: Microchip SAM9X7 Evaluation Boards
+        items:
+          - const: microchip,sam9x75-curiosity
+          - const: microchip,sam9x7
+          - const: atmel,at91sam9
+
       - description: Nattis v2 board with Natte v2 power board
         items:
           - const: axentia,nattis-2
-- 
2.25.1


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Re: [PATCH v4 38/39] dt-bindings: arm: add sam9x75 curiosity board

[Rob Herring]

On Fri, 23 Feb 2024 23:01:00 +0530, Varshini Rajendran wrote:
> Add documentation for SAM9X75 Curiosity board.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>


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[PATCH v4 39/39] ARM: dts: at91: sam9x75_curiosity: add sam9x75 curiosity board

[Varshini Rajendran]

Add device tree file for sam9x75 curiosity board.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v4:
- Removed full node paths
- Renamed Leds with color names
- Corrected regulator node names
- Added support for classd and i2s nodes and their corresponding
  pinctrl nodes
- Dropped USB nodes owing to the discussion here
https://lore.kernel.org/linux-devicetree/CAL_JsqJ9PrX6fj-EbffeJce09MXs=B7t+KS_kOinxaRx38=WxA@mail.gmail.com/
(Explained elaborately in the cover letter)
- Updated the linux,code property with the necessary value
---
 arch/arm/boot/dts/microchip/Makefile          |   3 +
 .../dts/microchip/at91-sam9x75_curiosity.dts  | 309 ++++++++++++++++++
 2 files changed, 312 insertions(+)
 create mode 100644 arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts

diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile
index efde9546c8f4..5b3d518da319 100644
--- a/arch/arm/boot/dts/microchip/Makefile
+++ b/arch/arm/boot/dts/microchip/Makefile
@@ -12,6 +12,7 @@ DTC_FLAGS_at91-sama5d3_eds := -@
 DTC_FLAGS_at91-sama5d3_xplained := -@
 DTC_FLAGS_at91-sama5d4_xplained := -@
 DTC_FLAGS_at91-sama7g5ek := -@
+DTC_FLAGS_at91-sam9x75_curiosity := -@
 dtb-$(CONFIG_SOC_AT91RM9200) += \
 	at91rm9200ek.dtb \
 	mpa1600.dtb
@@ -59,6 +60,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
 dtb-$(CONFIG_SOC_SAM9X60) += \
 	at91-sam9x60_curiosity.dtb \
 	at91-sam9x60ek.dtb
+dtb-$(CONFIG_SOC_SAM9X7) += \
+	at91-sam9x75_curiosity.dtb
 dtb-$(CONFIG_SOC_SAM_V7) += \
 	at91-kizbox2-2.dtb \
 	at91-kizbox3-hs.dtb \
diff --git a/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
new file mode 100644
index 000000000000..be37022d3d05
--- /dev/null
+++ b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
@@ -0,0 +1,309 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sam9x75_curiosity.dts - Device Tree file for Microchip SAM9X75 Curiosity board
+ *
+ * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
+ */
+/dts-v1/;
+#include "sam9x7.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Microchip SAM9X75 Curiosity";
+	compatible = "microchip,sam9x75-curiosity", "microchip,sam9x7", "atmel,at91sam9";
+
+	aliases {
+		i2c0 = &i2c6;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_key_gpio_default>;
+
+		button-user {
+			label = "USER";
+			gpios = <&pioC 9 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_0>;
+			wakeup-source;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_led_gpio_default>;
+
+		led-red {
+			label = "red";
+			gpios = <&pioC 19 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-green {
+			label = "green";
+			gpios = <&pioC 21 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-blue {
+			label = "blue";
+			gpios = <&pioC 20 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	memory@20000000 {
+		device_type = "memory";
+		reg = <0x20000000 0x10000000>;
+	};
+};
+
+&classd {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_classd>;
+	atmel,pwm-type = "diff";
+	atmel,non-overlap-time = <10>;
+	status = "okay";
+};
+
+&dbgu {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_dbgu>;
+	status = "okay";
+};
+
+&dma0 {
+	status = "okay";
+};
+
+&flx6 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+	status = "okay";
+};
+
+&i2c6 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flx6_default>;
+	i2c-analog-filter;
+	i2c-digital-filter;
+	i2c-digital-filter-width-ns = <35>;
+	status = "okay";
+
+	pmic@5b {
+		compatible = "microchip,mcp16502";
+		reg = <0x5b>;
+
+		regulators {
+			vdd_3v3: VDD_IO {
+				regulator-name = "VDD_IO";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-initial-mode = <2>;
+				regulator-allowed-modes = <2>, <4>;
+				regulator-always-on;
+
+				regulator-state-standby {
+					regulator-on-in-suspend;
+					regulator-mode = <4>;
+				};
+
+				regulator-state-mem {
+					regulator-mode = <4>;
+				};
+			};
+
+			vddioddr: VDD_DDR {
+				regulator-name = "VDD_DDR";
+				regulator-min-microvolt = <1283000>;
+				regulator-max-microvolt = <1450000>;
+				regulator-initial-mode = <2>;
+				regulator-allowed-modes = <2>, <4>;
+				regulator-always-on;
+
+				regulator-state-standby {
+					regulator-on-in-suspend;
+					regulator-mode = <4>;
+				};
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-mode = <4>;
+				};
+			};
+
+			vddcore: VDD_CORE {
+				regulator-name = "VDD_CORE";
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1210000>;
+				regulator-initial-mode = <2>;
+				regulator-allowed-modes = <2>, <4>;
+				regulator-always-on;
+
+				regulator-state-standby {
+					regulator-on-in-suspend;
+					regulator-mode = <4>;
+				};
+
+				regulator-state-mem {
+					regulator-mode = <4>;
+				};
+			};
+
+			vddcpu: VDD_OTHER {
+				regulator-name = "VDD_OTHER";
+				regulator-min-microvolt = <1700000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-initial-mode = <2>;
+				regulator-allowed-modes = <2>, <4>;
+				regulator-ramp-delay = <3125>;
+				regulator-always-on;
+
+				regulator-state-standby {
+					regulator-on-in-suspend;
+					regulator-mode = <4>;
+				};
+
+				regulator-state-mem {
+					regulator-mode = <4>;
+				};
+			};
+
+			vldo1: LDO1 {
+				regulator-name = "LDO1";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3700000>;
+				regulator-always-on;
+
+				regulator-state-standby {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vldo2: LDO2 {
+				regulator-name = "LDO2";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3700000>;
+
+				regulator-state-standby {
+					regulator-on-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2s {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2s_default>;
+	#sound-dai-cells = <0>;
+	status = "disabled";
+};
+
+&main_xtal {
+	clock-frequency = <24000000>;
+};
+
+&pinctrl {
+
+	classd {
+		pinctrl_classd: classd {
+			atmel,pins =
+				<AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_PULL_DOWN>;
+		};
+	};
+
+	dbgu {
+		pinctrl_dbgu: dbgu-0 {
+			atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				      AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+	};
+
+	flexcom {
+		pinctrl_flx6_default: flx6-twi {
+			atmel,pins =
+				<AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	gpio-keys {
+		pinctrl_key_gpio_default: key-gpio-default {
+			atmel,pins = <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+		};
+	};
+
+	i2s {
+		pinctrl_i2s_default: i2s {
+			atmel,pins =
+				<AT91_PIOB 26 AT91_PERIPH_D AT91_PINCTRL_NONE		/* I2SCK */
+				 AT91_PIOB 15 AT91_PERIPH_D AT91_PINCTRL_NONE		/* I2SWS */
+				 AT91_PIOB 16 AT91_PERIPH_D AT91_PINCTRL_NONE		/* I2SDIN */
+				 AT91_PIOB 17 AT91_PERIPH_D AT91_PINCTRL_NONE		/* I2SDOUT */
+				 AT91_PIOB 25 AT91_PERIPH_D AT91_PINCTRL_NONE>;		/* I2SMCK */
+		};
+	};
+
+	leds {
+		pinctrl_led_gpio_default: led-gpio-default {
+			atmel,pins = <AT91_PIOC 19 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+				      AT91_PIOC 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+				      AT91_PIOC 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+		};
+	};
+
+	sdmmc0 {
+		pinctrl_sdmmc0_default: sdmmc0 {
+			atmel,pins =
+				<AT91_PIOA 2 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_DIS)					/* PA2 CK  periph A with pullup */
+				 AT91_PIOA 1 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_DIS)		/* PA1 CMD periph A with pullup */
+				 AT91_PIOA 0 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_DIS)		/* PA0 DAT0 periph A */
+				 AT91_PIOA 3 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_DIS)		/* PA3 DAT1 periph A with pullup */
+				 AT91_PIOA 4 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_DIS)		/* PA4 DAT2 periph A with pullup */
+				 AT91_PIOA 5 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_DIS)>;	/* PA5 DAT3 periph A with pullup */
+		};
+	};
+
+}; /* pinctrl */
+
+&rtt {
+	atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdmmc0_default>;
+	cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	status = "okay";
+};
+
+&slow_xtal {
+	clock-frequency = <32768>;
+};
+
+&power_management {
+	debounce-delay-us = <976>;
+	status = "okay";
+
+	input@0 {
+		reg = <0>;
+	};
+};
+
+&trng {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
-- 
2.25.1


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Re: [PATCH v4 39/39] ARM: dts: at91: sam9x75_curiosity: add sam9x75 curiosity board

[claudiu beznea]

s/ARM: dts: at91/ARM: dts: microchip

in title.

On 23.02.2024 19:31, Varshini Rajendran wrote:
> Add device tree file for sam9x75 curiosity board.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
> Changes in v4:
> - Removed full node paths
> - Renamed Leds with color names
> - Corrected regulator node names
> - Added support for classd and i2s nodes and their corresponding
>   pinctrl nodes
> - Dropped USB nodes owing to the discussion here
> https://lore.kernel.org/linux-devicetree/CAL_JsqJ9PrX6fj-EbffeJce09MXs=B7t+KS_kOinxaRx38=WxA@mail.gmail.com/
> (Explained elaborately in the cover letter)
> - Updated the linux,code property with the necessary value
> ---
>  arch/arm/boot/dts/microchip/Makefile          |   3 +
>  .../dts/microchip/at91-sam9x75_curiosity.dts  | 309 ++++++++++++++++++
>  2 files changed, 312 insertions(+)
>  create mode 100644 arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
> 
> diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile
> index efde9546c8f4..5b3d518da319 100644
> --- a/arch/arm/boot/dts/microchip/Makefile
> +++ b/arch/arm/boot/dts/microchip/Makefile
> @@ -12,6 +12,7 @@ DTC_FLAGS_at91-sama5d3_eds := -@
>  DTC_FLAGS_at91-sama5d3_xplained := -@
>  DTC_FLAGS_at91-sama5d4_xplained := -@
>  DTC_FLAGS_at91-sama7g5ek := -@
> +DTC_FLAGS_at91-sam9x75_curiosity := -@

Keep it alphanumerically sorted, thus after sam9x60 entry.

>  dtb-$(CONFIG_SOC_AT91RM9200) += \
>  	at91rm9200ek.dtb \
>  	mpa1600.dtb
> @@ -59,6 +60,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
>  dtb-$(CONFIG_SOC_SAM9X60) += \
>  	at91-sam9x60_curiosity.dtb \
>  	at91-sam9x60ek.dtb
> +dtb-$(CONFIG_SOC_SAM9X7) += \
> +	at91-sam9x75_curiosity.dtb
>  dtb-$(CONFIG_SOC_SAM_V7) += \
>  	at91-kizbox2-2.dtb \
>  	at91-kizbox3-hs.dtb \
> diff --git a/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
> new file mode 100644
> index 000000000000..be37022d3d05
> --- /dev/null
> +++ b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
> @@ -0,0 +1,309 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * at91-sam9x75_curiosity.dts - Device Tree file for Microchip SAM9X75 Curiosity board
> + *
> + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
> + */
> +/dts-v1/;
> +#include "sam9x7.dtsi"
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> +	model = "Microchip SAM9X75 Curiosity";
> +	compatible = "microchip,sam9x75-curiosity", "microchip,sam9x7", "atmel,at91sam9";
> +
> +	aliases {
> +		i2c0 = &i2c6;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_key_gpio_default>;
> +
> +		button-user {
> +			label = "USER";
> +			gpios = <&pioC 9 GPIO_ACTIVE_LOW>;
> +			linux,code = <KEY_0>;
> +			wakeup-source;
> +		};
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_led_gpio_default>;
> +
> +		led-red {
> +			label = "red";
> +			gpios = <&pioC 19 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		led-green {
> +			label = "green";
> +			gpios = <&pioC 21 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		led-blue {
> +			label = "blue";
> +			gpios = <&pioC 20 GPIO_ACTIVE_HIGH>;
> +			linux,default-trigger = "heartbeat";
> +		};
> +	};
> +
> +	memory@20000000 {
> +		device_type = "memory";
> +		reg = <0x20000000 0x10000000>;
> +	};
> +};
> +
> +&classd {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_classd>;
> +	atmel,pwm-type = "diff";
> +	atmel,non-overlap-time = <10>;
> +	status = "okay";
> +};
> +
> +&dbgu {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_dbgu>;
> +	status = "okay";
> +};
> +
> +&dma0 {
> +	status = "okay";
> +};
> +
> +&flx6 {
> +	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
> +	status = "okay";
> +};
> +
> +&i2c6 {

I don't know if you got any review comments w/ regards to this in the
previous email but having flexcoms and inner node grouped together is
easier to follow (at least to me). e.g.:

> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_flx6_default>;
> +	i2c-analog-filter;
> +	i2c-digital-filter;
> +	i2c-digital-filter-width-ns = <35>;
> +	status = "okay";
> +
> +	pmic@5b {
> +		compatible = "microchip,mcp16502";
> +		reg = <0x5b>;
> +
> +		regulators {
> +			vdd_3v3: VDD_IO {
> +				regulator-name = "VDD_IO";
> +				regulator-min-microvolt = <3000000>;
> +				regulator-max-microvolt = <3600000>;

I can't find the schematics for this but these values here should reflect
the voltage that the board support not the ones that the PMIC itself
supports. Valid for all the other regulators.


> +				regulator-initial-mode = <2>;
> +				regulator-allowed-modes = <2>, <4>;
> +				regulator-always-on;
> +
> +				regulator-state-standby {
> +					regulator-on-in-suspend;
> +					regulator-mode = <4>;
> +				};
> +
> +				regulator-state-mem {
> +					regulator-mode = <4>;
> +				};
> +			};
> +
> +			vddioddr: VDD_DDR {
> +				regulator-name = "VDD_DDR";
> +				regulator-min-microvolt = <1283000>;
> +				regulator-max-microvolt = <1450000>;
> +				regulator-initial-mode = <2>;
> +				regulator-allowed-modes = <2>, <4>;
> +				regulator-always-on;
> +
> +				regulator-state-standby {
> +					regulator-on-in-suspend;
> +					regulator-mode = <4>;
> +				};
> +
> +				regulator-state-mem {
> +					regulator-on-in-suspend;
> +					regulator-mode = <4>;
> +				};
> +			};
> +
> +			vddcore: VDD_CORE {
> +				regulator-name = "VDD_CORE";
> +				regulator-min-microvolt = <500000>;
> +				regulator-max-microvolt = <1210000>;
> +				regulator-initial-mode = <2>;
> +				regulator-allowed-modes = <2>, <4>;
> +				regulator-always-on;
> +
> +				regulator-state-standby {
> +					regulator-on-in-suspend;
> +					regulator-mode = <4>;
> +				};
> +
> +				regulator-state-mem {
> +					regulator-mode = <4>;
> +				};
> +			};
> +
> +			vddcpu: VDD_OTHER {
> +				regulator-name = "VDD_OTHER";
> +				regulator-min-microvolt = <1700000>;
> +				regulator-max-microvolt = <3600000>;
> +				regulator-initial-mode = <2>;
> +				regulator-allowed-modes = <2>, <4>;
> +				regulator-ramp-delay = <3125>;
> +				regulator-always-on;
> +
> +				regulator-state-standby {
> +					regulator-on-in-suspend;
> +					regulator-mode = <4>;
> +				};
> +
> +				regulator-state-mem {
> +					regulator-mode = <4>;
> +				};
> +			};
> +
> +			vldo1: LDO1 {
> +				regulator-name = "LDO1";
> +				regulator-min-microvolt = <1200000>;
> +				regulator-max-microvolt = <3700000>;
> +				regulator-always-on;
> +
> +				regulator-state-standby {
> +					regulator-on-in-suspend;
> +				};
> +			};
> +
> +			vldo2: LDO2 {
> +				regulator-name = "LDO2";
> +				regulator-min-microvolt = <1200000>;
> +				regulator-max-microvolt = <3700000>;
> +
> +				regulator-state-standby {
> +					regulator-on-in-suspend;
> +				};
> +			};
> +		};
> +	};
> +};
> +
> +&i2s {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2s_default>;
> +	#sound-dai-cells = <0>;
> +	status = "disabled";

Any reason this is disabled?

> +};
> +
> +&main_xtal {
> +	clock-frequency = <24000000>;
> +};
> +
> +&pinctrl {
> +

This line could be removed.

> +	classd {
> +		pinctrl_classd: classd {
> +			atmel,pins =
> +				<AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_PULL_UP

Try to be compliant with coding style from here (valid everywhere):
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst#n167

> +				 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_PULL_DOWN>;
> +		};
> +	};
> +
> +	dbgu {
> +		pinctrl_dbgu: dbgu-0 {

usually pinctrl label is something like the following in Microchip AT91 DTSes:
pinctrl_<ip-name>_default and node name is <ip-name>-default.

Please use the same rule everywhere.

> +			atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
> +				      AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
> +		};
> +	};
> +
> +	flexcom {
> +		pinctrl_flx6_default: flx6-twi {
> +			atmel,pins =
> +				<AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
> +				 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
> +		};
> +	};
> +
> +	gpio-keys {
> +		pinctrl_key_gpio_default: key-gpio-default {
> +			atmel,pins = <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
> +		};
> +	};
> +
> +	i2s {
> +		pinctrl_i2s_default: i2s {
> +			atmel,pins =
> +				<AT91_PIOB 26 AT91_PERIPH_D AT91_PINCTRL_NONE		/* I2SCK */
> +				 AT91_PIOB 15 AT91_PERIPH_D AT91_PINCTRL_NONE		/* I2SWS */
> +				 AT91_PIOB 16 AT91_PERIPH_D AT91_PINCTRL_NONE		/* I2SDIN */
> +				 AT91_PIOB 17 AT91_PERIPH_D AT91_PINCTRL_NONE		/* I2SDOUT */
> +				 AT91_PIOB 25 AT91_PERIPH_D AT91_PINCTRL_NONE>;		/* I2SMCK */
> +		};
> +	};
> +
> +	leds {
> +		pinctrl_led_gpio_default: led-gpio-default {
> +			atmel,pins = <AT91_PIOC 19 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
> +				      AT91_PIOC 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
> +				      AT91_PIOC 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
> +		};
> +	};
> +
> +	sdmmc0 {
> +		pinctrl_sdmmc0_default: sdmmc0 {
> +			atmel,pins =
> +				<AT91_PIOA 2 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_DIS)					/* PA2 CK  periph A with pullup */
> +				 AT91_PIOA 1 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_DIS)		/* PA1 CMD periph A with pullup */
> +				 AT91_PIOA 0 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_DIS)		/* PA0 DAT0 periph A */
> +				 AT91_PIOA 3 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_DIS)		/* PA3 DAT1 periph A with pullup */
> +				 AT91_PIOA 4 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_DIS)		/* PA4 DAT2 periph A with pullup */
> +				 AT91_PIOA 5 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_DIS)>;	/* PA5 DAT3 periph A with pullup */
> +		};
> +	};
> +

You can remove this line

> +}; /* pinctrl */
> +
> +&rtt {
> +	atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
> +};
> +
> +&sdmmc0 {
> +	bus-width = <4>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_sdmmc0_default>;
> +	cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
> +	disable-wp;
> +	status = "okay";
> +};
> +
> +&slow_xtal {
> +	clock-frequency = <32768>;
> +};
> +
> +&power_management {
> +	debounce-delay-us = <976>;
> +	status = "okay";
> +
> +	input@0 {
> +		reg = <0>;
> +	};
> +};
> +
> +&trng {
> +	status = "okay";
> +};
> +
> +&watchdog {
> +	status = "okay";
> +};

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Re: [PATCH v4 39/39] ARM: dts: at91: sam9x75_curiosity: add sam9x75 curiosity board

[Varshini.Rajendran]

Hi Claudiu,

On 03/03/24 5:49 pm, claudiu beznea wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> s/ARM: dts: at91/ARM: dts: microchip
> 
> in title.
> 
> On 23.02.2024 19:31, Varshini Rajendran wrote:
>> Add device tree file for sam9x75 curiosity board.
>>
>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>> ---
>> Changes in v4:
>> - Removed full node paths
>> - Renamed Leds with color names
>> - Corrected regulator node names
>> - Added support for classd and i2s nodes and their corresponding
>>    pinctrl nodes
>> - Dropped USB nodes owing to the discussion here
>> https://lore.kernel.org/linux-devicetree/CAL_JsqJ9PrX6fj-EbffeJce09MXs=B7t+KS_kOinxaRx38=WxA@mail.gmail.com/
>> (Explained elaborately in the cover letter)
>> - Updated the linux,code property with the necessary value
>> ---
>>   arch/arm/boot/dts/microchip/Makefile          |   3 +
>>   .../dts/microchip/at91-sam9x75_curiosity.dts  | 309 ++++++++++++++++++
>>   2 files changed, 312 insertions(+)
>>   create mode 100644 arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
>>
>> diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile
>> index efde9546c8f4..5b3d518da319 100644
>> --- a/arch/arm/boot/dts/microchip/Makefile
>> +++ b/arch/arm/boot/dts/microchip/Makefile
>> @@ -12,6 +12,7 @@ DTC_FLAGS_at91-sama5d3_eds := -@
>>   DTC_FLAGS_at91-sama5d3_xplained := -@
>>   DTC_FLAGS_at91-sama5d4_xplained := -@
>>   DTC_FLAGS_at91-sama7g5ek := -@
>> +DTC_FLAGS_at91-sam9x75_curiosity := -@
> 
> Keep it alphanumerically sorted, thus after sam9x60 entry.
> 
>>   dtb-$(CONFIG_SOC_AT91RM9200) += \
>>        at91rm9200ek.dtb \
>>        mpa1600.dtb
>> @@ -59,6 +60,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
>>   dtb-$(CONFIG_SOC_SAM9X60) += \
>>        at91-sam9x60_curiosity.dtb \
>>        at91-sam9x60ek.dtb
>> +dtb-$(CONFIG_SOC_SAM9X7) += \
>> +     at91-sam9x75_curiosity.dtb
>>   dtb-$(CONFIG_SOC_SAM_V7) += \
>>        at91-kizbox2-2.dtb \
>>        at91-kizbox3-hs.dtb \
>> diff --git a/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
>> new file mode 100644
>> index 000000000000..be37022d3d05
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
>> @@ -0,0 +1,309 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * at91-sam9x75_curiosity.dts - Device Tree file for Microchip SAM9X75 Curiosity board
>> + *
>> + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
>> + *
>> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
>> + */
>> +/dts-v1/;
>> +#include "sam9x7.dtsi"
>> +#include <dt-bindings/input/input.h>
>> +
>> +/ {
>> +     model = "Microchip SAM9X75 Curiosity";
>> +     compatible = "microchip,sam9x75-curiosity", "microchip,sam9x7", "atmel,at91sam9";
>> +
>> +     aliases {
>> +             i2c0 = &i2c6;
>> +     };
>> +
>> +     chosen {
>> +             stdout-path = "serial0:115200n8";
>> +     };
>> +
>> +     gpio-keys {
>> +             compatible = "gpio-keys";
>> +             pinctrl-names = "default";
>> +             pinctrl-0 = <&pinctrl_key_gpio_default>;
>> +
>> +             button-user {
>> +                     label = "USER";
>> +                     gpios = <&pioC 9 GPIO_ACTIVE_LOW>;
>> +                     linux,code = <KEY_0>;
>> +                     wakeup-source;
>> +             };
>> +     };
>> +
>> +     leds {
>> +             compatible = "gpio-leds";
>> +             pinctrl-names = "default";
>> +             pinctrl-0 = <&pinctrl_led_gpio_default>;
>> +
>> +             led-red {
>> +                     label = "red";
>> +                     gpios = <&pioC 19 GPIO_ACTIVE_HIGH>;
>> +             };
>> +
>> +             led-green {
>> +                     label = "green";
>> +                     gpios = <&pioC 21 GPIO_ACTIVE_HIGH>;
>> +             };
>> +
>> +             led-blue {
>> +                     label = "blue";
>> +                     gpios = <&pioC 20 GPIO_ACTIVE_HIGH>;
>> +                     linux,default-trigger = "heartbeat";
>> +             };
>> +     };
>> +
>> +     memory@20000000 {
>> +             device_type = "memory";
>> +             reg = <0x20000000 0x10000000>;
>> +     };
>> +};
>> +
>> +&classd {
>> +     pinctrl-names = "default";
>> +     pinctrl-0 = <&pinctrl_classd>;
>> +     atmel,pwm-type = "diff";
>> +     atmel,non-overlap-time = <10>;
>> +     status = "okay";
>> +};
>> +
>> +&dbgu {
>> +     pinctrl-names = "default";
>> +     pinctrl-0 = <&pinctrl_dbgu>;
>> +     status = "okay";
>> +};
>> +
>> +&dma0 {
>> +     status = "okay";
>> +};
>> +
>> +&flx6 {
>> +     atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
>> +     status = "okay";
>> +};
>> +
>> +&i2c6 {
> 
> I don't know if you got any review comments w/ regards to this in the
> previous email but having flexcoms and inner node grouped together is
> easier to follow (at least to me). e.g.:
> 
Yes, I received a comment not to duplicate nodes. 
https://patchwork.kernel.org/project/linux-mmc/patch/20230623203056.689705-46-varshini.rajendran@microchip.com/

>> +     #address-cells = <1>;
>> +     #size-cells = <0>;
>> +     pinctrl-names = "default";
>> +     pinctrl-0 = <&pinctrl_flx6_default>;
>> +     i2c-analog-filter;
>> +     i2c-digital-filter;
>> +     i2c-digital-filter-width-ns = <35>;
>> +     status = "okay";
>> +
>> +     pmic@5b {
>> +             compatible = "microchip,mcp16502";
>> +             reg = <0x5b>;
>> +
>> +             regulators {
>> +                     vdd_3v3: VDD_IO {
>> +                             regulator-name = "VDD_IO";
>> +                             regulator-min-microvolt = <3000000>;
>> +                             regulator-max-microvolt = <3600000>;
> 
> I can't find the schematics for this but these values here should reflect
> the voltage that the board support not the ones that the PMIC itself
> supports. Valid for all the other regulators.
> 
Okay. I will double check this with hardware experts as well.
> 
>> +                             regulator-initial-mode = <2>;
>> +                             regulator-allowed-modes = <2>, <4>;
>> +                             regulator-always-on;
>> +
>> +                             regulator-state-standby {
>> +                                     regulator-on-in-suspend;
>> +                                     regulator-mode = <4>;
>> +                             };
>> +
>> +                             regulator-state-mem {
>> +                                     regulator-mode = <4>;
>> +                             };
>> +                     };
>> +
>> +                     vddioddr: VDD_DDR {
>> +                             regulator-name = "VDD_DDR";
>> +                             regulator-min-microvolt = <1283000>;
>> +                             regulator-max-microvolt = <1450000>;
>> +                             regulator-initial-mode = <2>;
>> +                             regulator-allowed-modes = <2>, <4>;
>> +                             regulator-always-on;
>> +
>> +                             regulator-state-standby {
>> +                                     regulator-on-in-suspend;
>> +                                     regulator-mode = <4>;
>> +                             };
>> +
>> +                             regulator-state-mem {
>> +                                     regulator-on-in-suspend;
>> +                                     regulator-mode = <4>;
>> +                             };
>> +                     };
>> +
>> +                     vddcore: VDD_CORE {
>> +                             regulator-name = "VDD_CORE";
>> +                             regulator-min-microvolt = <500000>;
>> +                             regulator-max-microvolt = <1210000>;
>> +                             regulator-initial-mode = <2>;
>> +                             regulator-allowed-modes = <2>, <4>;
>> +                             regulator-always-on;
>> +
>> +                             regulator-state-standby {
>> +                                     regulator-on-in-suspend;
>> +                                     regulator-mode = <4>;
>> +                             };
>> +
>> +                             regulator-state-mem {
>> +                                     regulator-mode = <4>;
>> +                             };
>> +                     };
>> +
>> +                     vddcpu: VDD_OTHER {
>> +                             regulator-name = "VDD_OTHER";
>> +                             regulator-min-microvolt = <1700000>;
>> +                             regulator-max-microvolt = <3600000>;
>> +                             regulator-initial-mode = <2>;
>> +                             regulator-allowed-modes = <2>, <4>;
>> +                             regulator-ramp-delay = <3125>;
>> +                             regulator-always-on;
>> +
>> +                             regulator-state-standby {
>> +                                     regulator-on-in-suspend;
>> +                                     regulator-mode = <4>;
>> +                             };
>> +
>> +                             regulator-state-mem {
>> +                                     regulator-mode = <4>;
>> +                             };
>> +                     };
>> +
>> +                     vldo1: LDO1 {
>> +                             regulator-name = "LDO1";
>> +                             regulator-min-microvolt = <1200000>;
>> +                             regulator-max-microvolt = <3700000>;
>> +                             regulator-always-on;
>> +
>> +                             regulator-state-standby {
>> +                                     regulator-on-in-suspend;
>> +                             };
>> +                     };
>> +
>> +                     vldo2: LDO2 {
>> +                             regulator-name = "LDO2";
>> +                             regulator-min-microvolt = <1200000>;
>> +                             regulator-max-microvolt = <3700000>;
>> +
>> +                             regulator-state-standby {
>> +                                     regulator-on-in-suspend;
>> +                             };
>> +                     };
>> +             };
>> +     };
>> +};
>> +
>> +&i2s {
>> +     pinctrl-names = "default";
>> +     pinctrl-0 = <&pinctrl_i2s_default>;
>> +     #sound-dai-cells = <0>;
>> +     status = "disabled";
> 
> Any reason this is disabled?
There is a conflict. My bad, I missed mentioning it since the other node 
support is not added yet. I will add it in the next version.
> 
>> +};
>> +
>> +&main_xtal {
>> +     clock-frequency = <24000000>;
>> +};
>> +
>> +&pinctrl {
>> +
> 
> This line could be removed.
> 
>> +     classd {
>> +             pinctrl_classd: classd {
>> +                     atmel,pins =
>> +                             <AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
> 
> Try to be compliant with coding style from here (valid everywhere):
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst#n167
> 
>> +                              AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_PULL_DOWN>;
>> +             };
>> +     };
>> +
>> +     dbgu {
>> +             pinctrl_dbgu: dbgu-0 {
> 
> usually pinctrl label is something like the following in Microchip AT91 DTSes:
> pinctrl_<ip-name>_default and node name is <ip-name>-default.
> 
> Please use the same rule everywhere.
> 
>> +                     atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
>> +                                   AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
>> +             };
>> +     };
>> +
>> +     flexcom {
>> +             pinctrl_flx6_default: flx6-twi {
>> +                     atmel,pins =
>> +                             <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
>> +                              AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
>> +             };
>> +     };
>> +
>> +     gpio-keys {
>> +             pinctrl_key_gpio_default: key-gpio-default {
>> +                     atmel,pins = <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
>> +             };
>> +     };
>> +
>> +     i2s {
>> +             pinctrl_i2s_default: i2s {
>> +                     atmel,pins =
>> +                             <AT91_PIOB 26 AT91_PERIPH_D AT91_PINCTRL_NONE           /* I2SCK */
>> +                              AT91_PIOB 15 AT91_PERIPH_D AT91_PINCTRL_NONE           /* I2SWS */
>> +                              AT91_PIOB 16 AT91_PERIPH_D AT91_PINCTRL_NONE           /* I2SDIN */
>> +                              AT91_PIOB 17 AT91_PERIPH_D AT91_PINCTRL_NONE           /* I2SDOUT */
>> +                              AT91_PIOB 25 AT91_PERIPH_D AT91_PINCTRL_NONE>;         /* I2SMCK */
>> +             };
>> +     };
>> +
>> +     leds {
>> +             pinctrl_led_gpio_default: led-gpio-default {
>> +                     atmel,pins = <AT91_PIOC 19 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
>> +                                   AT91_PIOC 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
>> +                                   AT91_PIOC 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
>> +             };
>> +     };
>> +
>> +     sdmmc0 {
>> +             pinctrl_sdmmc0_default: sdmmc0 {
>> +                     atmel,pins =
>> +                             <AT91_PIOA 2 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_DIS)                                 /* PA2 CK  periph A with pullup */
>> +                              AT91_PIOA 1 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_DIS)          /* PA1 CMD periph A with pullup */
>> +                              AT91_PIOA 0 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_DIS)          /* PA0 DAT0 periph A */
>> +                              AT91_PIOA 3 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_DIS)          /* PA3 DAT1 periph A with pullup */
>> +                              AT91_PIOA 4 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_DIS)          /* PA4 DAT2 periph A with pullup */
>> +                              AT91_PIOA 5 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_DIS)>;        /* PA5 DAT3 periph A with pullup */
>> +             };
>> +     };
>> +
> 
> You can remove this line
> 
>> +}; /* pinctrl */
>> +
>> +&rtt {
>> +     atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
>> +};
>> +
>> +&sdmmc0 {
>> +     bus-width = <4>;
>> +     pinctrl-names = "default";
>> +     pinctrl-0 = <&pinctrl_sdmmc0_default>;
>> +     cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
>> +     disable-wp;
>> +     status = "okay";
>> +};
>> +
>> +&slow_xtal {
>> +     clock-frequency = <32768>;
>> +};
>> +
>> +&power_management {
>> +     debounce-delay-us = <976>;
>> +     status = "okay";
>> +
>> +     input@0 {
>> +             reg = <0>;
>> +     };
>> +};
>> +
>> +&trng {
>> +     status = "okay";
>> +};
>> +
>> +&watchdog {
>> +     status = "okay";
>> +};

-- 
Thanks and Regards,
Varshini Rajendran.

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