[PATCH 00/25] Enable LT PHY

[PATCH 00/25] Enable LT PHY

[Suraj Kandpal]

From Xe3p we move on to LT PHY from CX0 PHY. This series implements
all the required enable/disable sequences, DP/HDMI PLL state calculation
using tables, HDMI Algorithm to calculate PLL state and the reverse Algo
where we use the state to calculate the portclock, new Vswing tables and
programming required to get everything up and running.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>

Suraj Kandpal (25):
  drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers
  drm/i915/cx0: Change register bit naming for powerdown values
  drm/i915/ltphy: Phy lane reset for LT Phy
  drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT Phy
  drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence
  drm/i915/ltphy: Read PHY_VDR_0_CONFIG register
  drm/i915/ltphy: Add LT Phy Programming recipe tables
  drm/i915/ltphy: Program the VDR PLL registers for LT PHY
  drm/i915/ltphy: Update the ltpll config table value for eDP
  drm/i915/ltphy: Enable SSC during port clock programming
  drm/i915/ltphy: Add function to calculate LT PHY port clock
  drm/i915/ltphy: Program the P2P Transaction flow for LT Phy
  drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL steps
  drm/i915/ltphy: Program the rest of the LT Phy Enable sequence
  drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequence
  drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences
  drm/i915/ddi: Define LT Phy Swing tables
  drm/i915/ltphy: Program LT Phy Voltage Swing
  drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence
  drm/i915/ltphy: Define the LT Phy state compare function
  drm/i915/ltphy: Define function to readout LT Phy PLL state
  drm/i915/ltphy: Define LT PHY PLL state verify function
  drm/i915/display: Aux Enable and Display powerwell timeouts
  drm/i915/ltphy: Modify the step that need to by skipped
  drm/i915/ltphy: Implement HDMI Algo for Pll state

 drivers/gpu/drm/i915/Makefile                 |    1 +
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |   64 +-
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   22 +
 .../gpu/drm/i915/display/intel_cx0_phy_regs.h |   15 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |   34 +-
 .../drm/i915/display/intel_ddi_buf_trans.c    |   81 +-
 .../drm/i915/display/intel_ddi_buf_trans.h    |    9 +
 drivers/gpu/drm/i915/display/intel_display.c  |   33 +-
 .../i915/display/intel_display_power_well.c   |   23 +-
 drivers/gpu/drm/i915/display/intel_dpll.c     |   31 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   11 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 2303 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |   47 +
 .../gpu/drm/i915/display/intel_lt_phy_regs.h  |   78 +
 .../drm/i915/display/intel_modeset_verify.c   |    2 +
 drivers/gpu/drm/xe/Makefile                   |    1 +
 16 files changed, 2708 insertions(+), 47 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_lt_phy.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_lt_phy.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_lt_phy_regs.h

-- 
2.34.1

[PATCH 01/25] drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers

[Suraj Kandpal]

Add LT Phy related VDR and pipe registers into its own new file.

Bspec: 74500
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../gpu/drm/i915/display/intel_lt_phy_regs.h  | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/intel_lt_phy_regs.h

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
new file mode 100644
index 000000000000..499acb1975d1
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_LT_PHY_REGS_H__
+#define __INTEL_LT_PHY_REGS_H__
+
+#include "i915_reg_defs.h"
+#include "intel_display_limits.h"
+
+/* LT Phy Vendor Register */
+#define LT_PHY_VDR_0_CONFIG	0xC02
+#define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
+#define LT_PHY_VDR_1_CONFIG	0xC03
+#define  LT_PHY_VDR_RATE_ENCODING_MASK	REG_GENMASK8(6, 3)
+#define  LT_PHY_VDR_MODE_ENCODING_MASK	REG_GENMASK8(2, 0)
+#define LT_PHY_VDR_2_CONFIG	0xCC3
+
+#define LT_PHY_VDR_X_ADDR_MSB(idx)	(0xC04 + 0x6 * (idx))
+#define LT_PHY_VDR_X_ADDR_LSB(idx)	(0xC05 + 0x6 * (idx))
+
+#define LT_PHY_VDR_X_DATAY(idx, y)	((0xC06 + (3 - (y))) + 0x6 * (idx))
+
+#define LT_PHY_RATE_UPDATE		0xCC4
+
+#endif /* __INTEL_LT_PHY_REGS_H__ */
-- 
2.34.1

Re: [PATCH 01/25] drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers

[Jani Nikula]

On Wed, 15 Oct 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Add LT Phy related VDR and pipe registers into its own new file.
>
> Bspec: 74500
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_lt_phy_regs.h  | 27 +++++++++++++++++++
>  1 file changed, 27 insertions(+)
>  create mode 100644 drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> new file mode 100644
> index 000000000000..499acb1975d1
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> @@ -0,0 +1,27 @@
> +/* SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __INTEL_LT_PHY_REGS_H__
> +#define __INTEL_LT_PHY_REGS_H__
> +
> +#include "i915_reg_defs.h"
> +#include "intel_display_limits.h"

Unnecessary.

> +
> +/* LT Phy Vendor Register */
> +#define LT_PHY_VDR_0_CONFIG	0xC02
> +#define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
> +#define LT_PHY_VDR_1_CONFIG	0xC03
> +#define  LT_PHY_VDR_RATE_ENCODING_MASK	REG_GENMASK8(6, 3)
> +#define  LT_PHY_VDR_MODE_ENCODING_MASK	REG_GENMASK8(2, 0)
> +#define LT_PHY_VDR_2_CONFIG	0xCC3
> +
> +#define LT_PHY_VDR_X_ADDR_MSB(idx)	(0xC04 + 0x6 * (idx))
> +#define LT_PHY_VDR_X_ADDR_LSB(idx)	(0xC05 + 0x6 * (idx))
> +
> +#define LT_PHY_VDR_X_DATAY(idx, y)	((0xC06 + (3 - (y))) + 0x6 * (idx))
> +
> +#define LT_PHY_RATE_UPDATE		0xCC4
> +
> +#endif /* __INTEL_LT_PHY_REGS_H__ */

-- 
Jani Nikula, Intel

RE: [PATCH 01/25] drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers

[Kandpal, Suraj]

> Subject: Re: [PATCH 01/25] drm/i915/ltphy: Add LT Phy related VDR and Pipe
> Registers
> 
> On Wed, 15 Oct 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > Add LT Phy related VDR and pipe registers into its own new file.
> >
> > Bspec: 74500
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >  .../gpu/drm/i915/display/intel_lt_phy_regs.h  | 27
> > +++++++++++++++++++
> >  1 file changed, 27 insertions(+)
> >  create mode 100644 drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > new file mode 100644
> > index 000000000000..499acb1975d1
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > @@ -0,0 +1,27 @@
> > +/* SPDX-License-Identifier: MIT
> > + *
> > + * Copyright © 2025 Intel Corporation  */
> > +
> > +#ifndef __INTEL_LT_PHY_REGS_H__
> > +#define __INTEL_LT_PHY_REGS_H__
> > +
> > +#include "i915_reg_defs.h"
> > +#include "intel_display_limits.h"
> 
> Unnecessary.

Sure will remove it

Regards,
Suraj Kandpal

> 
> > +
> > +/* LT Phy Vendor Register */
> > +#define LT_PHY_VDR_0_CONFIG	0xC02
> > +#define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
> > +#define LT_PHY_VDR_1_CONFIG	0xC03
> > +#define  LT_PHY_VDR_RATE_ENCODING_MASK	REG_GENMASK8(6, 3)
> > +#define  LT_PHY_VDR_MODE_ENCODING_MASK	REG_GENMASK8(2, 0)
> > +#define LT_PHY_VDR_2_CONFIG	0xCC3
> > +
> > +#define LT_PHY_VDR_X_ADDR_MSB(idx)	(0xC04 + 0x6 * (idx))
> > +#define LT_PHY_VDR_X_ADDR_LSB(idx)	(0xC05 + 0x6 * (idx))
> > +
> > +#define LT_PHY_VDR_X_DATAY(idx, y)	((0xC06 + (3 - (y))) + 0x6 * (idx))
> > +
> > +#define LT_PHY_RATE_UPDATE		0xCC4
> > +
> > +#endif /* __INTEL_LT_PHY_REGS_H__ */
> 
> --
> Jani Nikula, Intel

Re: [PATCH 01/25] drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers

[Murthy, Arun R]

On 15-10-2025 09:37, Suraj Kandpal wrote:
> Add LT Phy related VDR and pipe registers into its own new file.
>
> Bspec: 74500
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>   .../gpu/drm/i915/display/intel_lt_phy_regs.h  | 27 +++++++++++++++++++
>   1 file changed, 27 insertions(+)
>   create mode 100644 drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> new file mode 100644
> index 000000000000..499acb1975d1
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> @@ -0,0 +1,27 @@
> +/* SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __INTEL_LT_PHY_REGS_H__
> +#define __INTEL_LT_PHY_REGS_H__
> +
> +#include "i915_reg_defs.h"
> +#include "intel_display_limits.h"
> +
This may not be required!
Upon removal of this

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------
> +/* LT Phy Vendor Register */
> +#define LT_PHY_VDR_0_CONFIG	0xC02
> +#define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
> +#define LT_PHY_VDR_1_CONFIG	0xC03
> +#define  LT_PHY_VDR_RATE_ENCODING_MASK	REG_GENMASK8(6, 3)
> +#define  LT_PHY_VDR_MODE_ENCODING_MASK	REG_GENMASK8(2, 0)
> +#define LT_PHY_VDR_2_CONFIG	0xCC3
> +
> +#define LT_PHY_VDR_X_ADDR_MSB(idx)	(0xC04 + 0x6 * (idx))
> +#define LT_PHY_VDR_X_ADDR_LSB(idx)	(0xC05 + 0x6 * (idx))
> +
> +#define LT_PHY_VDR_X_DATAY(idx, y)	((0xC06 + (3 - (y))) + 0x6 * (idx))
> +
> +#define LT_PHY_RATE_UPDATE		0xCC4
> +
> +#endif /* __INTEL_LT_PHY_REGS_H__ */

[PATCH 02/25] drm/i915/cx0: Change register bit naming for powerdown values

[Suraj Kandpal]

Change the register bit naming for powerdown values from CX0 to
XELPDP so that it can be used with LT Phy too.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c      | 14 +++++++-------
 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 10 +++++-----
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index a2d2cecf7121..6d9ebc8717ba 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2850,11 +2850,11 @@ static void intel_cx0_setup_powerdown(struct intel_encoder *encoder)
 
 	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
 		     XELPDP_POWER_STATE_READY_MASK,
-		     XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
+		     XELPDP_POWER_STATE_READY(XELPDP_P2_STATE_READY));
 	intel_de_rmw(display, XELPDP_PORT_BUF_CTL3(display, port),
 		     XELPDP_POWER_STATE_ACTIVE_MASK |
 		     XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
-		     XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
+		     XELPDP_POWER_STATE_ACTIVE(XELPDP_P0_STATE_ACTIVE) |
 		     XELPDP_PLL_LANE_STAGGERING_DELAY(0));
 }
 
@@ -2927,7 +2927,7 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
 			 phy_name(phy), XELPDP_REFCLK_ENABLE_TIMEOUT_US);
 
 	intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
-					    CX0_P2_STATE_RESET);
+					    XELPDP_P2_STATE_RESET);
 	intel_cx0_setup_powerdown(encoder);
 
 	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset, 0);
@@ -3032,7 +3032,7 @@ static void __intel_cx0pll_enable(struct intel_encoder *encoder,
 	 * TODO: For DP alt mode use only one lane.
 	 */
 	intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
-					    CX0_P2_STATE_READY);
+					    XELPDP_P2_STATE_READY);
 
 	/*
 	 * 4. Program PORT_MSGBUS_TIMER register's Message Bus Timer field to 0xA000.
@@ -3273,13 +3273,13 @@ static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)
 	struct intel_display *display = to_intel_display(encoder);
 
 	if (intel_encoder_is_c10phy(encoder))
-		return CX0_P2PG_STATE_DISABLE;
+		return XELPDP_P2PG_STATE_DISABLE;
 
 	if ((display->platform.battlemage && encoder->port == PORT_A) ||
 	    (DISPLAY_VER(display) >= 30 && encoder->type == INTEL_OUTPUT_EDP))
-		return CX0_P2PG_STATE_DISABLE;
+		return XELPDP_P2PG_STATE_DISABLE;
 
-	return CX0_P4PG_STATE_DISABLE;
+	return XELPDP_P4PG_STATE_DISABLE;
 }
 
 static void intel_cx0pll_disable(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 77eae1d845f7..18b91c23d547 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -149,11 +149,11 @@
 #define   XELPDP_PLL_LANE_STAGGERING_DELAY(val)		REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)
 #define   XELPDP_POWER_STATE_ACTIVE_MASK		REG_GENMASK(3, 0)
 #define   XELPDP_POWER_STATE_ACTIVE(val)		REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)
-#define   CX0_P0_STATE_ACTIVE				0x0
-#define   CX0_P2_STATE_READY				0x2
-#define   CX0_P2PG_STATE_DISABLE			0x9
-#define   CX0_P4PG_STATE_DISABLE			0xC
-#define   CX0_P2_STATE_RESET				0x2
+#define   XELPDP_P0_STATE_ACTIVE			0x0
+#define   XELPDP_P2_STATE_READY				0x2
+#define   XELPDP_P2PG_STATE_DISABLE			0x9
+#define   XELPDP_P4PG_STATE_DISABLE			0xC
+#define   XELPDP_P2_STATE_RESET				0x2
 
 #define _XELPDP_PORT_MSGBUS_TIMER_LN0_A			0x640d8
 #define _XELPDP_PORT_MSGBUS_TIMER_LN0_B			0x641d8
-- 
2.34.1

Re: [PATCH 02/25] drm/i915/cx0: Change register bit naming for powerdown values

[Murthy, Arun R]

On 15-10-2025 09:37, Suraj Kandpal wrote:
> Change the register bit naming for powerdown values from CX0 to
> XELPDP so that it can be used with LT Phy too.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>   drivers/gpu/drm/i915/display/intel_cx0_phy.c      | 14 +++++++-------
>   drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 10 +++++-----
>   2 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index a2d2cecf7121..6d9ebc8717ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2850,11 +2850,11 @@ static void intel_cx0_setup_powerdown(struct intel_encoder *encoder)
>   
>   	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
>   		     XELPDP_POWER_STATE_READY_MASK,
> -		     XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
> +		     XELPDP_POWER_STATE_READY(XELPDP_P2_STATE_READY));
>   	intel_de_rmw(display, XELPDP_PORT_BUF_CTL3(display, port),
>   		     XELPDP_POWER_STATE_ACTIVE_MASK |
>   		     XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
> -		     XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
> +		     XELPDP_POWER_STATE_ACTIVE(XELPDP_P0_STATE_ACTIVE) |
>   		     XELPDP_PLL_LANE_STAGGERING_DELAY(0));
>   }
>   
> @@ -2927,7 +2927,7 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
>   			 phy_name(phy), XELPDP_REFCLK_ENABLE_TIMEOUT_US);
>   
>   	intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
> -					    CX0_P2_STATE_RESET);
> +					    XELPDP_P2_STATE_RESET);
>   	intel_cx0_setup_powerdown(encoder);
>   
>   	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset, 0);
> @@ -3032,7 +3032,7 @@ static void __intel_cx0pll_enable(struct intel_encoder *encoder,
>   	 * TODO: For DP alt mode use only one lane.
>   	 */
>   	intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
> -					    CX0_P2_STATE_READY);
> +					    XELPDP_P2_STATE_READY);
>   
>   	/*
>   	 * 4. Program PORT_MSGBUS_TIMER register's Message Bus Timer field to 0xA000.
> @@ -3273,13 +3273,13 @@ static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)
>   	struct intel_display *display = to_intel_display(encoder);
>   
>   	if (intel_encoder_is_c10phy(encoder))
> -		return CX0_P2PG_STATE_DISABLE;
> +		return XELPDP_P2PG_STATE_DISABLE;
>   
>   	if ((display->platform.battlemage && encoder->port == PORT_A) ||
>   	    (DISPLAY_VER(display) >= 30 && encoder->type == INTEL_OUTPUT_EDP))
> -		return CX0_P2PG_STATE_DISABLE;
> +		return XELPDP_P2PG_STATE_DISABLE;
>   
> -	return CX0_P4PG_STATE_DISABLE;
> +	return XELPDP_P4PG_STATE_DISABLE;
>   }
>   
>   static void intel_cx0pll_disable(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 77eae1d845f7..18b91c23d547 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -149,11 +149,11 @@
>   #define   XELPDP_PLL_LANE_STAGGERING_DELAY(val)		REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)
>   #define   XELPDP_POWER_STATE_ACTIVE_MASK		REG_GENMASK(3, 0)
>   #define   XELPDP_POWER_STATE_ACTIVE(val)		REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)
> -#define   CX0_P0_STATE_ACTIVE				0x0
> -#define   CX0_P2_STATE_READY				0x2
> -#define   CX0_P2PG_STATE_DISABLE			0x9
> -#define   CX0_P4PG_STATE_DISABLE			0xC
> -#define   CX0_P2_STATE_RESET				0x2
> +#define   XELPDP_P0_STATE_ACTIVE			0x0
> +#define   XELPDP_P2_STATE_READY				0x2
> +#define   XELPDP_P2PG_STATE_DISABLE			0x9
> +#define   XELPDP_P4PG_STATE_DISABLE			0xC
> +#define   XELPDP_P2_STATE_RESET				0x2
>   
>   #define _XELPDP_PORT_MSGBUS_TIMER_LN0_A			0x640d8
>   #define _XELPDP_PORT_MSGBUS_TIMER_LN0_B			0x641d8

[PATCH 03/25] drm/i915/ltphy: Phy lane reset for LT Phy

[Suraj Kandpal]

Define function to bring phy lane out of reset for LT Phy and the
corresponding pre-requisite steps before we follow the steps for
Phy lane reset. Also create a skeleton of LT PHY PLL enable sequence
function in which we can place this function

Bspec: 77449, 74749, 74499, 74495, 68960
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |   2 +-
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   2 +
 .../gpu/drm/i915/display/intel_cx0_phy_regs.h |   4 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 159 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |  17 ++
 .../gpu/drm/i915/display/intel_lt_phy_regs.h  |  17 ++
 drivers/gpu/drm/xe/Makefile                   |   1 +
 8 files changed, 202 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_lt_phy.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_lt_phy.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6d7800e25e55..33836829d2c0 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -352,6 +352,7 @@ i915-y += \
 	display/intel_gmbus.o \
 	display/intel_hdmi.o \
 	display/intel_lspcon.o \
+	display/intel_lt_phy.o \
 	display/intel_lvds.o \
 	display/intel_panel.o \
 	display/intel_pfit.o \
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6d9ebc8717ba..db2b05521c62 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2843,7 +2843,7 @@ static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
 			 phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
 }
 
-static void intel_cx0_setup_powerdown(struct intel_encoder *encoder)
+void intel_cx0_setup_powerdown(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	enum port port = encoder->port;
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index c5a7b529955b..c92026fe7b8f 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -41,6 +41,8 @@ bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
 				   const struct intel_cx0pll_state *b);
 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 				     const struct intel_crtc_state *crtc_state);
+int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
+void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
 void intel_cx0_pll_power_save_wa(struct intel_display *display);
 void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 18b91c23d547..114f6b2113db 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -104,6 +104,8 @@
 #define   XELPDP_PORT_BUF_PORT_DATA_20BIT		REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 1)
 #define   XELPDP_PORT_BUF_PORT_DATA_40BIT		REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2)
 #define   XELPDP_PORT_REVERSAL				REG_BIT(16)
+#define   XE3PLPDP_PHY_MODE_MASK			REG_GENMASK(15, 12)
+#define   XE3PLPDP_PHY_MODE_DP				REG_FIELD_PREP(XE3PLPDP_PHY_MODE_MASK, 0x3)
 #define   XELPDP_PORT_BUF_IO_SELECT_TBT			REG_BIT(11)
 #define   XELPDP_PORT_BUF_PHY_IDLE			REG_BIT(7)
 #define   XELPDP_TC_PHY_OWNERSHIP			REG_BIT(6)
@@ -124,6 +126,7 @@
 	 _XELPDP_PORT_BUF_CTL2(port))
 #define   XELPDP_LANE_PIPE_RESET(lane)			_PICK(lane, REG_BIT(31), REG_BIT(30))
 #define   XELPDP_LANE_PHY_CURRENT_STATUS(lane)		_PICK(lane, REG_BIT(29), REG_BIT(28))
+#define   XE3PLPDP_LANE_PHY_PULSE_STATUS(lane)		_PICK(lane, REG_BIT(27), REG_BIT(26))
 #define   XELPDP_LANE_POWERDOWN_UPDATE(lane)		_PICK(lane, REG_BIT(25), REG_BIT(24))
 #define   _XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK	REG_GENMASK(23, 20)
 #define   _XELPDP_LANE0_POWERDOWN_NEW_STATE(val)	REG_FIELD_PREP(_XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK, val)
@@ -151,6 +154,7 @@
 #define   XELPDP_POWER_STATE_ACTIVE(val)		REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)
 #define   XELPDP_P0_STATE_ACTIVE			0x0
 #define   XELPDP_P2_STATE_READY				0x2
+#define   XE3PLPD_P4_STATE_DISABLE			0x4
 #define   XELPDP_P2PG_STATE_DISABLE			0x9
 #define   XELPDP_P4PG_STATE_DISABLE			0xC
 #define   XELPDP_P2_STATE_RESET				0x2
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
new file mode 100644
index 000000000000..c65333cc9494
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include <drm/drm_print.h>
+
+#include "i915_reg.h"
+#include "intel_cx0_phy.h"
+#include "intel_cx0_phy_regs.h"
+#include "intel_de.h"
+#include "intel_display.h"
+#include "intel_display_types.h"
+#include "intel_lt_phy.h"
+#include "intel_lt_phy_regs.h"
+#include "intel_tc.h"
+
+#define INTEL_LT_PHY_LANE0		BIT(0)
+#define INTEL_LT_PHY_LANE1		BIT(1)
+#define INTEL_LT_PHY_BOTH_LANES		(INTEL_LT_PHY_LANE1 |\
+					 INTEL_LT_PHY_LANE0)
+
+static u8 intel_lt_phy_get_owned_lane_mask(struct intel_encoder *encoder)
+{
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+	if (!intel_tc_port_in_dp_alt_mode(dig_port))
+		return INTEL_LT_PHY_BOTH_LANES;
+
+	return intel_tc_port_max_lane_count(dig_port) > 2
+		? INTEL_LT_PHY_BOTH_LANES : INTEL_LT_PHY_LANE0;
+}
+
+static void
+intel_lt_phy_setup_powerdown(struct intel_encoder *encoder, u8 lane_count)
+{
+	/*
+	 * The new PORT_BUF_CTL6 stuff for dc5 entry and exit needs to be handled
+	 * by dmc firmware not explicitly mentioned in Bspec. This leaves this
+	 * function as a wrapper only but keeping it expecting future changes.
+	 */
+	intel_cx0_setup_powerdown(encoder);
+}
+
+static void
+intel_lt_phy_lane_reset(struct intel_encoder *encoder,
+			u8 lane_count)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	enum port port = encoder->port;
+	enum phy phy = intel_encoder_to_phy(encoder);
+	u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
+	u32 lane_pipe_reset = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES
+				? XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1)
+				: XELPDP_LANE_PIPE_RESET(0);
+	u32 lane_phy_current_status = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES
+					? (XELPDP_LANE_PHY_CURRENT_STATUS(0) |
+					   XELPDP_LANE_PHY_CURRENT_STATUS(1))
+					: XELPDP_LANE_PHY_CURRENT_STATUS(0);
+	u32 lane_phy_pulse_status = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES
+					? (XE3PLPDP_LANE_PHY_PULSE_STATUS(0) |
+					   XE3PLPDP_LANE_PHY_PULSE_STATUS(1))
+					: XE3PLPDP_LANE_PHY_PULSE_STATUS(0);
+
+	intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port),
+		     XE3PLPD_MACCLK_RATE_MASK, XE3PLPD_MACCLK_RATE_DEF);
+
+	intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),
+		     XE3PLPDP_PHY_MODE_MASK, XE3PLPDP_PHY_MODE_DP);
+
+	intel_lt_phy_setup_powerdown(encoder, lane_count);
+
+	intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port),
+		     XE3PLPD_MACCLK_RESET_0, 0);
+
+	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
+		     XELPDP_LANE_PCLK_PLL_REQUEST(0),
+		     XELPDP_LANE_PCLK_PLL_REQUEST(0));
+
+	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
+				 XELPDP_LANE_PCLK_PLL_ACK(0),
+				 XELPDP_LANE_PCLK_PLL_ACK(0),
+				 XE3PLPD_MACCLK_TURNON_LATENCY_US,
+				 XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
+		drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack not done after %dus.\n",
+			 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
+
+	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
+		     XELPDP_FORWARD_CLOCK_UNGATE,
+		     XELPDP_FORWARD_CLOCK_UNGATE);
+
+	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
+		     lane_pipe_reset | lane_phy_pulse_status, 0);
+
+	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
+				 lane_phy_current_status, 0,
+				 XE3PLPD_RESET_END_LATENCY_US, 2, NULL))
+		drm_warn(display->drm,
+			 "PHY %c failed to bring out of Lane reset after %dus.\n",
+			 phy_name(phy), XE3PLPD_RESET_END_LATENCY_US);
+
+	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
+				 lane_phy_pulse_status, lane_phy_pulse_status,
+				 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))
+		drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
+			 phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
+
+	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_phy_pulse_status, 0);
+}
+
+void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state)
+{
+	/* 1. Enable MacCLK at default 162 MHz frequency. */
+	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
+
+	/* 2. Program PORT_CLOCK_CTL register to configure clock muxes, gating, and SSC. */
+	/* 3. Change owned PHY lanes power to Ready state. */
+	/*
+	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,
+	 * encoded rate and encoded mode.
+	 */
+	/*
+	 * 5. Program the PHY internal PLL registers over PHY message bus for the desired
+	 * frequency and protocol type
+	 */
+	/* 6. Use the P2P transaction flow */
+	/*
+	 * 6.1. Set the PHY VDR register 0xCC4[Rate Control VDR Update] = 1 over PHY message
+	 * bus for Owned PHY Lanes.
+	 */
+	/*
+	 * 6.2. Poll for P2P Transaction Ready = "1" and read the MAC message bus VDR register
+	 * at offset 0xC00 for Owned PHY Lanes.
+	 */
+	/* 6.3. Clear P2P transaction Ready bit. */
+	/* 7. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0. */
+	/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
+	/*
+	 * 9. Follow the Display Voltage Frequency Switching - Sequence Before Frequency Change.
+	 * We handle this step in bxt_set_cdclk()
+	 */
+	/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
+	/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
+	/* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */
+	/* 13. Ungate the forward clock by setting PORT_CLOCK_CTL[Forward Clock Ungate] = 1. */
+	/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
+	/*
+	 * 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over PHY message bus for
+	 * Owned PHY Lanes.
+	 */
+	/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
+	/* 17. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
+	/*
+	 * 18. Follow the Display Voltage Frequency Switching - Sequence After Frequency Change.
+	 * We handle this step in bxt_set_cdclk()
+	 */
+	/* 19. Move the PHY powerdown state to Active and program to enable/disable transmitters */
+}
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
new file mode 100644
index 000000000000..bd3ff3007e1d
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_LT_PHY_H__
+#define __INTEL_LT_PHY_H__
+
+#include <linux/types.h>
+
+struct intel_encoder;
+struct intel_crtc_state;
+
+void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state);
+
+#endif /* __INTEL_LT_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
index 499acb1975d1..a4aa2a3e0425 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
@@ -9,6 +9,12 @@
 #include "i915_reg_defs.h"
 #include "intel_display_limits.h"
 
+#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
+#define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
+#define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
+#define XE3PLPD_RESET_START_LATENCY_US	10
+#define XE3PLPD_RESET_END_LATENCY_US	200
+
 /* LT Phy Vendor Register */
 #define LT_PHY_VDR_0_CONFIG	0xC02
 #define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
@@ -24,4 +30,15 @@
 
 #define LT_PHY_RATE_UPDATE		0xCC4
 
+#define _XE3PLPD_PORT_BUF_CTL5(idx)	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
+								 _XELPDP_PORT_BUF_CTL1_LN0_A, \
+								 _XELPDP_PORT_BUF_CTL1_LN0_B, \
+								 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
+								 _XELPDP_PORT_BUF_CTL1_LN0_USBC2) \
+								+ 0x34)
+#define XE3PLPD_PORT_BUF_CTL5(port)	_XE3PLPD_PORT_BUF_CTL5(__xe2lpd_port_idx(port))
+#define  XE3PLPD_MACCLK_RESET_0		REG_BIT(11)
+#define  XE3PLPD_MACCLK_RATE_MASK	REG_GENMASK(4, 0)
+#define  XE3PLPD_MACCLK_RATE_DEF	REG_FIELD_PREP(XE3PLPD_MACCLK_RATE_MASK, 0x1F)
+
 #endif /* __INTEL_LT_PHY_REGS_H__ */
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 84321fad3265..314aeea0f1e3 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -291,6 +291,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
 	i915-display/intel_hti.o \
 	i915-display/intel_link_bw.o \
 	i915-display/intel_lspcon.o \
+	i915-display/intel_lt_phy.o \
 	i915-display/intel_modeset_lock.o \
 	i915-display/intel_modeset_setup.o \
 	i915-display/intel_modeset_verify.o \
-- 
2.34.1

Re: [PATCH 03/25] drm/i915/ltphy: Phy lane reset for LT Phy

[Murthy, Arun R]

On 15-10-2025 09:37, Suraj Kandpal wrote:
> Define function to bring phy lane out of reset for LT Phy and the
> corresponding pre-requisite steps before we follow the steps for
> Phy lane reset. Also create a skeleton of LT PHY PLL enable sequence
> function in which we can place this function
>
> Bspec: 77449, 74749, 74499, 74495, 68960
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>   drivers/gpu/drm/i915/Makefile                 |   1 +
>   drivers/gpu/drm/i915/display/intel_cx0_phy.c  |   2 +-
>   drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   2 +
>   .../gpu/drm/i915/display/intel_cx0_phy_regs.h |   4 +
>   drivers/gpu/drm/i915/display/intel_lt_phy.c   | 159 ++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_lt_phy.h   |  17 ++
>   .../gpu/drm/i915/display/intel_lt_phy_regs.h  |  17 ++
>   drivers/gpu/drm/xe/Makefile                   |   1 +
>   8 files changed, 202 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/gpu/drm/i915/display/intel_lt_phy.c
>   create mode 100644 drivers/gpu/drm/i915/display/intel_lt_phy.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 6d7800e25e55..33836829d2c0 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -352,6 +352,7 @@ i915-y += \
>   	display/intel_gmbus.o \
>   	display/intel_hdmi.o \
>   	display/intel_lspcon.o \
> +	display/intel_lt_phy.o \
>   	display/intel_lvds.o \
>   	display/intel_panel.o \
>   	display/intel_pfit.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 6d9ebc8717ba..db2b05521c62 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2843,7 +2843,7 @@ static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
>   			 phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
>   }
>   
> -static void intel_cx0_setup_powerdown(struct intel_encoder *encoder)
> +void intel_cx0_setup_powerdown(struct intel_encoder *encoder)
>   {
>   	struct intel_display *display = to_intel_display(encoder);
>   	enum port port = encoder->port;
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index c5a7b529955b..c92026fe7b8f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -41,6 +41,8 @@ bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
>   				   const struct intel_cx0pll_state *b);
>   void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
>   				     const struct intel_crtc_state *crtc_state);
> +int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
> +void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
>   int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
>   void intel_cx0_pll_power_save_wa(struct intel_display *display);
>   void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 18b91c23d547..114f6b2113db 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -104,6 +104,8 @@
>   #define   XELPDP_PORT_BUF_PORT_DATA_20BIT		REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 1)
>   #define   XELPDP_PORT_BUF_PORT_DATA_40BIT		REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2)
>   #define   XELPDP_PORT_REVERSAL				REG_BIT(16)
> +#define   XE3PLPDP_PHY_MODE_MASK			REG_GENMASK(15, 12)
> +#define   XE3PLPDP_PHY_MODE_DP				REG_FIELD_PREP(XE3PLPDP_PHY_MODE_MASK, 0x3)
>   #define   XELPDP_PORT_BUF_IO_SELECT_TBT			REG_BIT(11)
>   #define   XELPDP_PORT_BUF_PHY_IDLE			REG_BIT(7)
>   #define   XELPDP_TC_PHY_OWNERSHIP			REG_BIT(6)
> @@ -124,6 +126,7 @@
>   	 _XELPDP_PORT_BUF_CTL2(port))
>   #define   XELPDP_LANE_PIPE_RESET(lane)			_PICK(lane, REG_BIT(31), REG_BIT(30))
>   #define   XELPDP_LANE_PHY_CURRENT_STATUS(lane)		_PICK(lane, REG_BIT(29), REG_BIT(28))
> +#define   XE3PLPDP_LANE_PHY_PULSE_STATUS(lane)		_PICK(lane, REG_BIT(27), REG_BIT(26))
>   #define   XELPDP_LANE_POWERDOWN_UPDATE(lane)		_PICK(lane, REG_BIT(25), REG_BIT(24))
>   #define   _XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK	REG_GENMASK(23, 20)
>   #define   _XELPDP_LANE0_POWERDOWN_NEW_STATE(val)	REG_FIELD_PREP(_XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK, val)
> @@ -151,6 +154,7 @@
>   #define   XELPDP_POWER_STATE_ACTIVE(val)		REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)
>   #define   XELPDP_P0_STATE_ACTIVE			0x0
>   #define   XELPDP_P2_STATE_READY				0x2
> +#define   XE3PLPD_P4_STATE_DISABLE			0x4
>   #define   XELPDP_P2PG_STATE_DISABLE			0x9
>   #define   XELPDP_P4PG_STATE_DISABLE			0xC
>   #define   XELPDP_P2_STATE_RESET				0x2
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> new file mode 100644
> index 000000000000..c65333cc9494
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -0,0 +1,159 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#include <drm/drm_print.h>
> +
> +#include "i915_reg.h"
> +#include "intel_cx0_phy.h"
> +#include "intel_cx0_phy_regs.h"
> +#include "intel_de.h"
> +#include "intel_display.h"
> +#include "intel_display_types.h"
> +#include "intel_lt_phy.h"
> +#include "intel_lt_phy_regs.h"
> +#include "intel_tc.h"
> +
> +#define INTEL_LT_PHY_LANE0		BIT(0)
> +#define INTEL_LT_PHY_LANE1		BIT(1)
> +#define INTEL_LT_PHY_BOTH_LANES		(INTEL_LT_PHY_LANE1 |\
> +					 INTEL_LT_PHY_LANE0)
> +
> +static u8 intel_lt_phy_get_owned_lane_mask(struct intel_encoder *encoder)
> +{
> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +
> +	if (!intel_tc_port_in_dp_alt_mode(dig_port))
> +		return INTEL_LT_PHY_BOTH_LANES;
> +
> +	return intel_tc_port_max_lane_count(dig_port) > 2
> +		? INTEL_LT_PHY_BOTH_LANES : INTEL_LT_PHY_LANE0;
> +}

Can the function in cx0 be exported/reused over here? This is just a 
duplicate of intel_cx0_phy_get_owned_lane_mask()

> +
> +static void
> +intel_lt_phy_setup_powerdown(struct intel_encoder *encoder, u8 lane_count)
> +{
> +	/*
> +	 * The new PORT_BUF_CTL6 stuff for dc5 entry and exit needs to be handled
> +	 * by dmc firmware not explicitly mentioned in Bspec. This leaves this
> +	 * function as a wrapper only but keeping it expecting future changes.
> +	 */
> +	intel_cx0_setup_powerdown(encoder);
> +}
> +
> +static void
> +intel_lt_phy_lane_reset(struct intel_encoder *encoder,
> +			u8 lane_count)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	enum port port = encoder->port;
> +	enum phy phy = intel_encoder_to_phy(encoder);
> +	u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
> +	u32 lane_pipe_reset = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES
> +				? XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1)
> +				: XELPDP_LANE_PIPE_RESET(0);
> +	u32 lane_phy_current_status = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES
> +					? (XELPDP_LANE_PHY_CURRENT_STATUS(0) |
> +					   XELPDP_LANE_PHY_CURRENT_STATUS(1))
> +					: XELPDP_LANE_PHY_CURRENT_STATUS(0);
> +	u32 lane_phy_pulse_status = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES
> +					? (XE3PLPDP_LANE_PHY_PULSE_STATUS(0) |
> +					   XE3PLPDP_LANE_PHY_PULSE_STATUS(1))
> +					: XE3PLPDP_LANE_PHY_PULSE_STATUS(0);
> +
> +	intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port),
> +		     XE3PLPD_MACCLK_RATE_MASK, XE3PLPD_MACCLK_RATE_DEF);
> +
> +	intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),
> +		     XE3PLPDP_PHY_MODE_MASK, XE3PLPDP_PHY_MODE_DP);
> +
> +	intel_lt_phy_setup_powerdown(encoder, lane_count);
> +
> +	intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port),
> +		     XE3PLPD_MACCLK_RESET_0, 0);
> +
> +	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> +		     XELPDP_LANE_PCLK_PLL_REQUEST(0),
> +		     XELPDP_LANE_PCLK_PLL_REQUEST(0));
> +
> +	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
> +				 XELPDP_LANE_PCLK_PLL_ACK(0),
> +				 XELPDP_LANE_PCLK_PLL_ACK(0),
> +				 XE3PLPD_MACCLK_TURNON_LATENCY_US,
> +				 XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
> +		drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack not done after %dus.\n",
> +			 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
> +
> +	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> +		     XELPDP_FORWARD_CLOCK_UNGATE,
> +		     XELPDP_FORWARD_CLOCK_UNGATE);
> +
> +	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> +		     lane_pipe_reset | lane_phy_pulse_status, 0);
> +
> +	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
> +				 lane_phy_current_status, 0,
> +				 XE3PLPD_RESET_END_LATENCY_US, 2, NULL))
> +		drm_warn(display->drm,
> +			 "PHY %c failed to bring out of Lane reset after %dus.\n",
> +			 phy_name(phy), XE3PLPD_RESET_END_LATENCY_US);
> +
> +	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
> +				 lane_phy_pulse_status, lane_phy_pulse_status,
> +				 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))
> +		drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
> +			 phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
> +
> +	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_phy_pulse_status, 0);
> +}
> +
> +void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> +			     const struct intel_crtc_state *crtc_state)
> +{
> +	/* 1. Enable MacCLK at default 162 MHz frequency. */
> +	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
> +
Should the entire steps be added over here or add them in the respective 
patches!
> +	/* 2. Program PORT_CLOCK_CTL register to configure clock muxes, gating, and SSC. */
> +	/* 3. Change owned PHY lanes power to Ready state. */
> +	/*
> +	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,
> +	 * encoded rate and encoded mode.
> +	 */
> +	/*
> +	 * 5. Program the PHY internal PLL registers over PHY message bus for the desired
> +	 * frequency and protocol type
> +	 */
> +	/* 6. Use the P2P transaction flow */
> +	/*
> +	 * 6.1. Set the PHY VDR register 0xCC4[Rate Control VDR Update] = 1 over PHY message
> +	 * bus for Owned PHY Lanes.
> +	 */
> +	/*
> +	 * 6.2. Poll for P2P Transaction Ready = "1" and read the MAC message bus VDR register
> +	 * at offset 0xC00 for Owned PHY Lanes.
> +	 */
> +	/* 6.3. Clear P2P transaction Ready bit. */
> +	/* 7. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0. */
> +	/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
> +	/*
> +	 * 9. Follow the Display Voltage Frequency Switching - Sequence Before Frequency Change.
> +	 * We handle this step in bxt_set_cdclk()
> +	 */
> +	/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
> +	/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
> +	/* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */
> +	/* 13. Ungate the forward clock by setting PORT_CLOCK_CTL[Forward Clock Ungate] = 1. */
> +	/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
> +	/*
> +	 * 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over PHY message bus for
> +	 * Owned PHY Lanes.
> +	 */
> +	/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
> +	/* 17. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
> +	/*
> +	 * 18. Follow the Display Voltage Frequency Switching - Sequence After Frequency Change.
> +	 * We handle this step in bxt_set_cdclk()
> +	 */
> +	/* 19. Move the PHY powerdown state to Active and program to enable/disable transmitters */
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> new file mode 100644
> index 000000000000..bd3ff3007e1d
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __INTEL_LT_PHY_H__
> +#define __INTEL_LT_PHY_H__
> +
> +#include <linux/types.h>
> +
> +struct intel_encoder;
> +struct intel_crtc_state;
> +
> +void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> +			     const struct intel_crtc_state *crtc_state);
> +
> +#endif /* __INTEL_LT_PHY_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> index 499acb1975d1..a4aa2a3e0425 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> @@ -9,6 +9,12 @@
>   #include "i915_reg_defs.h"
>   #include "intel_display_limits.h"
>   
> +#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
> +#define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
> +#define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
> +#define XE3PLPD_RESET_START_LATENCY_US	10
> +#define XE3PLPD_RESET_END_LATENCY_US	200
> +

Can the values be aligned?

Thanks and Regards,
Arun R Murthy
--------------------

>   /* LT Phy Vendor Register */
>   #define LT_PHY_VDR_0_CONFIG	0xC02
>   #define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
> @@ -24,4 +30,15 @@
>   
>   #define LT_PHY_RATE_UPDATE		0xCC4
>   
> +#define _XE3PLPD_PORT_BUF_CTL5(idx)	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
> +								 _XELPDP_PORT_BUF_CTL1_LN0_A, \
> +								 _XELPDP_PORT_BUF_CTL1_LN0_B, \
> +								 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> +								 _XELPDP_PORT_BUF_CTL1_LN0_USBC2) \
> +								+ 0x34)
> +#define XE3PLPD_PORT_BUF_CTL5(port)	_XE3PLPD_PORT_BUF_CTL5(__xe2lpd_port_idx(port))
> +#define  XE3PLPD_MACCLK_RESET_0		REG_BIT(11)
> +#define  XE3PLPD_MACCLK_RATE_MASK	REG_GENMASK(4, 0)
> +#define  XE3PLPD_MACCLK_RATE_DEF	REG_FIELD_PREP(XE3PLPD_MACCLK_RATE_MASK, 0x1F)
> +
>   #endif /* __INTEL_LT_PHY_REGS_H__ */
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 84321fad3265..314aeea0f1e3 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -291,6 +291,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
>   	i915-display/intel_hti.o \
>   	i915-display/intel_link_bw.o \
>   	i915-display/intel_lspcon.o \
> +	i915-display/intel_lt_phy.o \
>   	i915-display/intel_modeset_lock.o \
>   	i915-display/intel_modeset_setup.o \
>   	i915-display/intel_modeset_verify.o \

RE: [PATCH 03/25] drm/i915/ltphy: Phy lane reset for LT Phy

[Kandpal, Suraj]

> Subject: Re: [PATCH 03/25] drm/i915/ltphy: Phy lane reset for LT Phy
> 
> On 15-10-2025 09:37, Suraj Kandpal wrote:
> > Define function to bring phy lane out of reset for LT Phy and the
> > corresponding pre-requisite steps before we follow the steps for Phy
> > lane reset. Also create a skeleton of LT PHY PLL enable sequence
> > function in which we can place this function
> >
> > Bspec: 77449, 74749, 74499, 74495, 68960
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >   drivers/gpu/drm/i915/Makefile                 |   1 +
> >   drivers/gpu/drm/i915/display/intel_cx0_phy.c  |   2 +-
> >   drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   2 +
> >   .../gpu/drm/i915/display/intel_cx0_phy_regs.h |   4 +
> >   drivers/gpu/drm/i915/display/intel_lt_phy.c   | 159 ++++++++++++++++++
> >   drivers/gpu/drm/i915/display/intel_lt_phy.h   |  17 ++
> >   .../gpu/drm/i915/display/intel_lt_phy_regs.h  |  17 ++
> >   drivers/gpu/drm/xe/Makefile                   |   1 +
> >   8 files changed, 202 insertions(+), 1 deletion(-)
> >   create mode 100644 drivers/gpu/drm/i915/display/intel_lt_phy.c
> >   create mode 100644 drivers/gpu/drm/i915/display/intel_lt_phy.h
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile
> > b/drivers/gpu/drm/i915/Makefile index 6d7800e25e55..33836829d2c0
> > 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -352,6 +352,7 @@ i915-y += \
> >   	display/intel_gmbus.o \
> >   	display/intel_hdmi.o \
> >   	display/intel_lspcon.o \
> > +	display/intel_lt_phy.o \
> >   	display/intel_lvds.o \
> >   	display/intel_panel.o \
> >   	display/intel_pfit.o \
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index 6d9ebc8717ba..db2b05521c62 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -2843,7 +2843,7 @@ static void
> intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
> >   			 phy_name(phy),
> XELPDP_PORT_RESET_START_TIMEOUT_US);
> >   }
> >
> > -static void intel_cx0_setup_powerdown(struct intel_encoder *encoder)
> > +void intel_cx0_setup_powerdown(struct intel_encoder *encoder)
> >   {
> >   	struct intel_display *display = to_intel_display(encoder);
> >   	enum port port = encoder->port;
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > index c5a7b529955b..c92026fe7b8f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > @@ -41,6 +41,8 @@ bool intel_cx0pll_compare_hw_state(const struct
> intel_cx0pll_state *a,
> >   				   const struct intel_cx0pll_state *b);
> >   void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
> >   				     const struct intel_crtc_state *crtc_state);
> > +int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int
> > +clock); void intel_cx0_setup_powerdown(struct intel_encoder
> > +*encoder);
> >   int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
> >   void intel_cx0_pll_power_save_wa(struct intel_display *display);
> >   void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder, diff
> > --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> > index 18b91c23d547..114f6b2113db 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> > @@ -104,6 +104,8 @@
> >   #define   XELPDP_PORT_BUF_PORT_DATA_20BIT
> 	REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 1)
> >   #define   XELPDP_PORT_BUF_PORT_DATA_40BIT
> 	REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2)
> >   #define   XELPDP_PORT_REVERSAL				REG_BIT(16)
> > +#define   XE3PLPDP_PHY_MODE_MASK
> 	REG_GENMASK(15, 12)
> > +#define   XE3PLPDP_PHY_MODE_DP
> 	REG_FIELD_PREP(XE3PLPDP_PHY_MODE_MASK, 0x3)
> >   #define   XELPDP_PORT_BUF_IO_SELECT_TBT
> 	REG_BIT(11)
> >   #define   XELPDP_PORT_BUF_PHY_IDLE			REG_BIT(7)
> >   #define   XELPDP_TC_PHY_OWNERSHIP			REG_BIT(6)
> > @@ -124,6 +126,7 @@
> >   	 _XELPDP_PORT_BUF_CTL2(port))
> >   #define   XELPDP_LANE_PIPE_RESET(lane)			_PICK(lane,
> REG_BIT(31), REG_BIT(30))
> >   #define   XELPDP_LANE_PHY_CURRENT_STATUS(lane)
> 	_PICK(lane, REG_BIT(29), REG_BIT(28))
> > +#define   XE3PLPDP_LANE_PHY_PULSE_STATUS(lane)
> 	_PICK(lane, REG_BIT(27), REG_BIT(26))
> >   #define   XELPDP_LANE_POWERDOWN_UPDATE(lane)
> 	_PICK(lane, REG_BIT(25), REG_BIT(24))
> >   #define   _XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK
> 	REG_GENMASK(23, 20)
> >   #define   _XELPDP_LANE0_POWERDOWN_NEW_STATE(val)
> 	REG_FIELD_PREP(_XELPDP_LANE0_POWERDOWN_NEW_STATE_MA
> SK, val)
> > @@ -151,6 +154,7 @@
> >   #define   XELPDP_POWER_STATE_ACTIVE(val)
> 	REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)
> >   #define   XELPDP_P0_STATE_ACTIVE			0x0
> >   #define   XELPDP_P2_STATE_READY				0x2
> > +#define   XE3PLPD_P4_STATE_DISABLE			0x4
> >   #define   XELPDP_P2PG_STATE_DISABLE			0x9
> >   #define   XELPDP_P4PG_STATE_DISABLE			0xC
> >   #define   XELPDP_P2_STATE_RESET				0x2
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > new file mode 100644
> > index 000000000000..c65333cc9494
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -0,0 +1,159 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2025 Intel Corporation  */
> > +
> > +#include <drm/drm_print.h>
> > +
> > +#include "i915_reg.h"
> > +#include "intel_cx0_phy.h"
> > +#include "intel_cx0_phy_regs.h"
> > +#include "intel_de.h"
> > +#include "intel_display.h"
> > +#include "intel_display_types.h"
> > +#include "intel_lt_phy.h"
> > +#include "intel_lt_phy_regs.h"
> > +#include "intel_tc.h"
> > +
> > +#define INTEL_LT_PHY_LANE0		BIT(0)
> > +#define INTEL_LT_PHY_LANE1		BIT(1)
> > +#define INTEL_LT_PHY_BOTH_LANES
> 	(INTEL_LT_PHY_LANE1 |\
> > +					 INTEL_LT_PHY_LANE0)
> > +
> > +static u8 intel_lt_phy_get_owned_lane_mask(struct intel_encoder
> > +*encoder) {
> > +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > +
> > +	if (!intel_tc_port_in_dp_alt_mode(dig_port))
> > +		return INTEL_LT_PHY_BOTH_LANES;
> > +
> > +	return intel_tc_port_max_lane_count(dig_port) > 2
> > +		? INTEL_LT_PHY_BOTH_LANES : INTEL_LT_PHY_LANE0; }
> 
> Can the function in cx0 be exported/reused over here? This is just a duplicate
> of intel_cx0_phy_get_owned_lane_mask()

Not right now I do forsee some changes that may come in tc side of things later
Hence kept is separate for now

> 
> > +
> > +static void
> > +intel_lt_phy_setup_powerdown(struct intel_encoder *encoder, u8
> > +lane_count) {
> > +	/*
> > +	 * The new PORT_BUF_CTL6 stuff for dc5 entry and exit needs to be
> handled
> > +	 * by dmc firmware not explicitly mentioned in Bspec. This leaves this
> > +	 * function as a wrapper only but keeping it expecting future changes.
> > +	 */
> > +	intel_cx0_setup_powerdown(encoder);
> > +}
> > +
> > +static void
> > +intel_lt_phy_lane_reset(struct intel_encoder *encoder,
> > +			u8 lane_count)
> > +{
> > +	struct intel_display *display = to_intel_display(encoder);
> > +	enum port port = encoder->port;
> > +	enum phy phy = intel_encoder_to_phy(encoder);
> > +	u8 owned_lane_mask =
> intel_lt_phy_get_owned_lane_mask(encoder);
> > +	u32 lane_pipe_reset = owned_lane_mask ==
> INTEL_LT_PHY_BOTH_LANES
> > +				? XELPDP_LANE_PIPE_RESET(0) |
> XELPDP_LANE_PIPE_RESET(1)
> > +				: XELPDP_LANE_PIPE_RESET(0);
> > +	u32 lane_phy_current_status = owned_lane_mask ==
> INTEL_LT_PHY_BOTH_LANES
> > +					?
> (XELPDP_LANE_PHY_CURRENT_STATUS(0) |
> > +
> XELPDP_LANE_PHY_CURRENT_STATUS(1))
> > +					:
> XELPDP_LANE_PHY_CURRENT_STATUS(0);
> > +	u32 lane_phy_pulse_status = owned_lane_mask ==
> INTEL_LT_PHY_BOTH_LANES
> > +					?
> (XE3PLPDP_LANE_PHY_PULSE_STATUS(0) |
> > +
> XE3PLPDP_LANE_PHY_PULSE_STATUS(1))
> > +					:
> XE3PLPDP_LANE_PHY_PULSE_STATUS(0);
> > +
> > +	intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port),
> > +		     XE3PLPD_MACCLK_RATE_MASK,
> XE3PLPD_MACCLK_RATE_DEF);
> > +
> > +	intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),
> > +		     XE3PLPDP_PHY_MODE_MASK,
> XE3PLPDP_PHY_MODE_DP);
> > +
> > +	intel_lt_phy_setup_powerdown(encoder, lane_count);
> > +
> > +	intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port),
> > +		     XE3PLPD_MACCLK_RESET_0, 0);
> > +
> > +	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> > +		     XELPDP_LANE_PCLK_PLL_REQUEST(0),
> > +		     XELPDP_LANE_PCLK_PLL_REQUEST(0));
> > +
> > +	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display,
> port),
> > +				 XELPDP_LANE_PCLK_PLL_ACK(0),
> > +				 XELPDP_LANE_PCLK_PLL_ACK(0),
> > +				 XE3PLPD_MACCLK_TURNON_LATENCY_US,
> > +				 XE3PLPD_MACCLK_TURNON_LATENCY_MS,
> NULL))
> > +		drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack
> not done after %dus.\n",
> > +			 phy_name(phy),
> XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
> > +
> > +	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> > +		     XELPDP_FORWARD_CLOCK_UNGATE,
> > +		     XELPDP_FORWARD_CLOCK_UNGATE);
> > +
> > +	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> > +		     lane_pipe_reset | lane_phy_pulse_status, 0);
> > +
> > +	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display,
> port),
> > +				 lane_phy_current_status, 0,
> > +				 XE3PLPD_RESET_END_LATENCY_US, 2,
> NULL))
> > +		drm_warn(display->drm,
> > +			 "PHY %c failed to bring out of Lane reset after
> %dus.\n",
> > +			 phy_name(phy),
> XE3PLPD_RESET_END_LATENCY_US);
> > +
> > +	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display,
> port),
> > +				 lane_phy_pulse_status,
> lane_phy_pulse_status,
> > +				 XE3PLPD_RATE_CALIB_DONE_LATENCY_US,
> 0, NULL))
> > +		drm_warn(display->drm, "PHY %c PLL rate not changed after
> %dus.\n",
> > +			 phy_name(phy),
> XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
> > +
> > +	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> > +lane_phy_pulse_status, 0); }
> > +
> > +void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> > +			     const struct intel_crtc_state *crtc_state) {
> > +	/* 1. Enable MacCLK at default 162 MHz frequency. */
> > +	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
> > +
> Should the entire steps be added over here or add them in the respective
> patches!
> > +	/* 2. Program PORT_CLOCK_CTL register to configure clock muxes,
> gating, and SSC. */
> > +	/* 3. Change owned PHY lanes power to Ready state. */
> > +	/*
> > +	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config
> check enabled PLL type,
> > +	 * encoded rate and encoded mode.
> > +	 */
> > +	/*
> > +	 * 5. Program the PHY internal PLL registers over PHY message bus for
> the desired
> > +	 * frequency and protocol type
> > +	 */
> > +	/* 6. Use the P2P transaction flow */
> > +	/*
> > +	 * 6.1. Set the PHY VDR register 0xCC4[Rate Control VDR Update] = 1
> over PHY message
> > +	 * bus for Owned PHY Lanes.
> > +	 */
> > +	/*
> > +	 * 6.2. Poll for P2P Transaction Ready = "1" and read the MAC
> message bus VDR register
> > +	 * at offset 0xC00 for Owned PHY Lanes.
> > +	 */
> > +	/* 6.3. Clear P2P transaction Ready bit. */
> > +	/* 7. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0. */
> > +	/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
> > +	/*
> > +	 * 9. Follow the Display Voltage Frequency Switching - Sequence
> Before Frequency Change.
> > +	 * We handle this step in bxt_set_cdclk()
> > +	 */
> > +	/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock
> frequency. */
> > +	/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
> > +	/* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */
> > +	/* 13. Ungate the forward clock by setting PORT_CLOCK_CTL[Forward
> Clock Ungate] = 1. */
> > +	/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
> > +	/*
> > +	 * 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update]
> over PHY message bus for
> > +	 * Owned PHY Lanes.
> > +	 */
> > +	/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for
> Owned PHY Lanes. */
> > +	/* 17. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
> > +	/*
> > +	 * 18. Follow the Display Voltage Frequency Switching - Sequence
> After Frequency Change.
> > +	 * We handle this step in bxt_set_cdclk()
> > +	 */
> > +	/* 19. Move the PHY powerdown state to Active and program to
> > +enable/disable transmitters */ }
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > new file mode 100644
> > index 000000000000..bd3ff3007e1d
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> > @@ -0,0 +1,17 @@
> > +/* SPDX-License-Identifier: MIT
> > + *
> > + * Copyright © 2025 Intel Corporation  */
> > +
> > +#ifndef __INTEL_LT_PHY_H__
> > +#define __INTEL_LT_PHY_H__
> > +
> > +#include <linux/types.h>
> > +
> > +struct intel_encoder;
> > +struct intel_crtc_state;
> > +
> > +void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> > +			     const struct intel_crtc_state *crtc_state);
> > +
> > +#endif /* __INTEL_LT_PHY_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > index 499acb1975d1..a4aa2a3e0425 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > @@ -9,6 +9,12 @@
> >   #include "i915_reg_defs.h"
> >   #include "intel_display_limits.h"
> >
> > +#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
> > +#define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
> > +#define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
> > +#define XE3PLPD_RESET_START_LATENCY_US	10
> > +#define XE3PLPD_RESET_END_LATENCY_US	200
> > +
> 
> Can the values be aligned?

They seem to be aligned

Regards,
Suraj Kandpal

> 
> Thanks and Regards,
> Arun R Murthy
> --------------------
> 
> >   /* LT Phy Vendor Register */
> >   #define LT_PHY_VDR_0_CONFIG	0xC02
> >   #define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
> > @@ -24,4 +30,15 @@
> >
> >   #define LT_PHY_RATE_UPDATE		0xCC4
> >
> > +#define _XE3PLPD_PORT_BUF_CTL5(idx)
> 	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
> > +
> _XELPDP_PORT_BUF_CTL1_LN0_A, \
> > +
> _XELPDP_PORT_BUF_CTL1_LN0_B, \
> > +
> _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> > +
> _XELPDP_PORT_BUF_CTL1_LN0_USBC2) \
> > +								+ 0x34)
> > +#define XE3PLPD_PORT_BUF_CTL5(port)
> 	_XE3PLPD_PORT_BUF_CTL5(__xe2lpd_port_idx(port))
> > +#define  XE3PLPD_MACCLK_RESET_0		REG_BIT(11)
> > +#define  XE3PLPD_MACCLK_RATE_MASK	REG_GENMASK(4, 0)
> > +#define  XE3PLPD_MACCLK_RATE_DEF
> 	REG_FIELD_PREP(XE3PLPD_MACCLK_RATE_MASK, 0x1F)
> > +
> >   #endif /* __INTEL_LT_PHY_REGS_H__ */ diff --git
> > a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index
> > 84321fad3265..314aeea0f1e3 100644
> > --- a/drivers/gpu/drm/xe/Makefile
> > +++ b/drivers/gpu/drm/xe/Makefile
> > @@ -291,6 +291,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
> >   	i915-display/intel_hti.o \
> >   	i915-display/intel_link_bw.o \
> >   	i915-display/intel_lspcon.o \
> > +	i915-display/intel_lt_phy.o \
> >   	i915-display/intel_modeset_lock.o \
> >   	i915-display/intel_modeset_setup.o \
> >   	i915-display/intel_modeset_verify.o \

[PATCH 04/25] drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT Phy

[Suraj Kandpal]

Program sequence from port clock ctl except for the SSC
enablement part which will be taken care of later.

Bspec: 74492
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c |  8 ++---
 drivers/gpu/drm/i915/display/intel_cx0_phy.h |  1 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c  | 36 ++++++++++++++++++++
 3 files changed, 41 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index db2b05521c62..eab49c08d7ff 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2585,7 +2585,7 @@ static bool is_dp2(u32 clock)
 	return false;
 }
 
-static bool is_hdmi_frl(u32 clock)
+bool intel_cx0_is_hdmi_frl(u32 clock)
 {
 	switch (clock) {
 	case 300000: /* 3 Gbps */
@@ -2612,7 +2612,7 @@ static int intel_get_c20_custom_width(u32 clock, bool dp)
 {
 	if (dp && is_dp2(clock))
 		return 2;
-	else if (is_hdmi_frl(clock))
+	else if (intel_cx0_is_hdmi_frl(clock))
 		return 1;
 	else
 		return 0;
@@ -2706,7 +2706,7 @@ static void intel_c20_pll_program(struct intel_display *display,
 	} else {
 		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
 			      BIT(7) | PHY_C20_CUSTOM_SERDES_MASK,
-			      is_hdmi_frl(port_clock) ? BIT(7) : 0,
+			      intel_cx0_is_hdmi_frl(port_clock) ? BIT(7) : 0,
 			      MB_WRITE_COMMITTED);
 
 		intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
@@ -2766,7 +2766,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
 
 	val |= XELPDP_FORWARD_CLOCK_UNGATE;
 
-	if (!is_dp && is_hdmi_frl(port_clock))
+	if (!is_dp && intel_cx0_is_hdmi_frl(port_clock))
 		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
 	else
 		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index c92026fe7b8f..b111a893b428 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -43,6 +43,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 				     const struct intel_crtc_state *crtc_state);
 int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
 void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
+bool intel_cx0_is_hdmi_frl(u32 clock);
 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
 void intel_cx0_pll_power_save_wa(struct intel_display *display);
 void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index c65333cc9494..8c6f60d9e0ac 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -108,13 +108,49 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
 	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_phy_pulse_status, 0);
 }
 
+static void
+intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
+				    const struct intel_crtc_state *crtc_state,
+				    bool lane_reversal)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	u32 val = 0;
+
+	intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
+		     XELPDP_PORT_REVERSAL,
+		     lane_reversal ? XELPDP_PORT_REVERSAL : 0);
+
+	val |= XELPDP_FORWARD_CLOCK_UNGATE;
+
+	/*
+	 * We actually mean MACCLK here and not MAXPCLK when using LT Phy
+	 * but since the register bits still remain the same we use
+	 * the same definition
+	 */
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
+	    intel_cx0_is_hdmi_frl(crtc_state->port_clock))
+		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
+	else
+		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
+
+	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
+		     XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
+		     XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_SSC_ENABLE_PLLA |
+		     XELPDP_SSC_ENABLE_PLLB, val);
+}
+
 void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 			     const struct intel_crtc_state *crtc_state)
 {
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+	bool lane_reversal = dig_port->lane_reversal;
+
 	/* 1. Enable MacCLK at default 162 MHz frequency. */
 	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
 
 	/* 2. Program PORT_CLOCK_CTL register to configure clock muxes, gating, and SSC. */
+	intel_lt_phy_program_port_clock_ctl(encoder, crtc_state, lane_reversal);
+
 	/* 3. Change owned PHY lanes power to Ready state. */
 	/*
 	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,
-- 
2.34.1

Re: [PATCH 04/25] drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT Phy

[Murthy, Arun R]

On 15-10-2025 09:37, Suraj Kandpal wrote:
> Program sequence from port clock ctl except for the SSC
> enablement part which will be taken care of later.
>
> Bspec: 74492
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_cx0_phy.c |  8 ++---
>   drivers/gpu/drm/i915/display/intel_cx0_phy.h |  1 +
>   drivers/gpu/drm/i915/display/intel_lt_phy.c  | 36 ++++++++++++++++++++
>   3 files changed, 41 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index db2b05521c62..eab49c08d7ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2585,7 +2585,7 @@ static bool is_dp2(u32 clock)
>   	return false;
>   }
>   
> -static bool is_hdmi_frl(u32 clock)
> +bool intel_cx0_is_hdmi_frl(u32 clock)
>   {
>   	switch (clock) {
>   	case 300000: /* 3 Gbps */
> @@ -2612,7 +2612,7 @@ static int intel_get_c20_custom_width(u32 clock, bool dp)
>   {
>   	if (dp && is_dp2(clock))
>   		return 2;
> -	else if (is_hdmi_frl(clock))
> +	else if (intel_cx0_is_hdmi_frl(clock))
>   		return 1;
>   	else
>   		return 0;
> @@ -2706,7 +2706,7 @@ static void intel_c20_pll_program(struct intel_display *display,
>   	} else {
>   		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
>   			      BIT(7) | PHY_C20_CUSTOM_SERDES_MASK,
> -			      is_hdmi_frl(port_clock) ? BIT(7) : 0,
> +			      intel_cx0_is_hdmi_frl(port_clock) ? BIT(7) : 0,
>   			      MB_WRITE_COMMITTED);
>   
>   		intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
> @@ -2766,7 +2766,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
>   
>   	val |= XELPDP_FORWARD_CLOCK_UNGATE;
>   
> -	if (!is_dp && is_hdmi_frl(port_clock))
> +	if (!is_dp && intel_cx0_is_hdmi_frl(port_clock))
Would it be better to move this to a different patch?
>   		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
>   	else
>   		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index c92026fe7b8f..b111a893b428 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -43,6 +43,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
>   				     const struct intel_crtc_state *crtc_state);
>   int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
>   void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
> +bool intel_cx0_is_hdmi_frl(u32 clock);
>   int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
>   void intel_cx0_pll_power_save_wa(struct intel_display *display);
>   void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index c65333cc9494..8c6f60d9e0ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -108,13 +108,49 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
>   	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_phy_pulse_status, 0);
>   }
>   
> +static void
> +intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
> +				    const struct intel_crtc_state *crtc_state,
> +				    bool lane_reversal)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	u32 val = 0;
> +
> +	intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
> +		     XELPDP_PORT_REVERSAL,
> +		     lane_reversal ? XELPDP_PORT_REVERSAL : 0);
> +
> +	val |= XELPDP_FORWARD_CLOCK_UNGATE;
> +
> +	/*
> +	 * We actually mean MACCLK here and not MAXPCLK when using LT Phy
> +	 * but since the register bits still remain the same we use
> +	 * the same definition
> +	 */
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> +	    intel_cx0_is_hdmi_frl(crtc_state->port_clock))
> +		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
> +	else
> +		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
> +
> +	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> +		     XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
> +		     XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_SSC_ENABLE_PLLA |
> +		     XELPDP_SSC_ENABLE_PLLB, val);
> +}
> +
>   void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   			     const struct intel_crtc_state *crtc_state)
>   {
> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +	bool lane_reversal = dig_port->lane_reversal;
> +
>   	/* 1. Enable MacCLK at default 162 MHz frequency. */
>   	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
>   
>   	/* 2. Program PORT_CLOCK_CTL register to configure clock muxes, gating, and SSC. */
> +	intel_lt_phy_program_port_clock_ctl(encoder, crtc_state, lane_reversal);
> +
>   	/* 3. Change owned PHY lanes power to Ready state. */
>   	/*
>   	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,

RE: [PATCH 04/25] drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT Phy

[Kandpal, Suraj]

> Subject: Re: [PATCH 04/25] drm/i915/ltphy: Program sequence for
> PORT_CLOCK_CTL for LT Phy
> 
> On 15-10-2025 09:37, Suraj Kandpal wrote:
> > Program sequence from port clock ctl except for the SSC enablement
> > part which will be taken care of later.
> >
> > Bspec: 74492
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_cx0_phy.c |  8 ++---
> >   drivers/gpu/drm/i915/display/intel_cx0_phy.h |  1 +
> >   drivers/gpu/drm/i915/display/intel_lt_phy.c  | 36 ++++++++++++++++++++
> >   3 files changed, 41 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index db2b05521c62..eab49c08d7ff 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -2585,7 +2585,7 @@ static bool is_dp2(u32 clock)
> >   	return false;
> >   }
> >
> > -static bool is_hdmi_frl(u32 clock)
> > +bool intel_cx0_is_hdmi_frl(u32 clock)
> >   {
> >   	switch (clock) {
> >   	case 300000: /* 3 Gbps */
> > @@ -2612,7 +2612,7 @@ static int intel_get_c20_custom_width(u32 clock,
> bool dp)
> >   {
> >   	if (dp && is_dp2(clock))
> >   		return 2;
> > -	else if (is_hdmi_frl(clock))
> > +	else if (intel_cx0_is_hdmi_frl(clock))
> >   		return 1;
> >   	else
> >   		return 0;
> > @@ -2706,7 +2706,7 @@ static void intel_c20_pll_program(struct
> intel_display *display,
> >   	} else {
> >   		intel_cx0_rmw(encoder, owned_lane_mask,
> PHY_C20_VDR_CUSTOM_SERDES_RATE,
> >   			      BIT(7) | PHY_C20_CUSTOM_SERDES_MASK,
> > -			      is_hdmi_frl(port_clock) ? BIT(7) : 0,
> > +			      intel_cx0_is_hdmi_frl(port_clock) ? BIT(7) : 0,
> >   			      MB_WRITE_COMMITTED);
> >
> >   		intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES,
> > PHY_C20_VDR_HDMI_RATE, @@ -2766,7 +2766,7 @@ static void
> > intel_program_port_clock_ctl(struct intel_encoder *encoder,
> >
> >   	val |= XELPDP_FORWARD_CLOCK_UNGATE;
> >
> > -	if (!is_dp && is_hdmi_frl(port_clock))
> > +	if (!is_dp && intel_cx0_is_hdmi_frl(port_clock))
> Would it be better to move this to a different patch?

I can move it to a separate patch I was also thinking of having this function inside intel_hdmi then,
What do you say?

Regards,
Suraj Kandpal

> >   		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
> XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
> >   	else
> >   		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
> > XELPDP_DDI_CLOCK_SELECT_MAXPCLK); diff --git
> > a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > index c92026fe7b8f..b111a893b428 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > @@ -43,6 +43,7 @@ void intel_cx0_phy_set_signal_levels(struct
> intel_encoder *encoder,
> >   				     const struct intel_crtc_state *crtc_state);
> >   int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
> >   void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
> > +bool intel_cx0_is_hdmi_frl(u32 clock);
> >   int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
> >   void intel_cx0_pll_power_save_wa(struct intel_display *display);
> >   void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder, diff
> > --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index c65333cc9494..8c6f60d9e0ac 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -108,13 +108,49 @@ intel_lt_phy_lane_reset(struct intel_encoder
> *encoder,
> >   	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> lane_phy_pulse_status, 0);
> >   }
> >
> > +static void
> > +intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
> > +				    const struct intel_crtc_state *crtc_state,
> > +				    bool lane_reversal)
> > +{
> > +	struct intel_display *display = to_intel_display(encoder);
> > +	u32 val = 0;
> > +
> > +	intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder-
> >port),
> > +		     XELPDP_PORT_REVERSAL,
> > +		     lane_reversal ? XELPDP_PORT_REVERSAL : 0);
> > +
> > +	val |= XELPDP_FORWARD_CLOCK_UNGATE;
> > +
> > +	/*
> > +	 * We actually mean MACCLK here and not MAXPCLK when using LT
> Phy
> > +	 * but since the register bits still remain the same we use
> > +	 * the same definition
> > +	 */
> > +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> > +	    intel_cx0_is_hdmi_frl(crtc_state->port_clock))
> > +		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
> XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
> > +	else
> > +		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
> > +XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
> > +
> > +	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder-
> >port),
> > +		     XELPDP_LANE1_PHY_CLOCK_SELECT |
> XELPDP_FORWARD_CLOCK_UNGATE |
> > +		     XELPDP_DDI_CLOCK_SELECT_MASK(display) |
> XELPDP_SSC_ENABLE_PLLA |
> > +		     XELPDP_SSC_ENABLE_PLLB, val);
> > +}
> > +
> >   void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> >   			     const struct intel_crtc_state *crtc_state)
> >   {
> > +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > +	bool lane_reversal = dig_port->lane_reversal;
> > +
> >   	/* 1. Enable MacCLK at default 162 MHz frequency. */
> >   	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
> >
> >   	/* 2. Program PORT_CLOCK_CTL register to configure clock muxes,
> > gating, and SSC. */
> > +	intel_lt_phy_program_port_clock_ctl(encoder, crtc_state,
> > +lane_reversal);
> > +
> >   	/* 3. Change owned PHY lanes power to Ready state. */
> >   	/*
> >   	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check
> > enabled PLL type,

Re: [PATCH 04/25] drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT Phy

[Murthy, Arun R]

On 22-10-2025 14:28, Kandpal, Suraj wrote:
>> Subject: Re: [PATCH 04/25] drm/i915/ltphy: Program sequence for
>> PORT_CLOCK_CTL for LT Phy
>>
>> On 15-10-2025 09:37, Suraj Kandpal wrote:
>>> Program sequence from port clock ctl except for the SSC enablement
>>> part which will be taken care of later.
>>>
>>> Bspec: 74492
>>> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/display/intel_cx0_phy.c |  8 ++---
>>>    drivers/gpu/drm/i915/display/intel_cx0_phy.h |  1 +
>>>    drivers/gpu/drm/i915/display/intel_lt_phy.c  | 36 ++++++++++++++++++++
>>>    3 files changed, 41 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>> index db2b05521c62..eab49c08d7ff 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>> @@ -2585,7 +2585,7 @@ static bool is_dp2(u32 clock)
>>>    	return false;
>>>    }
>>>
>>> -static bool is_hdmi_frl(u32 clock)
>>> +bool intel_cx0_is_hdmi_frl(u32 clock)
>>>    {
>>>    	switch (clock) {
>>>    	case 300000: /* 3 Gbps */
>>> @@ -2612,7 +2612,7 @@ static int intel_get_c20_custom_width(u32 clock,
>> bool dp)
>>>    {
>>>    	if (dp && is_dp2(clock))
>>>    		return 2;
>>> -	else if (is_hdmi_frl(clock))
>>> +	else if (intel_cx0_is_hdmi_frl(clock))
>>>    		return 1;
>>>    	else
>>>    		return 0;
>>> @@ -2706,7 +2706,7 @@ static void intel_c20_pll_program(struct
>> intel_display *display,
>>>    	} else {
>>>    		intel_cx0_rmw(encoder, owned_lane_mask,
>> PHY_C20_VDR_CUSTOM_SERDES_RATE,
>>>    			      BIT(7) | PHY_C20_CUSTOM_SERDES_MASK,
>>> -			      is_hdmi_frl(port_clock) ? BIT(7) : 0,
>>> +			      intel_cx0_is_hdmi_frl(port_clock) ? BIT(7) : 0,
>>>    			      MB_WRITE_COMMITTED);
>>>
>>>    		intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES,
>>> PHY_C20_VDR_HDMI_RATE, @@ -2766,7 +2766,7 @@ static void
>>> intel_program_port_clock_ctl(struct intel_encoder *encoder,
>>>
>>>    	val |= XELPDP_FORWARD_CLOCK_UNGATE;
>>>
>>> -	if (!is_dp && is_hdmi_frl(port_clock))
>>> +	if (!is_dp && intel_cx0_is_hdmi_frl(port_clock))
>> Would it be better to move this to a different patch?
> I can move it to a separate patch I was also thinking of having this function inside intel_hdmi then,
> What do you say?

Sounds better to me!

Thanks and Regards,
Arun R Murthy
--------------------

> Regards,
> Suraj Kandpal
>
>>>    		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
>> XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
>>>    	else
>>>    		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
>>> XELPDP_DDI_CLOCK_SELECT_MAXPCLK); diff --git
>>> a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
>>> b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
>>> index c92026fe7b8f..b111a893b428 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
>>> @@ -43,6 +43,7 @@ void intel_cx0_phy_set_signal_levels(struct
>> intel_encoder *encoder,
>>>    				     const struct intel_crtc_state *crtc_state);
>>>    int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
>>>    void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
>>> +bool intel_cx0_is_hdmi_frl(u32 clock);
>>>    int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
>>>    void intel_cx0_pll_power_save_wa(struct intel_display *display);
>>>    void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder, diff
>>> --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
>>> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
>>> index c65333cc9494..8c6f60d9e0ac 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
>>> @@ -108,13 +108,49 @@ intel_lt_phy_lane_reset(struct intel_encoder
>> *encoder,
>>>    	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
>> lane_phy_pulse_status, 0);
>>>    }
>>>
>>> +static void
>>> +intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
>>> +				    const struct intel_crtc_state *crtc_state,
>>> +				    bool lane_reversal)
>>> +{
>>> +	struct intel_display *display = to_intel_display(encoder);
>>> +	u32 val = 0;
>>> +
>>> +	intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder-
>>> port),
>>> +		     XELPDP_PORT_REVERSAL,
>>> +		     lane_reversal ? XELPDP_PORT_REVERSAL : 0);
>>> +
>>> +	val |= XELPDP_FORWARD_CLOCK_UNGATE;
>>> +
>>> +	/*
>>> +	 * We actually mean MACCLK here and not MAXPCLK when using LT
>> Phy
>>> +	 * but since the register bits still remain the same we use
>>> +	 * the same definition
>>> +	 */
>>> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
>>> +	    intel_cx0_is_hdmi_frl(crtc_state->port_clock))
>>> +		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
>> XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
>>> +	else
>>> +		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
>>> +XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
>>> +
>>> +	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder-
>>> port),
>>> +		     XELPDP_LANE1_PHY_CLOCK_SELECT |
>> XELPDP_FORWARD_CLOCK_UNGATE |
>>> +		     XELPDP_DDI_CLOCK_SELECT_MASK(display) |
>> XELPDP_SSC_ENABLE_PLLA |
>>> +		     XELPDP_SSC_ENABLE_PLLB, val);
>>> +}
>>> +
>>>    void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>>>    			     const struct intel_crtc_state *crtc_state)
>>>    {
>>> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>>> +	bool lane_reversal = dig_port->lane_reversal;
>>> +
>>>    	/* 1. Enable MacCLK at default 162 MHz frequency. */
>>>    	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
>>>
>>>    	/* 2. Program PORT_CLOCK_CTL register to configure clock muxes,
>>> gating, and SSC. */
>>> +	intel_lt_phy_program_port_clock_ctl(encoder, crtc_state,
>>> +lane_reversal);
>>> +
>>>    	/* 3. Change owned PHY lanes power to Ready state. */
>>>    	/*
>>>    	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check
>>> enabled PLL type,

[PATCH 05/25] drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence

[Suraj Kandpal]

Add a wrapper on cx0 powerdown change sequence for LT Phy usage,
as the sequence remains unchanged when going from SNPS Phy to
LT Phy.

Bspec: 74495
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c |  6 +++---
 drivers/gpu/drm/i915/display/intel_cx0_phy.h |  2 ++
 drivers/gpu/drm/i915/display/intel_lt_phy.c  | 13 +++++++++++++
 3 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index eab49c08d7ff..8455d0725968 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2806,8 +2806,8 @@ static u32 intel_cx0_get_powerdown_state(u8 lane_mask, u8 state)
 	return val;
 }
 
-static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
-						u8 lane_mask, u8 state)
+void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
+					 u8 lane_mask, u8 state)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	enum port port = encoder->port;
@@ -2837,7 +2837,7 @@ static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
 	/* Update Timeout Value */
 	if (intel_de_wait_custom(display, buf_ctl2_reg,
 				 intel_cx0_get_powerdown_update(lane_mask), 0,
-				 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
+				 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 2, NULL))
 		drm_warn(display->drm,
 			 "PHY %c failed to bring out of Lane reset after %dus.\n",
 			 phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index b111a893b428..8c9b97f0922d 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -41,6 +41,8 @@ bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
 				   const struct intel_cx0pll_state *b);
 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 				     const struct intel_crtc_state *crtc_state);
+void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
+					 u8 lane_mask, u8 state);
 int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
 void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
 bool intel_cx0_is_hdmi_frl(u32 clock);
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 8c6f60d9e0ac..263e9780b55c 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -42,6 +42,13 @@ intel_lt_phy_setup_powerdown(struct intel_encoder *encoder, u8 lane_count)
 	intel_cx0_setup_powerdown(encoder);
 }
 
+static void
+intel_lt_phy_powerdown_change_sequence(struct intel_encoder *encoder,
+				       u8 lane_mask, u8 state)
+{
+	intel_cx0_powerdown_change_sequence(encoder, lane_mask, state);
+}
+
 static void
 intel_lt_phy_lane_reset(struct intel_encoder *encoder,
 			u8 lane_count)
@@ -69,6 +76,8 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
 		     XE3PLPDP_PHY_MODE_MASK, XE3PLPDP_PHY_MODE_DP);
 
 	intel_lt_phy_setup_powerdown(encoder, lane_count);
+	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
+					       XELPDP_P2_STATE_RESET);
 
 	intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port),
 		     XE3PLPD_MACCLK_RESET_0, 0);
@@ -144,6 +153,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	bool lane_reversal = dig_port->lane_reversal;
+	u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
 
 	/* 1. Enable MacCLK at default 162 MHz frequency. */
 	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
@@ -152,6 +162,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 	intel_lt_phy_program_port_clock_ctl(encoder, crtc_state, lane_reversal);
 
 	/* 3. Change owned PHY lanes power to Ready state. */
+	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
+					       XELPDP_P2_STATE_READY);
+
 	/*
 	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,
 	 * encoded rate and encoded mode.
-- 
2.34.1

Re: [PATCH 05/25] drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence

[Murthy, Arun R]

On 15-10-2025 09:37, Suraj Kandpal wrote:
> Add a wrapper on cx0 powerdown change sequence for LT Phy usage,
> as the sequence remains unchanged when going from SNPS Phy to
> LT Phy.
>
> Bspec: 74495
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>

Looks good to me

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>


Thanks and Regards,
Arun R Murthy
--------------------

> ---
>   drivers/gpu/drm/i915/display/intel_cx0_phy.c |  6 +++---
>   drivers/gpu/drm/i915/display/intel_cx0_phy.h |  2 ++
>   drivers/gpu/drm/i915/display/intel_lt_phy.c  | 13 +++++++++++++
>   3 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index eab49c08d7ff..8455d0725968 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2806,8 +2806,8 @@ static u32 intel_cx0_get_powerdown_state(u8 lane_mask, u8 state)
>   	return val;
>   }
>   
> -static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
> -						u8 lane_mask, u8 state)
> +void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
> +					 u8 lane_mask, u8 state)
>   {
>   	struct intel_display *display = to_intel_display(encoder);
>   	enum port port = encoder->port;
> @@ -2837,7 +2837,7 @@ static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
>   	/* Update Timeout Value */
>   	if (intel_de_wait_custom(display, buf_ctl2_reg,
>   				 intel_cx0_get_powerdown_update(lane_mask), 0,
> -				 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
> +				 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 2, NULL))
>   		drm_warn(display->drm,
>   			 "PHY %c failed to bring out of Lane reset after %dus.\n",
>   			 phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index b111a893b428..8c9b97f0922d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -41,6 +41,8 @@ bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
>   				   const struct intel_cx0pll_state *b);
>   void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
>   				     const struct intel_crtc_state *crtc_state);
> +void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
> +					 u8 lane_mask, u8 state);
>   int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
>   void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
>   bool intel_cx0_is_hdmi_frl(u32 clock);
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 8c6f60d9e0ac..263e9780b55c 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -42,6 +42,13 @@ intel_lt_phy_setup_powerdown(struct intel_encoder *encoder, u8 lane_count)
>   	intel_cx0_setup_powerdown(encoder);
>   }
>   
> +static void
> +intel_lt_phy_powerdown_change_sequence(struct intel_encoder *encoder,
> +				       u8 lane_mask, u8 state)
> +{
> +	intel_cx0_powerdown_change_sequence(encoder, lane_mask, state);
> +}
> +
>   static void
>   intel_lt_phy_lane_reset(struct intel_encoder *encoder,
>   			u8 lane_count)
> @@ -69,6 +76,8 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
>   		     XE3PLPDP_PHY_MODE_MASK, XE3PLPDP_PHY_MODE_DP);
>   
>   	intel_lt_phy_setup_powerdown(encoder, lane_count);
> +	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
> +					       XELPDP_P2_STATE_RESET);
>   
>   	intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port),
>   		     XE3PLPD_MACCLK_RESET_0, 0);
> @@ -144,6 +153,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   {
>   	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>   	bool lane_reversal = dig_port->lane_reversal;
> +	u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
>   
>   	/* 1. Enable MacCLK at default 162 MHz frequency. */
>   	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
> @@ -152,6 +162,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   	intel_lt_phy_program_port_clock_ctl(encoder, crtc_state, lane_reversal);
>   
>   	/* 3. Change owned PHY lanes power to Ready state. */
> +	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
> +					       XELPDP_P2_STATE_READY);
> +
>   	/*
>   	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,
>   	 * encoded rate and encoded mode.

[PATCH 06/25] drm/i915/ltphy: Read PHY_VDR_0_CONFIG register

[Suraj Kandpal]

Read PHY_VDR_0_CONFIG to check if there is any change in the register and
decide based on that if some steps need to be executed or not. This
scenario only happens if the requested mode uses 1.62Gbps with DP mode
since LT PHY defaults to this mode if any other mode is requested we
need to follow the whole sequence.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c |   4 +-
 drivers/gpu/drm/i915/display/intel_cx0_phy.h |   2 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c  | 146 ++++++++++++++++---
 3 files changed, 127 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 8455d0725968..4e074754a78f 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -271,8 +271,8 @@ static u8 __intel_cx0_read(struct intel_encoder *encoder,
 	return 0;
 }
 
-static u8 intel_cx0_read(struct intel_encoder *encoder,
-			 u8 lane_mask, u16 addr)
+u8 intel_cx0_read(struct intel_encoder *encoder,
+		  u8 lane_mask, u16 addr)
 {
 	int lane = lane_mask_to_lane(lane_mask);
 
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 8c9b97f0922d..b448ce936c37 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -46,6 +46,8 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
 int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
 void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
 bool intel_cx0_is_hdmi_frl(u32 clock);
+u8 intel_cx0_read(struct intel_encoder *encoder,
+		  u8 lane_mask, u16 addr);
 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
 void intel_cx0_pll_power_save_wa(struct intel_display *display);
 void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 263e9780b55c..c2d5e4b82db5 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -6,6 +6,7 @@
 #include <drm/drm_print.h>
 
 #include "i915_reg.h"
+#include "i915_utils.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_de.h"
@@ -13,12 +14,14 @@
 #include "intel_display_types.h"
 #include "intel_lt_phy.h"
 #include "intel_lt_phy_regs.h"
+#include "intel_psr.h"
 #include "intel_tc.h"
 
 #define INTEL_LT_PHY_LANE0		BIT(0)
 #define INTEL_LT_PHY_LANE1		BIT(1)
 #define INTEL_LT_PHY_BOTH_LANES		(INTEL_LT_PHY_LANE1 |\
 					 INTEL_LT_PHY_LANE0)
+#define MODE_DP				3
 
 static u8 intel_lt_phy_get_owned_lane_mask(struct intel_encoder *encoder)
 {
@@ -31,6 +34,12 @@ static u8 intel_lt_phy_get_owned_lane_mask(struct intel_encoder *encoder)
 		? INTEL_LT_PHY_BOTH_LANES : INTEL_LT_PHY_LANE0;
 }
 
+static u8 intel_lt_phy_read(struct intel_encoder *encoder,
+			    u8 lane_mask, u16 addr)
+{
+	return intel_cx0_read(encoder, lane_mask, addr);
+}
+
 static void
 intel_lt_phy_setup_powerdown(struct intel_encoder *encoder, u8 lane_count)
 {
@@ -148,12 +157,96 @@ intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
 		     XELPDP_SSC_ENABLE_PLLB, val);
 }
 
+static u32
+intel_lt_phy_get_dp_clock(u8 rate)
+{
+	switch (rate) {
+	case 0:
+		return 162000;
+	case 1:
+		return 270000;
+	case 2:
+		return 540000;
+	case 3:
+		return 810000;
+	case 4:
+		return 216000;
+	case 5:
+		return 243000;
+	case 6:
+		return 324000;
+	case 7:
+		return 432000;
+	case 8:
+		return 1000000;
+	case 9:
+		return 1350000;
+	case 10:
+		return 2000000;
+	case 11:
+		return 675000;
+	default:
+		MISSING_CASE(rate);
+		return 0;
+	}
+}
+
+static bool
+intel_lt_phy_config_changed(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state)
+{
+	u8 val, rate;
+	u32 clock;
+
+	val = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,
+				LT_PHY_VDR_0_CONFIG);
+	rate = REG_FIELD_GET8(LT_PHY_VDR_RATE_ENCODING_MASK, val);
+
+	/*
+	 * The only time we do not reconfigure the PLL is when we are
+	 * using 1.62 Gbps clock since PHY PLL defaults to that
+	 * otherwise we always need to reconfigure it.
+	 */
+	if (intel_crtc_has_dp_encoder(crtc_state)) {
+		clock = intel_lt_phy_get_dp_clock(rate);
+		if (crtc_state->port_clock == 1620000 && crtc_state->port_clock == clock)
+			return false;
+	}
+
+	return true;
+}
+
+static intel_wakeref_t intel_lt_phy_transaction_begin(struct intel_encoder *encoder)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	intel_wakeref_t wakeref;
+
+	intel_psr_pause(intel_dp);
+	wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF);
+
+	return wakeref;
+}
+
+static void intel_lt_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+	intel_psr_resume(intel_dp);
+	intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);
+}
+
 void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 			     const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	bool lane_reversal = dig_port->lane_reversal;
 	u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
+	intel_wakeref_t wakeref = 0;
+
+	wakeref = intel_lt_phy_transaction_begin(encoder);
 
 	/* 1. Enable MacCLK at default 162 MHz frequency. */
 	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
@@ -169,29 +262,34 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,
 	 * encoded rate and encoded mode.
 	 */
-	/*
-	 * 5. Program the PHY internal PLL registers over PHY message bus for the desired
-	 * frequency and protocol type
-	 */
-	/* 6. Use the P2P transaction flow */
-	/*
-	 * 6.1. Set the PHY VDR register 0xCC4[Rate Control VDR Update] = 1 over PHY message
-	 * bus for Owned PHY Lanes.
-	 */
-	/*
-	 * 6.2. Poll for P2P Transaction Ready = "1" and read the MAC message bus VDR register
-	 * at offset 0xC00 for Owned PHY Lanes.
-	 */
-	/* 6.3. Clear P2P transaction Ready bit. */
-	/* 7. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0. */
-	/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
-	/*
-	 * 9. Follow the Display Voltage Frequency Switching - Sequence Before Frequency Change.
-	 * We handle this step in bxt_set_cdclk()
-	 */
-	/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
-	/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
-	/* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */
+	if (intel_lt_phy_config_changed(encoder, crtc_state)) {
+		/*
+		 * 5. Program the PHY internal PLL registers over PHY message bus for the desired
+		 * frequency and protocol type
+		 */
+		/* 6. Use the P2P transaction flow */
+		/*
+		 * 6.1. Set the PHY VDR register 0xCC4[Rate Control VDR Update] = 1 over PHY message
+		 * bus for Owned PHY Lanes.
+		 */
+		/*
+		 * 6.2. Poll for P2P Transaction Ready = "1" and read the MAC message bus VDR
+		 * register at offset 0xC00 for Owned PHY Lanes*.
+		 */
+		/* 6.3. Clear P2P transaction Ready bit. */
+		/* 7. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0. */
+		/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
+		/*
+		 * 9. Follow the Display Voltage Frequency Switching - Sequence Before Frequency
+		 * Change. We handle this step in bxt_set_cdclk().
+		 */
+		/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
+		/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
+		/* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */
+	} else {
+		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), crtc_state->port_clock);
+	}
+
 	/* 13. Ungate the forward clock by setting PORT_CLOCK_CTL[Forward Clock Ungate] = 1. */
 	/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
 	/*
@@ -205,4 +303,6 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 	 * We handle this step in bxt_set_cdclk()
 	 */
 	/* 19. Move the PHY powerdown state to Active and program to enable/disable transmitters */
+
+	intel_lt_phy_transaction_end(encoder, wakeref);
 }
-- 
2.34.1

Re: [PATCH 06/25] drm/i915/ltphy: Read PHY_VDR_0_CONFIG register

[Murthy, Arun R]

On 15-10-2025 09:37, Suraj Kandpal wrote:
> Read PHY_VDR_0_CONFIG to check if there is any change in the register and
> decide based on that if some steps need to be executed or not.

Can using "some steps" be replaced with a proper seq/word? Something 
like if no change in PHY config then omit the P2P and port control 
configurations.

With the above correction
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>   This
> scenario only happens if the requested mode uses 1.62Gbps with DP mode
> since LT PHY defaults to this mode if any other mode is requested we
> need to follow the whole sequence.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_cx0_phy.c |   4 +-
>   drivers/gpu/drm/i915/display/intel_cx0_phy.h |   2 +
>   drivers/gpu/drm/i915/display/intel_lt_phy.c  | 146 ++++++++++++++++---
>   3 files changed, 127 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 8455d0725968..4e074754a78f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -271,8 +271,8 @@ static u8 __intel_cx0_read(struct intel_encoder *encoder,
>   	return 0;
>   }
>   
> -static u8 intel_cx0_read(struct intel_encoder *encoder,
> -			 u8 lane_mask, u16 addr)
> +u8 intel_cx0_read(struct intel_encoder *encoder,
> +		  u8 lane_mask, u16 addr)
>   {
>   	int lane = lane_mask_to_lane(lane_mask);
>   
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 8c9b97f0922d..b448ce936c37 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -46,6 +46,8 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
>   int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
>   void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
>   bool intel_cx0_is_hdmi_frl(u32 clock);
> +u8 intel_cx0_read(struct intel_encoder *encoder,
> +		  u8 lane_mask, u16 addr);
>   int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
>   void intel_cx0_pll_power_save_wa(struct intel_display *display);
>   void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 263e9780b55c..c2d5e4b82db5 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -6,6 +6,7 @@
>   #include <drm/drm_print.h>
>   
>   #include "i915_reg.h"
> +#include "i915_utils.h"
>   #include "intel_cx0_phy.h"
>   #include "intel_cx0_phy_regs.h"
>   #include "intel_de.h"
> @@ -13,12 +14,14 @@
>   #include "intel_display_types.h"
>   #include "intel_lt_phy.h"
>   #include "intel_lt_phy_regs.h"
> +#include "intel_psr.h"
>   #include "intel_tc.h"
>   
>   #define INTEL_LT_PHY_LANE0		BIT(0)
>   #define INTEL_LT_PHY_LANE1		BIT(1)
>   #define INTEL_LT_PHY_BOTH_LANES		(INTEL_LT_PHY_LANE1 |\
>   					 INTEL_LT_PHY_LANE0)
> +#define MODE_DP				3
>   
>   static u8 intel_lt_phy_get_owned_lane_mask(struct intel_encoder *encoder)
>   {
> @@ -31,6 +34,12 @@ static u8 intel_lt_phy_get_owned_lane_mask(struct intel_encoder *encoder)
>   		? INTEL_LT_PHY_BOTH_LANES : INTEL_LT_PHY_LANE0;
>   }
>   
> +static u8 intel_lt_phy_read(struct intel_encoder *encoder,
> +			    u8 lane_mask, u16 addr)
> +{
> +	return intel_cx0_read(encoder, lane_mask, addr);
> +}
> +
>   static void
>   intel_lt_phy_setup_powerdown(struct intel_encoder *encoder, u8 lane_count)
>   {
> @@ -148,12 +157,96 @@ intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
>   		     XELPDP_SSC_ENABLE_PLLB, val);
>   }
>   
> +static u32
> +intel_lt_phy_get_dp_clock(u8 rate)
> +{
> +	switch (rate) {
> +	case 0:
> +		return 162000;
> +	case 1:
> +		return 270000;
> +	case 2:
> +		return 540000;
> +	case 3:
> +		return 810000;
> +	case 4:
> +		return 216000;
> +	case 5:
> +		return 243000;
> +	case 6:
> +		return 324000;
> +	case 7:
> +		return 432000;
> +	case 8:
> +		return 1000000;
> +	case 9:
> +		return 1350000;
> +	case 10:
> +		return 2000000;
> +	case 11:
> +		return 675000;
> +	default:
> +		MISSING_CASE(rate);
> +		return 0;
> +	}
> +}
> +
> +static bool
> +intel_lt_phy_config_changed(struct intel_encoder *encoder,
> +			    const struct intel_crtc_state *crtc_state)
> +{
> +	u8 val, rate;
> +	u32 clock;
> +
> +	val = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,
> +				LT_PHY_VDR_0_CONFIG);
> +	rate = REG_FIELD_GET8(LT_PHY_VDR_RATE_ENCODING_MASK, val);
> +
> +	/*
> +	 * The only time we do not reconfigure the PLL is when we are
> +	 * using 1.62 Gbps clock since PHY PLL defaults to that
> +	 * otherwise we always need to reconfigure it.
> +	 */
> +	if (intel_crtc_has_dp_encoder(crtc_state)) {
> +		clock = intel_lt_phy_get_dp_clock(rate);
> +		if (crtc_state->port_clock == 1620000 && crtc_state->port_clock == clock)
> +			return false;
> +	}
> +
> +	return true;
> +}
> +
> +static intel_wakeref_t intel_lt_phy_transaction_begin(struct intel_encoder *encoder)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	intel_wakeref_t wakeref;
> +
> +	intel_psr_pause(intel_dp);
> +	wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF);
> +
> +	return wakeref;
> +}
> +
> +static void intel_lt_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> +	intel_psr_resume(intel_dp);
> +	intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);
> +}
> +
>   void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   			     const struct intel_crtc_state *crtc_state)
>   {
> +	struct intel_display *display = to_intel_display(encoder);
>   	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>   	bool lane_reversal = dig_port->lane_reversal;
>   	u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
> +	intel_wakeref_t wakeref = 0;
> +
> +	wakeref = intel_lt_phy_transaction_begin(encoder);
>   
>   	/* 1. Enable MacCLK at default 162 MHz frequency. */
>   	intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
> @@ -169,29 +262,34 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   	 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,
>   	 * encoded rate and encoded mode.
>   	 */
> -	/*
> -	 * 5. Program the PHY internal PLL registers over PHY message bus for the desired
> -	 * frequency and protocol type
> -	 */
> -	/* 6. Use the P2P transaction flow */
> -	/*
> -	 * 6.1. Set the PHY VDR register 0xCC4[Rate Control VDR Update] = 1 over PHY message
> -	 * bus for Owned PHY Lanes.
> -	 */
> -	/*
> -	 * 6.2. Poll for P2P Transaction Ready = "1" and read the MAC message bus VDR register
> -	 * at offset 0xC00 for Owned PHY Lanes.
> -	 */
> -	/* 6.3. Clear P2P transaction Ready bit. */
> -	/* 7. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0. */
> -	/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
> -	/*
> -	 * 9. Follow the Display Voltage Frequency Switching - Sequence Before Frequency Change.
> -	 * We handle this step in bxt_set_cdclk()
> -	 */
> -	/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
> -	/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
> -	/* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */
> +	if (intel_lt_phy_config_changed(encoder, crtc_state)) {
> +		/*
> +		 * 5. Program the PHY internal PLL registers over PHY message bus for the desired
> +		 * frequency and protocol type
> +		 */
> +		/* 6. Use the P2P transaction flow */
> +		/*
> +		 * 6.1. Set the PHY VDR register 0xCC4[Rate Control VDR Update] = 1 over PHY message
> +		 * bus for Owned PHY Lanes.
> +		 */
> +		/*
> +		 * 6.2. Poll for P2P Transaction Ready = "1" and read the MAC message bus VDR
> +		 * register at offset 0xC00 for Owned PHY Lanes*.
> +		 */
> +		/* 6.3. Clear P2P transaction Ready bit. */
> +		/* 7. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0. */
> +		/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
> +		/*
> +		 * 9. Follow the Display Voltage Frequency Switching - Sequence Before Frequency
> +		 * Change. We handle this step in bxt_set_cdclk().
> +		 */
> +		/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
> +		/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
> +		/* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */
> +	} else {
> +		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), crtc_state->port_clock);
> +	}
> +
>   	/* 13. Ungate the forward clock by setting PORT_CLOCK_CTL[Forward Clock Ungate] = 1. */
>   	/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
>   	/*
> @@ -205,4 +303,6 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   	 * We handle this step in bxt_set_cdclk()
>   	 */
>   	/* 19. Move the PHY powerdown state to Active and program to enable/disable transmitters */
> +
> +	intel_lt_phy_transaction_end(encoder, wakeref);
>   }

[PATCH 07/25] drm/i915/ltphy: Add LT Phy Programming recipe tables

[Suraj Kandpal]

Add the LT Phy programming recipe tables for eDP, DP & HDMI and a
function to use the correct table.

Bspec: 74667
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c     |  29 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  11 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 992 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |   5 +
 4 files changed, 1036 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index f969c5399a51..8c3ef5867a12 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -17,6 +17,7 @@
 #include "intel_display_types.h"
 #include "intel_dpio_phy.h"
 #include "intel_dpll.h"
+#include "intel_lt_phy.h"
 #include "intel_lvds.h"
 #include "intel_lvds_regs.h"
 #include "intel_panel.h"
@@ -1232,6 +1233,26 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
 	return 0;
 }
 
+static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state,
+				      struct intel_crtc *crtc)
+{
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	struct intel_encoder *encoder =
+		intel_get_crtc_new_encoder(state, crtc_state);
+	int ret;
+
+	ret = intel_lt_phy_pll_calc_state(crtc_state, encoder);
+	if (ret)
+		return ret;
+
+	/* TODO: Do the readback via intel_compute_shared_dplls() */
+
+	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
+
+	return 0;
+}
+
 static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -1691,6 +1712,10 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
 	return 0;
 }
 
+static const struct intel_dpll_global_funcs xe3plpd_dpll_funcs = {
+	.crtc_compute_clock = xe3plpd_crtc_compute_clock,
+};
+
 static const struct intel_dpll_global_funcs mtl_dpll_funcs = {
 	.crtc_compute_clock = mtl_crtc_compute_clock,
 };
@@ -1789,7 +1814,9 @@ int intel_dpll_crtc_get_dpll(struct intel_atomic_state *state,
 void
 intel_dpll_init_clock_hook(struct intel_display *display)
 {
-	if (DISPLAY_VER(display) >= 14)
+	if (HAS_LT_PHY(display))
+		display->funcs.dpll = &xe3plpd_dpll_funcs;
+	else if (DISPLAY_VER(display) >= 14)
 		display->funcs.dpll = &mtl_dpll_funcs;
 	else if (display->platform.dg2)
 		display->funcs.dpll = &dg2_dpll_funcs;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index f131bdd1c975..6183da90b28d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -267,6 +267,16 @@ struct intel_cx0pll_state {
 	bool tbt_mode;
 };
 
+struct intel_lt_phy_pll_state {
+	u32 clock; /* in kHz */
+	u8 addr_msb[13];
+	u8 addr_lsb[13];
+	u8 data[13][4];
+	u8 config[3];
+	bool ssc_enabled;
+	bool tbt_mode;
+};
+
 struct intel_dpll_hw_state {
 	union {
 		struct i9xx_dpll_hw_state i9xx;
@@ -276,6 +286,7 @@ struct intel_dpll_hw_state {
 		struct icl_dpll_hw_state icl;
 		struct intel_mpllb_state mpllb;
 		struct intel_cx0pll_state cx0pll;
+		struct intel_lt_phy_pll_state ltpll;
 	};
 };
 
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index c2d5e4b82db5..c8910262efb6 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -12,6 +12,7 @@
 #include "intel_de.h"
 #include "intel_display.h"
 #include "intel_display_types.h"
+#include "intel_dpll_mgr.h"
 #include "intel_lt_phy.h"
 #include "intel_lt_phy_regs.h"
 #include "intel_psr.h"
@@ -23,6 +24,957 @@
 					 INTEL_LT_PHY_LANE0)
 #define MODE_DP				3
 
+static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_rbr = {
+	.clock = 162000,
+	.config = {
+		0x83,
+		0x2d,
+		0x0,
+	},
+	.addr_msb = {
+		0x87,
+		0x87,
+		0x87,
+		0x87,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x5,  0xa,  0x2a, 0x20 },
+		{ 0x80, 0x0,  0x0,  0x0  },
+		{ 0x4,  0x4,  0x82, 0x28 },
+		{ 0xfa, 0x16, 0x83, 0x11 },
+		{ 0x80, 0x0f, 0xf9, 0x53 },
+		{ 0x84, 0x26, 0x5,  0x4  },
+		{ 0x0,  0xe0, 0x1,  0x0  },
+		{ 0x4b, 0x48, 0x0,  0x0  },
+		{ 0x27, 0x8,  0x0,  0x0  },
+		{ 0x5a, 0x13, 0x29, 0x13 },
+		{ 0x0,  0x5b, 0xe0, 0x0a },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr1 = {
+	.clock = 270000,
+	.config = {
+		0x8b,
+		0x2d,
+		0x0,
+	},
+	.addr_msb = {
+		0x87,
+		0x87,
+		0x87,
+		0x87,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x3,  0xca, 0x34, 0xa0 },
+		{ 0xe0, 0x0,  0x0,  0x0  },
+		{ 0x5,  0x4,  0x81, 0xad },
+		{ 0xfa, 0x11, 0x83, 0x11 },
+		{ 0x80, 0x0f, 0xf9, 0x53 },
+		{ 0x84, 0x26, 0x7,  0x4  },
+		{ 0x0,  0xe0, 0x1,  0x0  },
+		{ 0x43, 0x48, 0x0,  0x0  },
+		{ 0x27, 0x8,  0x0,  0x0  },
+		{ 0x5a, 0x13, 0x29, 0x13 },
+		{ 0x0,  0x5b, 0xe0, 0x0d },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr2 = {
+	.clock = 540000,
+	.config = {
+		0x93,
+		0x2d,
+		0x0,
+	},
+	.addr_msb = {
+		0x87,
+		0x87,
+		0x87,
+		0x87,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x1,  0x4d, 0x34, 0xa0 },
+		{ 0xe0, 0x0,  0x0,  0x0  },
+		{ 0xa,  0x4,  0x81, 0xda },
+		{ 0xfa, 0x11, 0x83, 0x11 },
+		{ 0x80, 0x0f, 0xf9, 0x53 },
+		{ 0x84, 0x26, 0x7,  0x4  },
+		{ 0x0,  0xe0, 0x1,  0x0  },
+		{ 0x43, 0x48, 0x0,  0x0  },
+		{ 0x27, 0x8,  0x0,  0x0  },
+		{ 0x5a, 0x13, 0x29, 0x13 },
+		{ 0x0,  0x5b, 0xe0, 0x0d },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr3 = {
+	.clock = 810000,
+	.config = {
+		0x9b,
+		0x2d,
+		0x0,
+	},
+	.addr_msb = {
+		0x87,
+		0x87,
+		0x87,
+		0x87,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x1,  0x4a, 0x34, 0xa0 },
+		{ 0xe0, 0x0,  0x0,  0x0  },
+		{ 0x5,  0x4,  0x80, 0xa8 },
+		{ 0xfa, 0x11, 0x83, 0x11 },
+		{ 0x80, 0x0f, 0xf9, 0x53 },
+		{ 0x84, 0x26, 0x7,  0x4  },
+		{ 0x0,  0xe0, 0x1,  0x0  },
+		{ 0x43, 0x48, 0x0,  0x0  },
+		{ 0x27, 0x8,  0x0,  0x0  },
+		{ 0x5a, 0x13, 0x29, 0x13 },
+		{ 0x0,  0x5b, 0xe0, 0x0d },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr10 = {
+	.clock = 1000000,
+	.config = {
+		0x43,
+		0x2d,
+		0x0,
+	},
+	.addr_msb = {
+		0x85,
+		0x85,
+		0x85,
+		0x85,
+		0x86,
+		0x86,
+		0x86,
+		0x86,
+		0x86,
+		0x86,
+		0x86,
+		0x86,
+		0x86,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x1,  0xa,  0x20, 0x80 },
+		{ 0x6a, 0xaa, 0xaa, 0xab },
+		{ 0x0,  0x3,  0x4,  0x94 },
+		{ 0xfa, 0x1c, 0x83, 0x11 },
+		{ 0x80, 0x0f, 0xf9, 0x53 },
+		{ 0x84, 0x26, 0x4,  0x4  },
+		{ 0x0,  0xe0, 0x1,  0x0  },
+		{ 0x45, 0x48, 0x0,  0x0  },
+		{ 0x27, 0x8,  0x0,  0x0  },
+		{ 0x5a, 0x14, 0x2a, 0x14 },
+		{ 0x0,  0x5b, 0xe0, 0x8  },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr13_5 = {
+	.clock = 1350000,
+	.config = {
+		0xcb,
+		0x2d,
+		0x0,
+	},
+	.addr_msb = {
+		0x87,
+		0x87,
+		0x87,
+		0x87,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x2,  0x9,  0x2b, 0xe0 },
+		{ 0x90, 0x0,  0x0,  0x0  },
+		{ 0x8,  0x4,  0x80, 0xe0 },
+		{ 0xfa, 0x15, 0x83, 0x11 },
+		{ 0x80, 0x0f, 0xf9, 0x53 },
+		{ 0x84, 0x26, 0x6,  0x4  },
+		{ 0x0,  0xe0, 0x1,  0x0  },
+		{ 0x49, 0x48, 0x0,  0x0  },
+		{ 0x27, 0x8,  0x0,  0x0  },
+		{ 0x5a, 0x13, 0x29, 0x13 },
+		{ 0x0,  0x57, 0xe0, 0x0c },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr20 = {
+	.clock = 2000000,
+	.config = {
+		0x53,
+		0x2d,
+		0x0,
+	},
+	.addr_msb = {
+		0x85,
+		0x85,
+		0x85,
+		0x85,
+		0x86,
+		0x86,
+		0x86,
+		0x86,
+		0x86,
+		0x86,
+		0x86,
+		0x86,
+		0x86,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x1,  0xa,  0x20, 0x80 },
+		{ 0x6a, 0xaa, 0xaa, 0xab },
+		{ 0x0,  0x3,  0x4,  0x94 },
+		{ 0xfa, 0x1c, 0x83, 0x11 },
+		{ 0x80, 0x0f, 0xf9, 0x53 },
+		{ 0x84, 0x26, 0x4,  0x4  },
+		{ 0x0,  0xe0, 0x1,  0x0  },
+		{ 0x45, 0x48, 0x0,  0x0  },
+		{ 0x27, 0x8,  0x0,  0x0  },
+		{ 0x5a, 0x14, 0x2a, 0x14 },
+		{ 0x0,  0x5b, 0xe0, 0x8  },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state * const xe3plpd_lt_dp_tables[] = {
+	&xe3plpd_lt_dp_rbr,
+	&xe3plpd_lt_dp_hbr1,
+	&xe3plpd_lt_dp_hbr2,
+	&xe3plpd_lt_dp_hbr3,
+	&xe3plpd_lt_dp_uhbr10,
+	&xe3plpd_lt_dp_uhbr13_5,
+	&xe3plpd_lt_dp_uhbr20,
+	NULL,
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_16 = {
+	.clock = 216000,
+	.config = {
+		0xa3,
+		0x2d,
+		0x1,
+	},
+	.addr_msb = {
+		0x87,
+		0x87,
+		0x87,
+		0x87,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x3,  0xca, 0x2a, 0x20 },
+		{ 0x80, 0x0,  0x0,  0x0  },
+		{ 0x6,  0x4,  0x81, 0xbc },
+		{ 0xfa, 0x16, 0x83, 0x11 },
+		{ 0x80, 0x0f, 0xf9, 0x53 },
+		{ 0x84, 0x26, 0x5,  0x4  },
+		{ 0x0,  0xe0, 0x1,  0x0  },
+		{ 0x4b, 0x48, 0x0,  0x0  },
+		{ 0x27, 0x8,  0x0,  0x0  },
+		{ 0x5a, 0x13, 0x29, 0x13 },
+		{ 0x0,  0x5b, 0xe0, 0x0a },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_43 = {
+	.clock = 243000,
+	.config = {
+		0xab,
+		0x2d,
+		0x1,
+	},
+	.addr_msb = {
+		0x87,
+		0x87,
+		0x87,
+		0x87,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x3,  0xca, 0x2f, 0x60 },
+		{ 0xb0, 0x0,  0x0,  0x0  },
+		{ 0x6,  0x4,  0x81, 0xbc },
+		{ 0xfa, 0x13, 0x83, 0x11 },
+		{ 0x80, 0x0f, 0xf9, 0x53 },
+		{ 0x84, 0x26, 0x6,  0x4  },
+		{ 0x0,  0xe0, 0x1,  0x0  },
+		{ 0x47, 0x48, 0x0,  0x0  },
+		{ 0x0,  0x0,  0x0,  0x0  },
+		{ 0x5a, 0x13, 0x29, 0x13 },
+		{ 0x0,  0x5b, 0xe0, 0x0c },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_3_24 = {
+	.clock = 324000,
+	.config = {
+		0xb3,
+		0x2d,
+		0x1,
+	},
+	.addr_msb = {
+		0x87,
+		0x87,
+		0x87,
+		0x87,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x2,  0x8a, 0x2a, 0x20 },
+		{ 0x80, 0x0,  0x0,  0x0  },
+		{ 0x6,  0x4,  0x81, 0x28 },
+		{ 0xfa, 0x16, 0x83, 0x11 },
+		{ 0x80, 0x0f, 0xf9, 0x53 },
+		{ 0x84, 0x26, 0x5,  0x4  },
+		{ 0x0,  0xe0, 0x1,  0x0  },
+		{ 0x4b, 0x48, 0x0,  0x0  },
+		{ 0x27, 0x8,  0x0,  0x0  },
+		{ 0x5a, 0x13, 0x29, 0x13 },
+		{ 0x0,  0x5b, 0xe0, 0x0a },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_4_32 = {
+	.clock = 432000,
+	.config = {
+		0xbb,
+		0x2d,
+		0x1,
+	},
+	.addr_msb = {
+		0x87,
+		0x87,
+		0x87,
+		0x87,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x1,  0x4d, 0x2a, 0x20 },
+		{ 0x80, 0x0,  0x0,  0x0  },
+		{ 0xc,  0x4,  0x81, 0xbc },
+		{ 0xfa, 0x16, 0x83, 0x11 },
+		{ 0x80, 0x0f, 0xf9, 0x53 },
+		{ 0x84, 0x26, 0x5,  0x4  },
+		{ 0x0,  0xe0, 0x1,  0x0  },
+		{ 0x4b, 0x48, 0x0,  0x0  },
+		{ 0x27, 0x8,  0x0,  0x0  },
+		{ 0x5a, 0x13, 0x29, 0x13 },
+		{ 0x0,  0x5b, 0xe0, 0x0a },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_6_75 = {
+	.clock = 675000,
+	.config = {
+		0xdb,
+		0x2d,
+		0x1,
+	},
+	.addr_msb = {
+		0x87,
+		0x87,
+		0x87,
+		0x87,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x1,  0x4a, 0x2b, 0xe0 },
+		{ 0x90, 0x0,  0x0,  0x0  },
+		{ 0x6,  0x4,  0x80, 0xa8 },
+		{ 0xfa, 0x15, 0x83, 0x11 },
+		{ 0x80, 0x0f, 0xf9, 0x53 },
+		{ 0x84, 0x26, 0x6,  0x4  },
+		{ 0x0,  0xe0, 0x1,  0x0  },
+		{ 0x49, 0x48, 0x0,  0x0  },
+		{ 0x27, 0x8,  0x0,  0x0  },
+		{ 0x5a, 0x13, 0x29, 0x13 },
+		{ 0x0,  0x57, 0xe0, 0x0c },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state * const xe3plpd_lt_edp_tables[] = {
+	&xe3plpd_lt_dp_rbr,
+	&xe3plpd_lt_edp_2_16,
+	&xe3plpd_lt_edp_2_43,
+	&xe3plpd_lt_dp_hbr1,
+	&xe3plpd_lt_edp_3_24,
+	&xe3plpd_lt_edp_4_32,
+	&xe3plpd_lt_dp_hbr2,
+	&xe3plpd_lt_edp_6_75,
+	&xe3plpd_lt_dp_hbr3,
+	NULL,
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_252 = {
+	.clock = 25200,
+	.config = {
+		0x84,
+		0x2d,
+		0x0,
+	},
+	.addr_msb = {
+		0x87,
+		0x87,
+		0x87,
+		0x87,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x0c, 0x15, 0x27, 0x60 },
+		{ 0x0,  0x0,  0x0,  0x0  },
+		{ 0x8,  0x4,  0x98, 0x28 },
+		{ 0x42, 0x0,  0x84, 0x10 },
+		{ 0x80, 0x0f, 0xd9, 0xb5 },
+		{ 0x86, 0x0,  0x0,  0x0  },
+		{ 0x1,  0xa0, 0x1,  0x0  },
+		{ 0x4b, 0x0,  0x0,  0x0  },
+		{ 0x28, 0x0,  0x0,  0x0  },
+		{ 0x0,  0x14, 0x2a, 0x14 },
+		{ 0x0,  0x0,  0x0,  0x0  },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_272 = {
+	.clock = 27200,
+	.config = {
+		0x84,
+		0x2d,
+		0x0,
+	},
+	.addr_msb = {
+		0x87,
+		0x87,
+		0x87,
+		0x87,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x0b, 0x15, 0x26, 0xa0 },
+		{ 0x60, 0x0,  0x0,  0x0  },
+		{ 0x8,  0x4,  0x96, 0x28 },
+		{ 0xfa, 0x0c, 0x84, 0x11 },
+		{ 0x80, 0x0f, 0xd9, 0x53 },
+		{ 0x86, 0x0,  0x0,  0x0  },
+		{ 0x1,  0xa0, 0x1,  0x0  },
+		{ 0x4b, 0x0,  0x0,  0x0  },
+		{ 0x28, 0x0,  0x0,  0x0  },
+		{ 0x0,  0x14, 0x2a, 0x14 },
+		{ 0x0,  0x0,  0x0,  0x0  },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_742p5 = {
+	.clock = 74250,
+	.config = {
+		0x84,
+		0x2d,
+		0x0,
+	},
+	.addr_msb = {
+		0x87,
+		0x87,
+		0x87,
+		0x87,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x4,  0x15, 0x26, 0xa0 },
+		{ 0x60, 0x0,  0x0,  0x0  },
+		{ 0x8,  0x4,  0x88, 0x28 },
+		{ 0xfa, 0x0c, 0x84, 0x11 },
+		{ 0x80, 0x0f, 0xd9, 0x53 },
+		{ 0x86, 0x0,  0x0,  0x0  },
+		{ 0x1,  0xa0, 0x1,  0x0  },
+		{ 0x4b, 0x0,  0x0,  0x0  },
+		{ 0x28, 0x0,  0x0,  0x0  },
+		{ 0x0,  0x14, 0x2a, 0x14 },
+		{ 0x0,  0x0,  0x0,  0x0  },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_1p485 = {
+	.clock = 148500,
+	.config = {
+		0x84,
+		0x2d,
+		0x0,
+	},
+	.addr_msb = {
+		0x87,
+		0x87,
+		0x87,
+		0x87,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x2,  0x15, 0x26, 0xa0 },
+		{ 0x60, 0x0,  0x0,  0x0  },
+		{ 0x8,  0x4,  0x84, 0x28 },
+		{ 0xfa, 0x0c, 0x84, 0x11 },
+		{ 0x80, 0x0f, 0xd9, 0x53 },
+		{ 0x86, 0x0,  0x0,  0x0  },
+		{ 0x1,  0xa0, 0x1,  0x0  },
+		{ 0x4b, 0x0,  0x0,  0x0  },
+		{ 0x28, 0x0,  0x0,  0x0  },
+		{ 0x0,  0x14, 0x2a, 0x14 },
+		{ 0x0,  0x0,  0x0,  0x0  },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_5p94 = {
+	.clock = 594000,
+	.config = {
+		0x84,
+		0x2d,
+		0x0,
+	},
+	.addr_msb = {
+		0x87,
+		0x87,
+		0x87,
+		0x87,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x0,  0x95, 0x26, 0xa0 },
+		{ 0x60, 0x0,  0x0,  0x0  },
+		{ 0x8,  0x4,  0x81, 0x28 },
+		{ 0xfa, 0x0c, 0x84, 0x11 },
+		{ 0x80, 0x0f, 0xd9, 0x53 },
+		{ 0x86, 0x0,  0x0,  0x0  },
+		{ 0x1,  0xa0, 0x1,  0x0  },
+		{ 0x4b, 0x0,  0x0,  0x0  },
+		{ 0x28, 0x0,  0x0,  0x0  },
+		{ 0x0,  0x14, 0x2a, 0x14 },
+		{ 0x0,  0x0,  0x0,  0x0  },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state * const xe3plpd_lt_hdmi_tables[] = {
+	&xe3plpd_lt_hdmi_252,
+	&xe3plpd_lt_hdmi_272,
+	&xe3plpd_lt_hdmi_742p5,
+	&xe3plpd_lt_hdmi_1p485,
+	&xe3plpd_lt_hdmi_5p94,
+	NULL,
+};
+
 static u8 intel_lt_phy_get_owned_lane_mask(struct intel_encoder *encoder)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
@@ -237,6 +1189,46 @@ static void intel_lt_phy_transaction_end(struct intel_encoder *encoder, intel_wa
 	intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);
 }
 
+static const struct intel_lt_phy_pll_state * const *
+intel_lt_phy_pll_tables_get(struct intel_crtc_state *crtc_state,
+			    struct intel_encoder *encoder)
+{
+	if (intel_crtc_has_dp_encoder(crtc_state)) {
+		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+			return xe3plpd_lt_edp_tables;
+
+		return xe3plpd_lt_dp_tables;
+	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+		return xe3plpd_lt_hdmi_tables;
+	}
+
+	MISSING_CASE(encoder->type);
+	return NULL;
+}
+
+int
+intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
+			    struct intel_encoder *encoder)
+{
+	const struct intel_lt_phy_pll_state * const *tables;
+	int i;
+
+	tables = intel_lt_phy_pll_tables_get(crtc_state, encoder);
+	if (!tables)
+		return -EINVAL;
+
+	for (i = 0; tables[i]; i++) {
+		if (crtc_state->port_clock == tables[i]->clock) {
+			crtc_state->dpll_hw_state.ltpll = *tables[i];
+			return 0;
+		}
+	}
+
+	/* TODO: Add a function to compute the data for HDMI TMDS*/
+
+	return -EINVAL;
+}
+
 void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 			     const struct intel_crtc_state *crtc_state)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index bd3ff3007e1d..3f255c9b0f96 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -13,5 +13,10 @@ struct intel_crtc_state;
 
 void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 			     const struct intel_crtc_state *crtc_state);
+int
+intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
+			    struct intel_encoder *encoder);
+
+#define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35)
 
 #endif /* __INTEL_LT_PHY_H__ */
-- 
2.34.1

Re: [PATCH 07/25] drm/i915/ltphy: Add LT Phy Programming recipe tables

[Murthy, Arun R]

On 15-10-2025 09:37, Suraj Kandpal wrote:
> Add the LT Phy programming recipe tables for eDP, DP & HDMI and a
> function to use the correct table.
>
> Bspec: 74667
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Look good!
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
-------------------
> ---
>   drivers/gpu/drm/i915/display/intel_dpll.c     |  29 +-
>   drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  11 +
>   drivers/gpu/drm/i915/display/intel_lt_phy.c   | 992 ++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_lt_phy.h   |   5 +
>   4 files changed, 1036 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index f969c5399a51..8c3ef5867a12 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -17,6 +17,7 @@
>   #include "intel_display_types.h"
>   #include "intel_dpio_phy.h"
>   #include "intel_dpll.h"
> +#include "intel_lt_phy.h"
>   #include "intel_lvds.h"
>   #include "intel_lvds_regs.h"
>   #include "intel_panel.h"
> @@ -1232,6 +1233,26 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
>   	return 0;
>   }
>   
> +static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state,
> +				      struct intel_crtc *crtc)
> +{
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	struct intel_encoder *encoder =
> +		intel_get_crtc_new_encoder(state, crtc_state);
> +	int ret;
> +
> +	ret = intel_lt_phy_pll_calc_state(crtc_state, encoder);
> +	if (ret)
> +		return ret;
> +
> +	/* TODO: Do the readback via intel_compute_shared_dplls() */
> +
> +	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> +
> +	return 0;
> +}
> +
>   static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
> @@ -1691,6 +1712,10 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
>   	return 0;
>   }
>   
> +static const struct intel_dpll_global_funcs xe3plpd_dpll_funcs = {
> +	.crtc_compute_clock = xe3plpd_crtc_compute_clock,
> +};
> +
>   static const struct intel_dpll_global_funcs mtl_dpll_funcs = {
>   	.crtc_compute_clock = mtl_crtc_compute_clock,
>   };
> @@ -1789,7 +1814,9 @@ int intel_dpll_crtc_get_dpll(struct intel_atomic_state *state,
>   void
>   intel_dpll_init_clock_hook(struct intel_display *display)
>   {
> -	if (DISPLAY_VER(display) >= 14)
> +	if (HAS_LT_PHY(display))
> +		display->funcs.dpll = &xe3plpd_dpll_funcs;
> +	else if (DISPLAY_VER(display) >= 14)
>   		display->funcs.dpll = &mtl_dpll_funcs;
>   	else if (display->platform.dg2)
>   		display->funcs.dpll = &dg2_dpll_funcs;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index f131bdd1c975..6183da90b28d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -267,6 +267,16 @@ struct intel_cx0pll_state {
>   	bool tbt_mode;
>   };
>   
> +struct intel_lt_phy_pll_state {
> +	u32 clock; /* in kHz */
> +	u8 addr_msb[13];
> +	u8 addr_lsb[13];
> +	u8 data[13][4];
> +	u8 config[3];
> +	bool ssc_enabled;
> +	bool tbt_mode;
> +};
> +
>   struct intel_dpll_hw_state {
>   	union {
>   		struct i9xx_dpll_hw_state i9xx;
> @@ -276,6 +286,7 @@ struct intel_dpll_hw_state {
>   		struct icl_dpll_hw_state icl;
>   		struct intel_mpllb_state mpllb;
>   		struct intel_cx0pll_state cx0pll;
> +		struct intel_lt_phy_pll_state ltpll;
>   	};
>   };
>   
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index c2d5e4b82db5..c8910262efb6 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -12,6 +12,7 @@
>   #include "intel_de.h"
>   #include "intel_display.h"
>   #include "intel_display_types.h"
> +#include "intel_dpll_mgr.h"
>   #include "intel_lt_phy.h"
>   #include "intel_lt_phy_regs.h"
>   #include "intel_psr.h"
> @@ -23,6 +24,957 @@
>   					 INTEL_LT_PHY_LANE0)
>   #define MODE_DP				3
>   
> +static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_rbr = {
> +	.clock = 162000,
> +	.config = {
> +		0x83,
> +		0x2d,
> +		0x0,
> +	},
> +	.addr_msb = {
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +	},
> +	.addr_lsb = {
> +		0x10,
> +		0x0c,
> +		0x14,
> +		0xe4,
> +		0x0c,
> +		0x10,
> +		0x14,
> +		0x18,
> +		0x48,
> +		0x40,
> +		0x4c,
> +		0x24,
> +		0x44,
> +	},
> +	.data = {
> +		{ 0x0,  0x4c, 0x2,  0x0  },
> +		{ 0x5,  0xa,  0x2a, 0x20 },
> +		{ 0x80, 0x0,  0x0,  0x0  },
> +		{ 0x4,  0x4,  0x82, 0x28 },
> +		{ 0xfa, 0x16, 0x83, 0x11 },
> +		{ 0x80, 0x0f, 0xf9, 0x53 },
> +		{ 0x84, 0x26, 0x5,  0x4  },
> +		{ 0x0,  0xe0, 0x1,  0x0  },
> +		{ 0x4b, 0x48, 0x0,  0x0  },
> +		{ 0x27, 0x8,  0x0,  0x0  },
> +		{ 0x5a, 0x13, 0x29, 0x13 },
> +		{ 0x0,  0x5b, 0xe0, 0x0a },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +	},
> +};
> +
> +static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr1 = {
> +	.clock = 270000,
> +	.config = {
> +		0x8b,
> +		0x2d,
> +		0x0,
> +	},
> +	.addr_msb = {
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +	},
> +	.addr_lsb = {
> +		0x10,
> +		0x0c,
> +		0x14,
> +		0xe4,
> +		0x0c,
> +		0x10,
> +		0x14,
> +		0x18,
> +		0x48,
> +		0x40,
> +		0x4c,
> +		0x24,
> +		0x44,
> +	},
> +	.data = {
> +		{ 0x0,  0x4c, 0x2,  0x0  },
> +		{ 0x3,  0xca, 0x34, 0xa0 },
> +		{ 0xe0, 0x0,  0x0,  0x0  },
> +		{ 0x5,  0x4,  0x81, 0xad },
> +		{ 0xfa, 0x11, 0x83, 0x11 },
> +		{ 0x80, 0x0f, 0xf9, 0x53 },
> +		{ 0x84, 0x26, 0x7,  0x4  },
> +		{ 0x0,  0xe0, 0x1,  0x0  },
> +		{ 0x43, 0x48, 0x0,  0x0  },
> +		{ 0x27, 0x8,  0x0,  0x0  },
> +		{ 0x5a, 0x13, 0x29, 0x13 },
> +		{ 0x0,  0x5b, 0xe0, 0x0d },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +	},
> +};
> +
> +static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr2 = {
> +	.clock = 540000,
> +	.config = {
> +		0x93,
> +		0x2d,
> +		0x0,
> +	},
> +	.addr_msb = {
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +	},
> +	.addr_lsb = {
> +		0x10,
> +		0x0c,
> +		0x14,
> +		0xe4,
> +		0x0c,
> +		0x10,
> +		0x14,
> +		0x18,
> +		0x48,
> +		0x40,
> +		0x4c,
> +		0x24,
> +		0x44,
> +	},
> +	.data = {
> +		{ 0x0,  0x4c, 0x2,  0x0  },
> +		{ 0x1,  0x4d, 0x34, 0xa0 },
> +		{ 0xe0, 0x0,  0x0,  0x0  },
> +		{ 0xa,  0x4,  0x81, 0xda },
> +		{ 0xfa, 0x11, 0x83, 0x11 },
> +		{ 0x80, 0x0f, 0xf9, 0x53 },
> +		{ 0x84, 0x26, 0x7,  0x4  },
> +		{ 0x0,  0xe0, 0x1,  0x0  },
> +		{ 0x43, 0x48, 0x0,  0x0  },
> +		{ 0x27, 0x8,  0x0,  0x0  },
> +		{ 0x5a, 0x13, 0x29, 0x13 },
> +		{ 0x0,  0x5b, 0xe0, 0x0d },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +	},
> +};
> +
> +static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr3 = {
> +	.clock = 810000,
> +	.config = {
> +		0x9b,
> +		0x2d,
> +		0x0,
> +	},
> +	.addr_msb = {
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +	},
> +	.addr_lsb = {
> +		0x10,
> +		0x0c,
> +		0x14,
> +		0xe4,
> +		0x0c,
> +		0x10,
> +		0x14,
> +		0x18,
> +		0x48,
> +		0x40,
> +		0x4c,
> +		0x24,
> +		0x44,
> +	},
> +	.data = {
> +		{ 0x0,  0x4c, 0x2,  0x0  },
> +		{ 0x1,  0x4a, 0x34, 0xa0 },
> +		{ 0xe0, 0x0,  0x0,  0x0  },
> +		{ 0x5,  0x4,  0x80, 0xa8 },
> +		{ 0xfa, 0x11, 0x83, 0x11 },
> +		{ 0x80, 0x0f, 0xf9, 0x53 },
> +		{ 0x84, 0x26, 0x7,  0x4  },
> +		{ 0x0,  0xe0, 0x1,  0x0  },
> +		{ 0x43, 0x48, 0x0,  0x0  },
> +		{ 0x27, 0x8,  0x0,  0x0  },
> +		{ 0x5a, 0x13, 0x29, 0x13 },
> +		{ 0x0,  0x5b, 0xe0, 0x0d },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +	},
> +};
> +
> +static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr10 = {
> +	.clock = 1000000,
> +	.config = {
> +		0x43,
> +		0x2d,
> +		0x0,
> +	},
> +	.addr_msb = {
> +		0x85,
> +		0x85,
> +		0x85,
> +		0x85,
> +		0x86,
> +		0x86,
> +		0x86,
> +		0x86,
> +		0x86,
> +		0x86,
> +		0x86,
> +		0x86,
> +		0x86,
> +	},
> +	.addr_lsb = {
> +		0x10,
> +		0x0c,
> +		0x14,
> +		0xe4,
> +		0x0c,
> +		0x10,
> +		0x14,
> +		0x18,
> +		0x48,
> +		0x40,
> +		0x4c,
> +		0x24,
> +		0x44,
> +	},
> +	.data = {
> +		{ 0x0,  0x4c, 0x2,  0x0  },
> +		{ 0x1,  0xa,  0x20, 0x80 },
> +		{ 0x6a, 0xaa, 0xaa, 0xab },
> +		{ 0x0,  0x3,  0x4,  0x94 },
> +		{ 0xfa, 0x1c, 0x83, 0x11 },
> +		{ 0x80, 0x0f, 0xf9, 0x53 },
> +		{ 0x84, 0x26, 0x4,  0x4  },
> +		{ 0x0,  0xe0, 0x1,  0x0  },
> +		{ 0x45, 0x48, 0x0,  0x0  },
> +		{ 0x27, 0x8,  0x0,  0x0  },
> +		{ 0x5a, 0x14, 0x2a, 0x14 },
> +		{ 0x0,  0x5b, 0xe0, 0x8  },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +	},
> +};
> +
> +static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr13_5 = {
> +	.clock = 1350000,
> +	.config = {
> +		0xcb,
> +		0x2d,
> +		0x0,
> +	},
> +	.addr_msb = {
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +	},
> +	.addr_lsb = {
> +		0x10,
> +		0x0c,
> +		0x14,
> +		0xe4,
> +		0x0c,
> +		0x10,
> +		0x14,
> +		0x18,
> +		0x48,
> +		0x40,
> +		0x4c,
> +		0x24,
> +		0x44,
> +	},
> +	.data = {
> +		{ 0x0,  0x4c, 0x2,  0x0  },
> +		{ 0x2,  0x9,  0x2b, 0xe0 },
> +		{ 0x90, 0x0,  0x0,  0x0  },
> +		{ 0x8,  0x4,  0x80, 0xe0 },
> +		{ 0xfa, 0x15, 0x83, 0x11 },
> +		{ 0x80, 0x0f, 0xf9, 0x53 },
> +		{ 0x84, 0x26, 0x6,  0x4  },
> +		{ 0x0,  0xe0, 0x1,  0x0  },
> +		{ 0x49, 0x48, 0x0,  0x0  },
> +		{ 0x27, 0x8,  0x0,  0x0  },
> +		{ 0x5a, 0x13, 0x29, 0x13 },
> +		{ 0x0,  0x57, 0xe0, 0x0c },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +	},
> +};
> +
> +static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr20 = {
> +	.clock = 2000000,
> +	.config = {
> +		0x53,
> +		0x2d,
> +		0x0,
> +	},
> +	.addr_msb = {
> +		0x85,
> +		0x85,
> +		0x85,
> +		0x85,
> +		0x86,
> +		0x86,
> +		0x86,
> +		0x86,
> +		0x86,
> +		0x86,
> +		0x86,
> +		0x86,
> +		0x86,
> +	},
> +	.addr_lsb = {
> +		0x10,
> +		0x0c,
> +		0x14,
> +		0xe4,
> +		0x0c,
> +		0x10,
> +		0x14,
> +		0x18,
> +		0x48,
> +		0x40,
> +		0x4c,
> +		0x24,
> +		0x44,
> +	},
> +	.data = {
> +		{ 0x0,  0x4c, 0x2,  0x0  },
> +		{ 0x1,  0xa,  0x20, 0x80 },
> +		{ 0x6a, 0xaa, 0xaa, 0xab },
> +		{ 0x0,  0x3,  0x4,  0x94 },
> +		{ 0xfa, 0x1c, 0x83, 0x11 },
> +		{ 0x80, 0x0f, 0xf9, 0x53 },
> +		{ 0x84, 0x26, 0x4,  0x4  },
> +		{ 0x0,  0xe0, 0x1,  0x0  },
> +		{ 0x45, 0x48, 0x0,  0x0  },
> +		{ 0x27, 0x8,  0x0,  0x0  },
> +		{ 0x5a, 0x14, 0x2a, 0x14 },
> +		{ 0x0,  0x5b, 0xe0, 0x8  },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +	},
> +};
> +
> +static const struct intel_lt_phy_pll_state * const xe3plpd_lt_dp_tables[] = {
> +	&xe3plpd_lt_dp_rbr,
> +	&xe3plpd_lt_dp_hbr1,
> +	&xe3plpd_lt_dp_hbr2,
> +	&xe3plpd_lt_dp_hbr3,
> +	&xe3plpd_lt_dp_uhbr10,
> +	&xe3plpd_lt_dp_uhbr13_5,
> +	&xe3plpd_lt_dp_uhbr20,
> +	NULL,
> +};
> +
> +static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_16 = {
> +	.clock = 216000,
> +	.config = {
> +		0xa3,
> +		0x2d,
> +		0x1,
> +	},
> +	.addr_msb = {
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +	},
> +	.addr_lsb = {
> +		0x10,
> +		0x0c,
> +		0x14,
> +		0xe4,
> +		0x0c,
> +		0x10,
> +		0x14,
> +		0x18,
> +		0x48,
> +		0x40,
> +		0x4c,
> +		0x24,
> +		0x44,
> +	},
> +	.data = {
> +		{ 0x0,  0x4c, 0x2,  0x0  },
> +		{ 0x3,  0xca, 0x2a, 0x20 },
> +		{ 0x80, 0x0,  0x0,  0x0  },
> +		{ 0x6,  0x4,  0x81, 0xbc },
> +		{ 0xfa, 0x16, 0x83, 0x11 },
> +		{ 0x80, 0x0f, 0xf9, 0x53 },
> +		{ 0x84, 0x26, 0x5,  0x4  },
> +		{ 0x0,  0xe0, 0x1,  0x0  },
> +		{ 0x4b, 0x48, 0x0,  0x0  },
> +		{ 0x27, 0x8,  0x0,  0x0  },
> +		{ 0x5a, 0x13, 0x29, 0x13 },
> +		{ 0x0,  0x5b, 0xe0, 0x0a },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +	},
> +};
> +
> +static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_43 = {
> +	.clock = 243000,
> +	.config = {
> +		0xab,
> +		0x2d,
> +		0x1,
> +	},
> +	.addr_msb = {
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +	},
> +	.addr_lsb = {
> +		0x10,
> +		0x0c,
> +		0x14,
> +		0xe4,
> +		0x0c,
> +		0x10,
> +		0x14,
> +		0x18,
> +		0x48,
> +		0x40,
> +		0x4c,
> +		0x24,
> +		0x44,
> +	},
> +	.data = {
> +		{ 0x0,  0x4c, 0x2,  0x0  },
> +		{ 0x3,  0xca, 0x2f, 0x60 },
> +		{ 0xb0, 0x0,  0x0,  0x0  },
> +		{ 0x6,  0x4,  0x81, 0xbc },
> +		{ 0xfa, 0x13, 0x83, 0x11 },
> +		{ 0x80, 0x0f, 0xf9, 0x53 },
> +		{ 0x84, 0x26, 0x6,  0x4  },
> +		{ 0x0,  0xe0, 0x1,  0x0  },
> +		{ 0x47, 0x48, 0x0,  0x0  },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +		{ 0x5a, 0x13, 0x29, 0x13 },
> +		{ 0x0,  0x5b, 0xe0, 0x0c },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +	},
> +};
> +
> +static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_3_24 = {
> +	.clock = 324000,
> +	.config = {
> +		0xb3,
> +		0x2d,
> +		0x1,
> +	},
> +	.addr_msb = {
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +	},
> +	.addr_lsb = {
> +		0x10,
> +		0x0c,
> +		0x14,
> +		0xe4,
> +		0x0c,
> +		0x10,
> +		0x14,
> +		0x18,
> +		0x48,
> +		0x40,
> +		0x4c,
> +		0x24,
> +		0x44,
> +	},
> +	.data = {
> +		{ 0x0,  0x4c, 0x2,  0x0  },
> +		{ 0x2,  0x8a, 0x2a, 0x20 },
> +		{ 0x80, 0x0,  0x0,  0x0  },
> +		{ 0x6,  0x4,  0x81, 0x28 },
> +		{ 0xfa, 0x16, 0x83, 0x11 },
> +		{ 0x80, 0x0f, 0xf9, 0x53 },
> +		{ 0x84, 0x26, 0x5,  0x4  },
> +		{ 0x0,  0xe0, 0x1,  0x0  },
> +		{ 0x4b, 0x48, 0x0,  0x0  },
> +		{ 0x27, 0x8,  0x0,  0x0  },
> +		{ 0x5a, 0x13, 0x29, 0x13 },
> +		{ 0x0,  0x5b, 0xe0, 0x0a },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +	},
> +};
> +
> +static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_4_32 = {
> +	.clock = 432000,
> +	.config = {
> +		0xbb,
> +		0x2d,
> +		0x1,
> +	},
> +	.addr_msb = {
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +	},
> +	.addr_lsb = {
> +		0x10,
> +		0x0c,
> +		0x14,
> +		0xe4,
> +		0x0c,
> +		0x10,
> +		0x14,
> +		0x18,
> +		0x48,
> +		0x40,
> +		0x4c,
> +		0x24,
> +		0x44,
> +	},
> +	.data = {
> +		{ 0x0,  0x4c, 0x2,  0x0  },
> +		{ 0x1,  0x4d, 0x2a, 0x20 },
> +		{ 0x80, 0x0,  0x0,  0x0  },
> +		{ 0xc,  0x4,  0x81, 0xbc },
> +		{ 0xfa, 0x16, 0x83, 0x11 },
> +		{ 0x80, 0x0f, 0xf9, 0x53 },
> +		{ 0x84, 0x26, 0x5,  0x4  },
> +		{ 0x0,  0xe0, 0x1,  0x0  },
> +		{ 0x4b, 0x48, 0x0,  0x0  },
> +		{ 0x27, 0x8,  0x0,  0x0  },
> +		{ 0x5a, 0x13, 0x29, 0x13 },
> +		{ 0x0,  0x5b, 0xe0, 0x0a },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +	},
> +};
> +
> +static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_6_75 = {
> +	.clock = 675000,
> +	.config = {
> +		0xdb,
> +		0x2d,
> +		0x1,
> +	},
> +	.addr_msb = {
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +	},
> +	.addr_lsb = {
> +		0x10,
> +		0x0c,
> +		0x14,
> +		0xe4,
> +		0x0c,
> +		0x10,
> +		0x14,
> +		0x18,
> +		0x48,
> +		0x40,
> +		0x4c,
> +		0x24,
> +		0x44,
> +	},
> +	.data = {
> +		{ 0x0,  0x4c, 0x2,  0x0  },
> +		{ 0x1,  0x4a, 0x2b, 0xe0 },
> +		{ 0x90, 0x0,  0x0,  0x0  },
> +		{ 0x6,  0x4,  0x80, 0xa8 },
> +		{ 0xfa, 0x15, 0x83, 0x11 },
> +		{ 0x80, 0x0f, 0xf9, 0x53 },
> +		{ 0x84, 0x26, 0x6,  0x4  },
> +		{ 0x0,  0xe0, 0x1,  0x0  },
> +		{ 0x49, 0x48, 0x0,  0x0  },
> +		{ 0x27, 0x8,  0x0,  0x0  },
> +		{ 0x5a, 0x13, 0x29, 0x13 },
> +		{ 0x0,  0x57, 0xe0, 0x0c },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +	},
> +};
> +
> +static const struct intel_lt_phy_pll_state * const xe3plpd_lt_edp_tables[] = {
> +	&xe3plpd_lt_dp_rbr,
> +	&xe3plpd_lt_edp_2_16,
> +	&xe3plpd_lt_edp_2_43,
> +	&xe3plpd_lt_dp_hbr1,
> +	&xe3plpd_lt_edp_3_24,
> +	&xe3plpd_lt_edp_4_32,
> +	&xe3plpd_lt_dp_hbr2,
> +	&xe3plpd_lt_edp_6_75,
> +	&xe3plpd_lt_dp_hbr3,
> +	NULL,
> +};
> +
> +static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_252 = {
> +	.clock = 25200,
> +	.config = {
> +		0x84,
> +		0x2d,
> +		0x0,
> +	},
> +	.addr_msb = {
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +	},
> +	.addr_lsb = {
> +		0x10,
> +		0x0c,
> +		0x14,
> +		0xe4,
> +		0x0c,
> +		0x10,
> +		0x14,
> +		0x18,
> +		0x48,
> +		0x40,
> +		0x4c,
> +		0x24,
> +		0x44,
> +	},
> +	.data = {
> +		{ 0x0,  0x4c, 0x2,  0x0  },
> +		{ 0x0c, 0x15, 0x27, 0x60 },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +		{ 0x8,  0x4,  0x98, 0x28 },
> +		{ 0x42, 0x0,  0x84, 0x10 },
> +		{ 0x80, 0x0f, 0xd9, 0xb5 },
> +		{ 0x86, 0x0,  0x0,  0x0  },
> +		{ 0x1,  0xa0, 0x1,  0x0  },
> +		{ 0x4b, 0x0,  0x0,  0x0  },
> +		{ 0x28, 0x0,  0x0,  0x0  },
> +		{ 0x0,  0x14, 0x2a, 0x14 },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +	},
> +};
> +
> +static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_272 = {
> +	.clock = 27200,
> +	.config = {
> +		0x84,
> +		0x2d,
> +		0x0,
> +	},
> +	.addr_msb = {
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +	},
> +	.addr_lsb = {
> +		0x10,
> +		0x0c,
> +		0x14,
> +		0xe4,
> +		0x0c,
> +		0x10,
> +		0x14,
> +		0x18,
> +		0x48,
> +		0x40,
> +		0x4c,
> +		0x24,
> +		0x44,
> +	},
> +	.data = {
> +		{ 0x0,  0x4c, 0x2,  0x0  },
> +		{ 0x0b, 0x15, 0x26, 0xa0 },
> +		{ 0x60, 0x0,  0x0,  0x0  },
> +		{ 0x8,  0x4,  0x96, 0x28 },
> +		{ 0xfa, 0x0c, 0x84, 0x11 },
> +		{ 0x80, 0x0f, 0xd9, 0x53 },
> +		{ 0x86, 0x0,  0x0,  0x0  },
> +		{ 0x1,  0xa0, 0x1,  0x0  },
> +		{ 0x4b, 0x0,  0x0,  0x0  },
> +		{ 0x28, 0x0,  0x0,  0x0  },
> +		{ 0x0,  0x14, 0x2a, 0x14 },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +	},
> +};
> +
> +static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_742p5 = {
> +	.clock = 74250,
> +	.config = {
> +		0x84,
> +		0x2d,
> +		0x0,
> +	},
> +	.addr_msb = {
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +	},
> +	.addr_lsb = {
> +		0x10,
> +		0x0c,
> +		0x14,
> +		0xe4,
> +		0x0c,
> +		0x10,
> +		0x14,
> +		0x18,
> +		0x48,
> +		0x40,
> +		0x4c,
> +		0x24,
> +		0x44,
> +	},
> +	.data = {
> +		{ 0x0,  0x4c, 0x2,  0x0  },
> +		{ 0x4,  0x15, 0x26, 0xa0 },
> +		{ 0x60, 0x0,  0x0,  0x0  },
> +		{ 0x8,  0x4,  0x88, 0x28 },
> +		{ 0xfa, 0x0c, 0x84, 0x11 },
> +		{ 0x80, 0x0f, 0xd9, 0x53 },
> +		{ 0x86, 0x0,  0x0,  0x0  },
> +		{ 0x1,  0xa0, 0x1,  0x0  },
> +		{ 0x4b, 0x0,  0x0,  0x0  },
> +		{ 0x28, 0x0,  0x0,  0x0  },
> +		{ 0x0,  0x14, 0x2a, 0x14 },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +	},
> +};
> +
> +static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_1p485 = {
> +	.clock = 148500,
> +	.config = {
> +		0x84,
> +		0x2d,
> +		0x0,
> +	},
> +	.addr_msb = {
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +	},
> +	.addr_lsb = {
> +		0x10,
> +		0x0c,
> +		0x14,
> +		0xe4,
> +		0x0c,
> +		0x10,
> +		0x14,
> +		0x18,
> +		0x48,
> +		0x40,
> +		0x4c,
> +		0x24,
> +		0x44,
> +	},
> +	.data = {
> +		{ 0x0,  0x4c, 0x2,  0x0  },
> +		{ 0x2,  0x15, 0x26, 0xa0 },
> +		{ 0x60, 0x0,  0x0,  0x0  },
> +		{ 0x8,  0x4,  0x84, 0x28 },
> +		{ 0xfa, 0x0c, 0x84, 0x11 },
> +		{ 0x80, 0x0f, 0xd9, 0x53 },
> +		{ 0x86, 0x0,  0x0,  0x0  },
> +		{ 0x1,  0xa0, 0x1,  0x0  },
> +		{ 0x4b, 0x0,  0x0,  0x0  },
> +		{ 0x28, 0x0,  0x0,  0x0  },
> +		{ 0x0,  0x14, 0x2a, 0x14 },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +	},
> +};
> +
> +static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_5p94 = {
> +	.clock = 594000,
> +	.config = {
> +		0x84,
> +		0x2d,
> +		0x0,
> +	},
> +	.addr_msb = {
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x87,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +		0x88,
> +	},
> +	.addr_lsb = {
> +		0x10,
> +		0x0c,
> +		0x14,
> +		0xe4,
> +		0x0c,
> +		0x10,
> +		0x14,
> +		0x18,
> +		0x48,
> +		0x40,
> +		0x4c,
> +		0x24,
> +		0x44,
> +	},
> +	.data = {
> +		{ 0x0,  0x4c, 0x2,  0x0  },
> +		{ 0x0,  0x95, 0x26, 0xa0 },
> +		{ 0x60, 0x0,  0x0,  0x0  },
> +		{ 0x8,  0x4,  0x81, 0x28 },
> +		{ 0xfa, 0x0c, 0x84, 0x11 },
> +		{ 0x80, 0x0f, 0xd9, 0x53 },
> +		{ 0x86, 0x0,  0x0,  0x0  },
> +		{ 0x1,  0xa0, 0x1,  0x0  },
> +		{ 0x4b, 0x0,  0x0,  0x0  },
> +		{ 0x28, 0x0,  0x0,  0x0  },
> +		{ 0x0,  0x14, 0x2a, 0x14 },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +		{ 0x0,  0x0,  0x0,  0x0  },
> +	},
> +};
> +
> +static const struct intel_lt_phy_pll_state * const xe3plpd_lt_hdmi_tables[] = {
> +	&xe3plpd_lt_hdmi_252,
> +	&xe3plpd_lt_hdmi_272,
> +	&xe3plpd_lt_hdmi_742p5,
> +	&xe3plpd_lt_hdmi_1p485,
> +	&xe3plpd_lt_hdmi_5p94,
> +	NULL,
> +};
> +
>   static u8 intel_lt_phy_get_owned_lane_mask(struct intel_encoder *encoder)
>   {
>   	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> @@ -237,6 +1189,46 @@ static void intel_lt_phy_transaction_end(struct intel_encoder *encoder, intel_wa
>   	intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);
>   }
>   
> +static const struct intel_lt_phy_pll_state * const *
> +intel_lt_phy_pll_tables_get(struct intel_crtc_state *crtc_state,
> +			    struct intel_encoder *encoder)
> +{
> +	if (intel_crtc_has_dp_encoder(crtc_state)) {
> +		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> +			return xe3plpd_lt_edp_tables;
> +
> +		return xe3plpd_lt_dp_tables;
> +	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> +		return xe3plpd_lt_hdmi_tables;
> +	}
> +
> +	MISSING_CASE(encoder->type);
> +	return NULL;
> +}
> +
> +int
> +intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
> +			    struct intel_encoder *encoder)
> +{
> +	const struct intel_lt_phy_pll_state * const *tables;
> +	int i;
> +
> +	tables = intel_lt_phy_pll_tables_get(crtc_state, encoder);
> +	if (!tables)
> +		return -EINVAL;
> +
> +	for (i = 0; tables[i]; i++) {
> +		if (crtc_state->port_clock == tables[i]->clock) {
> +			crtc_state->dpll_hw_state.ltpll = *tables[i];
> +			return 0;
> +		}
> +	}
> +
> +	/* TODO: Add a function to compute the data for HDMI TMDS*/
> +
> +	return -EINVAL;
> +}
> +
>   void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   			     const struct intel_crtc_state *crtc_state)
>   {
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index bd3ff3007e1d..3f255c9b0f96 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -13,5 +13,10 @@ struct intel_crtc_state;
>   
>   void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   			     const struct intel_crtc_state *crtc_state);
> +int
> +intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
> +			    struct intel_encoder *encoder);
> +
> +#define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35)
>   
>   #endif /* __INTEL_LT_PHY_H__ */

[PATCH 08/25] drm/i915/ltphy: Program the VDR PLL registers for LT PHY

[Suraj Kandpal]

Calculate the tables which needs to be used and program it in
the specified VDR register space. Everything is done over Lane0
as mentioned in the tables.

Bspec: 68862, 74500
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c |  7 ++--
 drivers/gpu/drm/i915/display/intel_cx0_phy.h |  5 +++
 drivers/gpu/drm/i915/display/intel_lt_phy.c  | 38 ++++++++++++++++++++
 3 files changed, 45 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 4e074754a78f..c50233f17bc6 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -23,9 +23,6 @@
 #include "intel_snps_hdmi_pll.h"
 #include "intel_tc.h"
 
-#define MB_WRITE_COMMITTED      true
-#define MB_WRITE_UNCOMMITTED    false
-
 #define for_each_cx0_lane_in_mask(__lane_mask, __lane) \
 	for ((__lane) = 0; (__lane) < 2; (__lane)++) \
 		for_each_if((__lane_mask) & BIT(__lane))
@@ -359,8 +356,8 @@ static void __intel_cx0_write(struct intel_encoder *encoder,
 		     "PHY %c Write %04x failed after %d retries.\n", phy_name(phy), addr, i);
 }
 
-static void intel_cx0_write(struct intel_encoder *encoder,
-			    u8 lane_mask, u16 addr, u8 data, bool committed)
+void intel_cx0_write(struct intel_encoder *encoder,
+		     u8 lane_mask, u16 addr, u8 data, bool committed)
 {
 	int lane;
 
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index b448ce936c37..283be36d5dff 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -8,6 +8,9 @@
 
 #include <linux/types.h>
 
+#define MB_WRITE_COMMITTED      true
+#define MB_WRITE_UNCOMMITTED    false
+
 enum icl_port_dpll_id;
 struct intel_atomic_state;
 struct intel_c10pll_state;
@@ -48,6 +51,8 @@ void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
 bool intel_cx0_is_hdmi_frl(u32 clock);
 u8 intel_cx0_read(struct intel_encoder *encoder,
 		  u8 lane_mask, u16 addr);
+void intel_cx0_write(struct intel_encoder *encoder,
+		     u8 lane_mask, u16 addr, u8 data, bool committed);
 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
 void intel_cx0_pll_power_save_wa(struct intel_display *display);
 void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index c8910262efb6..9380ba530901 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -992,6 +992,12 @@ static u8 intel_lt_phy_read(struct intel_encoder *encoder,
 	return intel_cx0_read(encoder, lane_mask, addr);
 }
 
+static void intel_lt_phy_write(struct intel_encoder *encoder,
+			       u8 lane_mask, u16 addr, u8 data, bool committed)
+{
+	intel_cx0_write(encoder, lane_mask, addr, data, committed);
+}
+
 static void
 intel_lt_phy_setup_powerdown(struct intel_encoder *encoder, u8 lane_count)
 {
@@ -1229,6 +1235,36 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 	return -EINVAL;
 }
 
+static void
+intel_lt_phy_program_pll(struct intel_encoder *encoder,
+			 const struct intel_crtc_state *crtc_state)
+{
+	u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
+	int i, j, k;
+
+	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_0_CONFIG,
+			   crtc_state->dpll_hw_state.ltpll.config[0], MB_WRITE_COMMITTED);
+	intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG,
+			   crtc_state->dpll_hw_state.ltpll.config[1], MB_WRITE_COMMITTED);
+	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_2_CONFIG,
+			   crtc_state->dpll_hw_state.ltpll.config[2], MB_WRITE_COMMITTED);
+
+	for (i = 0; i <= 12; i++) {
+		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_MSB(i),
+				   crtc_state->dpll_hw_state.ltpll.addr_msb[i],
+				   MB_WRITE_COMMITTED);
+		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_LSB(i),
+				   crtc_state->dpll_hw_state.ltpll.addr_lsb[i],
+				   MB_WRITE_COMMITTED);
+
+		for (j = 3, k = 0; j >= 0; j--, k++)
+			intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
+					   LT_PHY_VDR_X_DATAY(i, j),
+					   crtc_state->dpll_hw_state.ltpll.data[i][k],
+					   MB_WRITE_COMMITTED);
+	}
+}
+
 void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 			     const struct intel_crtc_state *crtc_state)
 {
@@ -1259,6 +1295,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 		 * 5. Program the PHY internal PLL registers over PHY message bus for the desired
 		 * frequency and protocol type
 		 */
+		intel_lt_phy_program_pll(encoder, crtc_state);
+
 		/* 6. Use the P2P transaction flow */
 		/*
 		 * 6.1. Set the PHY VDR register 0xCC4[Rate Control VDR Update] = 1 over PHY message
-- 
2.34.1

Re: [PATCH 08/25] drm/i915/ltphy: Program the VDR PLL registers for LT PHY

[Murthy, Arun R]

On 15-10-2025 09:38, Suraj Kandpal wrote:
> Calculate the tables which needs to be used and program it in

We dont do any calculation of the tables, its just getting the table 
with pre-filled swings.

Upon reframing the commit msg
Reviewd-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

> the specified VDR register space. Everything is done over Lane0
> as mentioned in the tables.
>
> Bspec: 68862, 74500
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_cx0_phy.c |  7 ++--
>   drivers/gpu/drm/i915/display/intel_cx0_phy.h |  5 +++
>   drivers/gpu/drm/i915/display/intel_lt_phy.c  | 38 ++++++++++++++++++++
>   3 files changed, 45 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 4e074754a78f..c50233f17bc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -23,9 +23,6 @@
>   #include "intel_snps_hdmi_pll.h"
>   #include "intel_tc.h"
>   
> -#define MB_WRITE_COMMITTED      true
> -#define MB_WRITE_UNCOMMITTED    false
> -
>   #define for_each_cx0_lane_in_mask(__lane_mask, __lane) \
>   	for ((__lane) = 0; (__lane) < 2; (__lane)++) \
>   		for_each_if((__lane_mask) & BIT(__lane))
> @@ -359,8 +356,8 @@ static void __intel_cx0_write(struct intel_encoder *encoder,
>   		     "PHY %c Write %04x failed after %d retries.\n", phy_name(phy), addr, i);
>   }
>   
> -static void intel_cx0_write(struct intel_encoder *encoder,
> -			    u8 lane_mask, u16 addr, u8 data, bool committed)
> +void intel_cx0_write(struct intel_encoder *encoder,
> +		     u8 lane_mask, u16 addr, u8 data, bool committed)
>   {
>   	int lane;
>   
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index b448ce936c37..283be36d5dff 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -8,6 +8,9 @@
>   
>   #include <linux/types.h>
>   
> +#define MB_WRITE_COMMITTED      true
> +#define MB_WRITE_UNCOMMITTED    false
> +
>   enum icl_port_dpll_id;
>   struct intel_atomic_state;
>   struct intel_c10pll_state;
> @@ -48,6 +51,8 @@ void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
>   bool intel_cx0_is_hdmi_frl(u32 clock);
>   u8 intel_cx0_read(struct intel_encoder *encoder,
>   		  u8 lane_mask, u16 addr);
> +void intel_cx0_write(struct intel_encoder *encoder,
> +		     u8 lane_mask, u16 addr, u8 data, bool committed);
>   int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
>   void intel_cx0_pll_power_save_wa(struct intel_display *display);
>   void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index c8910262efb6..9380ba530901 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -992,6 +992,12 @@ static u8 intel_lt_phy_read(struct intel_encoder *encoder,
>   	return intel_cx0_read(encoder, lane_mask, addr);
>   }
>   
> +static void intel_lt_phy_write(struct intel_encoder *encoder,
> +			       u8 lane_mask, u16 addr, u8 data, bool committed)
> +{
> +	intel_cx0_write(encoder, lane_mask, addr, data, committed);
> +}
> +
>   static void
>   intel_lt_phy_setup_powerdown(struct intel_encoder *encoder, u8 lane_count)
>   {
> @@ -1229,6 +1235,36 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
>   	return -EINVAL;
>   }
>   
> +static void
> +intel_lt_phy_program_pll(struct intel_encoder *encoder,
> +			 const struct intel_crtc_state *crtc_state)
> +{
> +	u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
> +	int i, j, k;
> +
> +	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_0_CONFIG,
> +			   crtc_state->dpll_hw_state.ltpll.config[0], MB_WRITE_COMMITTED);
> +	intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG,
> +			   crtc_state->dpll_hw_state.ltpll.config[1], MB_WRITE_COMMITTED);
> +	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_2_CONFIG,
> +			   crtc_state->dpll_hw_state.ltpll.config[2], MB_WRITE_COMMITTED);
> +
> +	for (i = 0; i <= 12; i++) {
> +		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_MSB(i),
> +				   crtc_state->dpll_hw_state.ltpll.addr_msb[i],
> +				   MB_WRITE_COMMITTED);
> +		intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_LSB(i),
> +				   crtc_state->dpll_hw_state.ltpll.addr_lsb[i],
> +				   MB_WRITE_COMMITTED);
> +
> +		for (j = 3, k = 0; j >= 0; j--, k++)
> +			intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
> +					   LT_PHY_VDR_X_DATAY(i, j),
> +					   crtc_state->dpll_hw_state.ltpll.data[i][k],
> +					   MB_WRITE_COMMITTED);
> +	}
> +}
> +
>   void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   			     const struct intel_crtc_state *crtc_state)
>   {
> @@ -1259,6 +1295,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   		 * 5. Program the PHY internal PLL registers over PHY message bus for the desired
>   		 * frequency and protocol type
>   		 */
> +		intel_lt_phy_program_pll(encoder, crtc_state);
> +
>   		/* 6. Use the P2P transaction flow */
>   		/*
>   		 * 6.1. Set the PHY VDR register 0xCC4[Rate Control VDR Update] = 1 over PHY messag

[PATCH 09/25] drm/i915/ltphy: Update the ltpll config table value for eDP

[Suraj Kandpal]

When we get the eDP tables we reuse dp tables for some data rates.
We need to modify the 3rd config value of this table to 1 instead
of 0 since that is the only difference in the dp and edp table for
that particular data rate.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 9380ba530901..8cd0009609d4 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1226,6 +1226,10 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 	for (i = 0; tables[i]; i++) {
 		if (crtc_state->port_clock == tables[i]->clock) {
 			crtc_state->dpll_hw_state.ltpll = *tables[i];
+			if (intel_crtc_has_dp_encoder(crtc_state)) {
+				if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+					crtc_state->dpll_hw_state.ltpll.config[2] = 1;
+			}
 			return 0;
 		}
 	}
-- 
2.34.1

Re: [PATCH 09/25] drm/i915/ltphy: Update the ltpll config table value for eDP

[Murthy, Arun R]

On 15-10-2025 09:38, Suraj Kandpal wrote:
> When we get the eDP tables we reuse dp tables for some data rates.
> We need to modify the 3rd config value of this table to 1 instead
> of 0 since that is the only difference in the dp and edp table for
> that particular data rate.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>   drivers/gpu/drm/i915/display/intel_lt_phy.c | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 9380ba530901..8cd0009609d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1226,6 +1226,10 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
>   	for (i = 0; tables[i]; i++) {
>   		if (crtc_state->port_clock == tables[i]->clock) {
>   			crtc_state->dpll_hw_state.ltpll = *tables[i];
> +			if (intel_crtc_has_dp_encoder(crtc_state)) {
> +				if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> +					crtc_state->dpll_hw_state.ltpll.config[2] = 1;
> +			}
>   			return 0;
>   		}
>   	}

[PATCH 10/25] drm/i915/ltphy: Enable SSC during port clock programming

[Suraj Kandpal]

We enable SSC when we program PORT_CLOCK_CTL register. We logically
determine if ssc is enabled or not while we calculate our state.

Bspec: 74492, 74667
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 26 +++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 8cd0009609d4..6ee785fbcad2 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -15,6 +15,7 @@
 #include "intel_dpll_mgr.h"
 #include "intel_lt_phy.h"
 #include "intel_lt_phy_regs.h"
+#include "intel_panel.h"
 #include "intel_psr.h"
 #include "intel_tc.h"
 
@@ -1109,6 +1110,12 @@ intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
 	else
 		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
 
+	 /* DP2.0 10G and 20G rates enable MPLLA*/
+	if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000)
+		val |= XELPDP_SSC_ENABLE_PLLA;
+	else
+		val |= crtc_state->dpll_hw_state.ltpll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
+
 	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
 		     XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
 		     XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_SSC_ENABLE_PLLA |
@@ -1212,6 +1219,23 @@ intel_lt_phy_pll_tables_get(struct intel_crtc_state *crtc_state,
 	return NULL;
 }
 
+static bool
+intel_lt_phy_pll_is_ssc_enabled(struct intel_crtc_state *crtc_state,
+				struct intel_encoder *encoder)
+{
+	struct intel_display *display = to_intel_display(encoder);
+
+	if (intel_crtc_has_dp_encoder(crtc_state)) {
+		if (intel_panel_use_ssc(display)) {
+			struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+			return (intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);
+		}
+	}
+
+	return false;
+}
+
 int
 intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 			    struct intel_encoder *encoder)
@@ -1230,6 +1254,8 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 				if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 					crtc_state->dpll_hw_state.ltpll.config[2] = 1;
 			}
+			crtc_state->dpll_hw_state.ltpll.ssc_enabled =
+				intel_lt_phy_pll_is_ssc_enabled(crtc_state, encoder);
 			return 0;
 		}
 	}
-- 
2.34.1

Re: [PATCH 10/25] drm/i915/ltphy: Enable SSC during port clock programming

[Murthy, Arun R]

On 15-10-2025 09:38, Suraj Kandpal wrote:
> We enable SSC when we program PORT_CLOCK_CTL register. We logically
> determine if ssc is enabled or not while we calculate our state.
>
> Bspec: 74492, 74667
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
-------------------

>   drivers/gpu/drm/i915/display/intel_lt_phy.c | 26 +++++++++++++++++++++
>   1 file changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 8cd0009609d4..6ee785fbcad2 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -15,6 +15,7 @@
>   #include "intel_dpll_mgr.h"
>   #include "intel_lt_phy.h"
>   #include "intel_lt_phy_regs.h"
> +#include "intel_panel.h"
>   #include "intel_psr.h"
>   #include "intel_tc.h"
>   
> @@ -1109,6 +1110,12 @@ intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
>   	else
>   		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
>   
> +	 /* DP2.0 10G and 20G rates enable MPLLA*/
> +	if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000)
> +		val |= XELPDP_SSC_ENABLE_PLLA;
> +	else
> +		val |= crtc_state->dpll_hw_state.ltpll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
> +
>   	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
>   		     XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
>   		     XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_SSC_ENABLE_PLLA |
> @@ -1212,6 +1219,23 @@ intel_lt_phy_pll_tables_get(struct intel_crtc_state *crtc_state,
>   	return NULL;
>   }
>   
> +static bool
> +intel_lt_phy_pll_is_ssc_enabled(struct intel_crtc_state *crtc_state,
> +				struct intel_encoder *encoder)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +
> +	if (intel_crtc_has_dp_encoder(crtc_state)) {
> +		if (intel_panel_use_ssc(display)) {
> +			struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> +			return (intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);
> +		}
> +	}
> +
> +	return false;
> +}
> +
>   int
>   intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
>   			    struct intel_encoder *encoder)
> @@ -1230,6 +1254,8 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
>   				if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
>   					crtc_state->dpll_hw_state.ltpll.config[2] = 1;
>   			}
> +			crtc_state->dpll_hw_state.ltpll.ssc_enabled =
> +				intel_lt_phy_pll_is_ssc_enabled(crtc_state, encoder);
>   			return 0;
>   		}
>   	}

[PATCH 11/25] drm/i915/ltphy: Add function to calculate LT PHY port clock

[Suraj Kandpal]

The current algorithm is very wrong and was made wrose with
changes in algorithm that were done. It needs to be rewritten
to be able to extract the correct values and get the right port clock.

Bspec: 74667
Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c   |  2 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 80 +++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h |  3 +
 3 files changed, 85 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 8c3ef5867a12..2e1f67be8eda 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1247,6 +1247,8 @@ static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state,
 		return ret;
 
 	/* TODO: Do the readback via intel_compute_shared_dplls() */
+	crtc_state->port_clock =
+			intel_lt_phy_calc_port_clock(encoder, crtc_state);
 
 	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 6ee785fbcad2..3aa8b3b345d3 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1236,6 +1236,86 @@ intel_lt_phy_pll_is_ssc_enabled(struct intel_crtc_state *crtc_state,
 	return false;
 }
 
+static int
+intel_lt_phy_calc_hdmi_port_clock(const struct intel_lt_phy_pll_state *lt_state)
+{
+#define DIV_CONST 10000000
+#define REF_CLK 38400
+#define REGVAL(i) (				\
+	(lt_state->data[i][3])		|	\
+	(lt_state->data[i][2] << 8)	|	\
+	(lt_state->data[i][1] << 16)	|	\
+	(lt_state->data[i][0] << 24)		\
+)
+
+	int clk = 0;
+	u32 d8, pll_reg_5, pll_reg_3, pll_reg_57, m2div_frac, m2div_int;
+	u64 temp0, temp1;
+
+	/*
+	 * d7 max val can be 10 so 4 bits
+	 * postdiv can be max 9 hence needs 4 bits
+	 * d8 since loop_cnt / 2 and loop count can be max 255
+	 * henc we needs  only 7 bits to represent but 8 bits is given.
+	 * d8 since loop_cnt / 2 and loop count can be max 255
+	 * hence we needs  only 7 bits to represent but 8 bits is given
+	 * PLL_reg57 = ((D7 << 24) + (postdiv << 15) + (D8 << 7) + D6_new);
+	 * PLL_reg57 = ((D7 << 24) + (postdiv << 15) + (D8 << 7) + D6_new);
+	 * d4 max val can be 256 so 9 bits
+	 * d3 can be max 9 hence needs 4 bits
+	 * d1 can be max 2 hence needs 2 bits
+	 * m2div can never be > 511 hence m2div_int
+	 * usees up to 9 bits but since it is shifted
+	 * by 5 in forward algo and then d1 is shifted to 15th bit
+	 * it has 10 bits.
+	 * PLL_reg3 = (uint32_t)((D4 << 21) + (D3 << 18) + (D1 << 15)+ (m2div_int << 5));
+	 */
+
+	pll_reg_5 = REGVAL(2);
+	pll_reg_3 = REGVAL(1);
+	pll_reg_57 = REGVAL(3);
+	m2div_frac = pll_reg_5;
+
+	d8 = (pll_reg_57 & REG_GENMASK(14, 7)) >> 7;
+	m2div_int = (pll_reg_3  & REG_GENMASK(14, 5)) >> 5;
+	temp0 = ((u64)m2div_frac * REF_CLK) >> 32;
+	temp1 = (u64)m2div_int * REF_CLK;
+	if (d8 == 0)
+		return 0;
+
+	clk = div_u64((temp1 + temp0), d8 * 10);
+
+	return clk;
+}
+
+int
+intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state)
+{
+	int clk;
+	const struct intel_lt_phy_pll_state *lt_state =
+		&crtc_state->dpll_hw_state.ltpll;
+	u8 mode, rate;
+
+	mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK,
+			      lt_state->config[0]);
+	/*
+	 * For edp/dp read the clock value from the tables
+	 * and return the clock as the algorithm used for
+	 * calculating the port clock does not exactly matches
+	 * with edp/dp clock.
+	 */
+	if (mode == MODE_DP) {
+		rate = REG_FIELD_GET8(LT_PHY_VDR_RATE_ENCODING_MASK,
+				      lt_state->config[0]);
+		clk = intel_lt_phy_get_dp_clock(rate);
+	} else {
+		clk = intel_lt_phy_calc_hdmi_port_clock(lt_state);
+	}
+
+	return clk;
+}
+
 int
 intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 			    struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 3f255c9b0f96..5b4e0d9c940f 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -10,12 +10,15 @@
 
 struct intel_encoder;
 struct intel_crtc_state;
+struct intel_lt_phy_pll_state;
 
 void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 			     const struct intel_crtc_state *crtc_state);
 int
 intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 			    struct intel_encoder *encoder);
+int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *crtc_state);
 
 #define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35)
 
-- 
2.34.1

[PATCH 12/25] drm/i915/ltphy: Program the P2P Transaction flow for LT Phy

[Suraj Kandpal]

Program the LT PHY P2P transaction which uses P2M cycle to get
get data fro Phy when it is ready and then go read the MAC register
from the MAC address space.

Bspec: 68966, 74497, 74483, 74500
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  10 +-
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   5 +
 .../gpu/drm/i915/display/intel_cx0_phy_regs.h |   1 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 115 ++++++++++++++++++
 .../gpu/drm/i915/display/intel_lt_phy_regs.h  |  15 +++
 5 files changed, 141 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index c50233f17bc6..b060a5007921 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -125,8 +125,8 @@ static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_w
 	intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);
 }
 
-static void intel_clear_response_ready_flag(struct intel_encoder *encoder,
-					    int lane)
+void intel_clear_response_ready_flag(struct intel_encoder *encoder,
+				     int lane)
 {
 	struct intel_display *display = to_intel_display(encoder);
 
@@ -135,7 +135,7 @@ static void intel_clear_response_ready_flag(struct intel_encoder *encoder,
 		     0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET);
 }
 
-static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
+void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	enum port port = encoder->port;
@@ -156,8 +156,8 @@ static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
 	intel_clear_response_ready_flag(encoder, lane);
 }
 
-static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
-				  int command, int lane, u32 *val)
+int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
+			   int command, int lane, u32 *val)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	enum port port = encoder->port;
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 283be36d5dff..a5446686b23b 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -22,6 +22,8 @@ struct intel_display;
 struct intel_encoder;
 struct intel_hdmi;
 
+void intel_clear_response_ready_flag(struct intel_encoder *encoder,
+				     int lane);
 bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
 void intel_mtl_pll_enable(struct intel_encoder *encoder,
 			  const struct intel_crtc_state *crtc_state);
@@ -53,6 +55,9 @@ u8 intel_cx0_read(struct intel_encoder *encoder,
 		  u8 lane_mask, u16 addr);
 void intel_cx0_write(struct intel_encoder *encoder,
 		     u8 lane_mask, u16 addr, u8 data, bool committed);
+int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
+			   int command, int lane, u32 *val);
+void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane);
 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
 void intel_cx0_pll_power_save_wa(struct intel_display *display);
 void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 114f6b2113db..cb2ab8442aa1 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -50,6 +50,7 @@
 #define   XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED	REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
 #define   XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED	REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2)
 #define   XELPDP_PORT_M2P_COMMAND_READ			REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3)
+#define   XELPDP_PORT_P2P_TRANSACTION_PENDING		REG_BIT(24)
 #define   XELPDP_PORT_M2P_DATA_MASK			REG_GENMASK(23, 16)
 #define   XELPDP_PORT_M2P_DATA(val)			REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val)
 #define   XELPDP_PORT_M2P_TRANSACTION_RESET		REG_BIT(15)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 3aa8b3b345d3..32a5a60fe92f 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -19,6 +19,10 @@
 #include "intel_psr.h"
 #include "intel_tc.h"
 
+#define for_each_lt_phy_lane_in_mask(__lane_mask, __lane) \
+	for ((__lane) = 0; (__lane) < 2; (__lane)++) \
+		for_each_if((__lane_mask) & BIT(__lane))
+
 #define INTEL_LT_PHY_LANE0		BIT(0)
 #define INTEL_LT_PHY_LANE1		BIT(1)
 #define INTEL_LT_PHY_BOTH_LANES		(INTEL_LT_PHY_LANE1 |\
@@ -999,6 +1003,113 @@ static void intel_lt_phy_write(struct intel_encoder *encoder,
 	intel_cx0_write(encoder, lane_mask, addr, data, committed);
 }
 
+static void intel_lt_phy_clear_status_p2p(struct intel_encoder *encoder,
+					  int lane)
+{
+	struct intel_display *display = to_intel_display(encoder);
+
+	intel_de_rmw(display,
+		     XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(encoder->port, lane),
+		     XELPDP_PORT_P2M_RESPONSE_READY, 0);
+}
+
+static void
+assert_dc_off(struct intel_display *display)
+{
+	bool enabled;
+
+	enabled = intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF);
+	drm_WARN_ON(display->drm, !enabled);
+}
+
+static int __intel_lt_phy_p2p_write_once(struct intel_encoder *encoder,
+					 int lane, u16 addr, u8 data,
+					 i915_reg_t mac_reg_addr,
+					 u8 expected_mac_val)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	enum port port = encoder->port;
+	enum phy phy = intel_encoder_to_phy(encoder);
+	int ack;
+	u32 val;
+
+	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
+				    XELPDP_PORT_P2P_TRANSACTION_PENDING,
+				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
+		drm_dbg_kms(display->drm,
+			    "PHY %c Timeout waiting for previous transaction to complete. Resetting bus.\n",
+			    phy_name(phy));
+		intel_cx0_bus_reset(encoder, lane);
+		return -ETIMEDOUT;
+	}
+
+	intel_de_rmw(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane), 0, 0);
+
+	intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
+		       XELPDP_PORT_P2P_TRANSACTION_PENDING |
+		       XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED |
+		       XELPDP_PORT_M2P_DATA(data) |
+		       XELPDP_PORT_M2P_ADDRESS(addr));
+
+	ack = intel_cx0_wait_for_ack(encoder, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val);
+	if (ack < 0)
+		return ack;
+
+	if (val & XELPDP_PORT_P2M_ERROR_SET) {
+		drm_dbg_kms(display->drm,
+			    "PHY %c Error occurred during P2P write command. Status: 0x%x\n",
+			    phy_name(phy), val);
+		intel_lt_phy_clear_status_p2p(encoder, lane);
+		intel_cx0_bus_reset(encoder, lane);
+		return -EINVAL;
+	}
+
+	/*
+	 * This needs to be added to give PHY time to set everything up this was a requirement
+	 * to get the display up and running.
+	 */
+	udelay(150);
+	intel_clear_response_ready_flag(encoder, lane);
+	intel_lt_phy_clear_status_p2p(encoder, lane);
+
+	return 0;
+}
+
+static void __intel_lt_phy_p2p_write(struct intel_encoder *encoder,
+				     int lane, u16 addr, u8 data,
+				     i915_reg_t mac_reg_addr,
+				     u8 expected_mac_val)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	enum phy phy = intel_encoder_to_phy(encoder);
+	int i, status;
+
+	assert_dc_off(display);
+
+	/* 3 tries is assumed to be enough to write successfully */
+	for (i = 0; i < 3; i++) {
+		status = __intel_lt_phy_p2p_write_once(encoder, lane, addr, data, mac_reg_addr,
+						       expected_mac_val);
+
+		if (status == 0)
+			return;
+	}
+
+	drm_err_once(display->drm,
+		     "PHY %c P2P Write %04x failed after %d retries.\n", phy_name(phy), addr, i);
+}
+
+static void intel_lt_phy_p2p_write(struct intel_encoder *encoder,
+				   u8 lane_mask, u16 addr, u8 data,
+				   i915_reg_t mac_reg_addr,
+				   u8 expected_mac_val)
+{
+	int lane;
+
+	for_each_lt_phy_lane_in_mask(lane_mask, lane)
+		__intel_lt_phy_p2p_write(encoder, lane, addr, data, mac_reg_addr, expected_mac_val);
+}
+
 static void
 intel_lt_phy_setup_powerdown(struct intel_encoder *encoder, u8 lane_count)
 {
@@ -1417,6 +1528,10 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 		 * register at offset 0xC00 for Owned PHY Lanes*.
 		 */
 		/* 6.3. Clear P2P transaction Ready bit. */
+		intel_lt_phy_p2p_write(encoder, owned_lane_mask, LT_PHY_RATE_UPDATE,
+				       LT_PHY_RATE_CONTROL_VDR_UPDATE, LT_PHY_MAC_VDR,
+				       LT_PHY_PCLKIN_GATE);
+
 		/* 7. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0. */
 		/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
 		/*
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
index a4aa2a3e0425..5fb4331c387f 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
@@ -9,12 +9,17 @@
 #include "i915_reg_defs.h"
 #include "intel_display_limits.h"
 
+#define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
 #define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
 #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
 #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
 #define XE3PLPD_RESET_START_LATENCY_US	10
 #define XE3PLPD_RESET_END_LATENCY_US	200
 
+/* LT Phy MAC Register */
+#define LT_PHY_MAC_VDR			_MMIO(0xC00)
+#define    LT_PHY_PCLKIN_GATE		REG_BIT8(0)
+
 /* LT Phy Vendor Register */
 #define LT_PHY_VDR_0_CONFIG	0xC02
 #define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
@@ -29,6 +34,7 @@
 #define LT_PHY_VDR_X_DATAY(idx, y)	((0xC06 + (3 - (y))) + 0x6 * (idx))
 
 #define LT_PHY_RATE_UPDATE		0xCC4
+#define    LT_PHY_RATE_CONTROL_VDR_UPDATE	REG_BIT8(0)
 
 #define _XE3PLPD_PORT_BUF_CTL5(idx)	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
 								 _XELPDP_PORT_BUF_CTL1_LN0_A, \
@@ -41,4 +47,13 @@
 #define  XE3PLPD_MACCLK_RATE_MASK	REG_GENMASK(4, 0)
 #define  XE3PLPD_MACCLK_RATE_DEF	REG_FIELD_PREP(XE3PLPD_MACCLK_RATE_MASK, 0x1F)
 
+#define _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(idx, lane)	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
+										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
+										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
+										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
+										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) \
+										 + 0x60 + (lane) * 0x4)
+#define XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(port, lane)	 _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(__xe2lpd_port_idx(port), \
+											    lane)
+#define   XE3LPD_PORT_P2M_ADDR_MASK			REG_GENMASK(11, 0)
 #endif /* __INTEL_LT_PHY_REGS_H__ */
-- 
2.34.1

Re: [PATCH 12/25] drm/i915/ltphy: Program the P2P Transaction flow for LT Phy

[Murthy, Arun R]

On 15-10-2025 09:38, Suraj Kandpal wrote:
> Program the LT PHY P2P transaction which uses P2M cycle to get
> get data fro Phy when it is ready and then go read the MAC register
> from the MAC address space.
>
> Bspec: 68966, 74497, 74483, 74500
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  10 +-
>   drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   5 +
>   .../gpu/drm/i915/display/intel_cx0_phy_regs.h |   1 +
>   drivers/gpu/drm/i915/display/intel_lt_phy.c   | 115 ++++++++++++++++++
>   .../gpu/drm/i915/display/intel_lt_phy_regs.h  |  15 +++
>   5 files changed, 141 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index c50233f17bc6..b060a5007921 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -125,8 +125,8 @@ static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_w
>   	intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);
>   }
>   
> -static void intel_clear_response_ready_flag(struct intel_encoder *encoder,
> -					    int lane)
> +void intel_clear_response_ready_flag(struct intel_encoder *encoder,
> +				     int lane)
>   {
>   	struct intel_display *display = to_intel_display(encoder);
>   
> @@ -135,7 +135,7 @@ static void intel_clear_response_ready_flag(struct intel_encoder *encoder,
>   		     0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET);
>   }
>   
> -static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
> +void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
>   {
>   	struct intel_display *display = to_intel_display(encoder);
>   	enum port port = encoder->port;
> @@ -156,8 +156,8 @@ static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
>   	intel_clear_response_ready_flag(encoder, lane);
>   }
>   
> -static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
> -				  int command, int lane, u32 *val)
> +int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
> +			   int command, int lane, u32 *val)
>   {
>   	struct intel_display *display = to_intel_display(encoder);
>   	enum port port = encoder->port;
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 283be36d5dff..a5446686b23b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -22,6 +22,8 @@ struct intel_display;
>   struct intel_encoder;
>   struct intel_hdmi;
>   
> +void intel_clear_response_ready_flag(struct intel_encoder *encoder,
> +				     int lane);
>   bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
>   void intel_mtl_pll_enable(struct intel_encoder *encoder,
>   			  const struct intel_crtc_state *crtc_state);
> @@ -53,6 +55,9 @@ u8 intel_cx0_read(struct intel_encoder *encoder,
>   		  u8 lane_mask, u16 addr);
>   void intel_cx0_write(struct intel_encoder *encoder,
>   		     u8 lane_mask, u16 addr, u8 data, bool committed);
> +int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
> +			   int command, int lane, u32 *val);
> +void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane);
>   int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
>   void intel_cx0_pll_power_save_wa(struct intel_display *display);
>   void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 114f6b2113db..cb2ab8442aa1 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -50,6 +50,7 @@
>   #define   XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED	REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
>   #define   XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED	REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2)
>   #define   XELPDP_PORT_M2P_COMMAND_READ			REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3)
> +#define   XELPDP_PORT_P2P_TRANSACTION_PENDING		REG_BIT(24)
>   #define   XELPDP_PORT_M2P_DATA_MASK			REG_GENMASK(23, 16)
>   #define   XELPDP_PORT_M2P_DATA(val)			REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val)
>   #define   XELPDP_PORT_M2P_TRANSACTION_RESET		REG_BIT(15)
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 3aa8b3b345d3..32a5a60fe92f 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -19,6 +19,10 @@
>   #include "intel_psr.h"
>   #include "intel_tc.h"
>   
> +#define for_each_lt_phy_lane_in_mask(__lane_mask, __lane) \
> +	for ((__lane) = 0; (__lane) < 2; (__lane)++) \
> +		for_each_if((__lane_mask) & BIT(__lane))
> +
>   #define INTEL_LT_PHY_LANE0		BIT(0)
>   #define INTEL_LT_PHY_LANE1		BIT(1)
>   #define INTEL_LT_PHY_BOTH_LANES		(INTEL_LT_PHY_LANE1 |\
> @@ -999,6 +1003,113 @@ static void intel_lt_phy_write(struct intel_encoder *encoder,
>   	intel_cx0_write(encoder, lane_mask, addr, data, committed);
>   }
>   
> +static void intel_lt_phy_clear_status_p2p(struct intel_encoder *encoder,
> +					  int lane)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +
> +	intel_de_rmw(display,
> +		     XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(encoder->port, lane),
> +		     XELPDP_PORT_P2M_RESPONSE_READY, 0);
> +}
> +
> +static void
> +assert_dc_off(struct intel_display *display)
> +{
> +	bool enabled;
> +
> +	enabled = intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF);
> +	drm_WARN_ON(display->drm, !enabled);
> +}
> +
> +static int __intel_lt_phy_p2p_write_once(struct intel_encoder *encoder,
> +					 int lane, u16 addr, u8 data,
> +					 i915_reg_t mac_reg_addr,
> +					 u8 expected_mac_val)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	enum port port = encoder->port;
> +	enum phy phy = intel_encoder_to_phy(encoder);
> +	int ack;
> +	u32 val;
> +
> +	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> +				    XELPDP_PORT_P2P_TRANSACTION_PENDING,
> +				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> +		drm_dbg_kms(display->drm,
> +			    "PHY %c Timeout waiting for previous transaction to complete. Resetting bus.\n",
> +			    phy_name(phy));
> +		intel_cx0_bus_reset(encoder, lane);
> +		return -ETIMEDOUT;
> +	}
> +
> +	intel_de_rmw(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane), 0, 0);
> +
> +	intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> +		       XELPDP_PORT_P2P_TRANSACTION_PENDING |
> +		       XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED |
> +		       XELPDP_PORT_M2P_DATA(data) |
> +		       XELPDP_PORT_M2P_ADDRESS(addr));
> +
> +	ack = intel_cx0_wait_for_ack(encoder, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val);
> +	if (ack < 0)
> +		return ack;
> +
> +	if (val & XELPDP_PORT_P2M_ERROR_SET) {
> +		drm_dbg_kms(display->drm,
> +			    "PHY %c Error occurred during P2P write command. Status: 0x%x\n",
> +			    phy_name(phy), val);
> +		intel_lt_phy_clear_status_p2p(encoder, lane);
> +		intel_cx0_bus_reset(encoder, lane);
> +		return -EINVAL;
> +	}
> +
> +	/*
> +	 * This needs to be added to give PHY time to set everything up this was a requirement
> +	 * to get the display up and running.
> +	 */
> +	udelay(150);

How was this delay value derived?

Thanks and Regards,
Arun R Murthy
-------------------

> +	intel_clear_response_ready_flag(encoder, lane);
> +	intel_lt_phy_clear_status_p2p(encoder, lane);
> +
> +	return 0;
> +}
> +
> +static void __intel_lt_phy_p2p_write(struct intel_encoder *encoder,
> +				     int lane, u16 addr, u8 data,
> +				     i915_reg_t mac_reg_addr,
> +				     u8 expected_mac_val)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	enum phy phy = intel_encoder_to_phy(encoder);
> +	int i, status;
> +
> +	assert_dc_off(display);
> +
> +	/* 3 tries is assumed to be enough to write successfully */
> +	for (i = 0; i < 3; i++) {
> +		status = __intel_lt_phy_p2p_write_once(encoder, lane, addr, data, mac_reg_addr,
> +						       expected_mac_val);
> +
> +		if (status == 0)
> +			return;
> +	}
> +
> +	drm_err_once(display->drm,
> +		     "PHY %c P2P Write %04x failed after %d retries.\n", phy_name(phy), addr, i);
> +}
> +
> +static void intel_lt_phy_p2p_write(struct intel_encoder *encoder,
> +				   u8 lane_mask, u16 addr, u8 data,
> +				   i915_reg_t mac_reg_addr,
> +				   u8 expected_mac_val)
> +{
> +	int lane;
> +
> +	for_each_lt_phy_lane_in_mask(lane_mask, lane)
> +		__intel_lt_phy_p2p_write(encoder, lane, addr, data, mac_reg_addr, expected_mac_val);
> +}
> +
>   static void
>   intel_lt_phy_setup_powerdown(struct intel_encoder *encoder, u8 lane_count)
>   {
> @@ -1417,6 +1528,10 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   		 * register at offset 0xC00 for Owned PHY Lanes*.
>   		 */
>   		/* 6.3. Clear P2P transaction Ready bit. */
> +		intel_lt_phy_p2p_write(encoder, owned_lane_mask, LT_PHY_RATE_UPDATE,
> +				       LT_PHY_RATE_CONTROL_VDR_UPDATE, LT_PHY_MAC_VDR,
> +				       LT_PHY_PCLKIN_GATE);
> +
>   		/* 7. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0. */
>   		/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
>   		/*
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> index a4aa2a3e0425..5fb4331c387f 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> @@ -9,12 +9,17 @@
>   #include "i915_reg_defs.h"
>   #include "intel_display_limits.h"
>   
> +#define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
>   #define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
>   #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
>   #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
>   #define XE3PLPD_RESET_START_LATENCY_US	10
>   #define XE3PLPD_RESET_END_LATENCY_US	200
>   
> +/* LT Phy MAC Register */
> +#define LT_PHY_MAC_VDR			_MMIO(0xC00)
> +#define    LT_PHY_PCLKIN_GATE		REG_BIT8(0)
> +
>   /* LT Phy Vendor Register */
>   #define LT_PHY_VDR_0_CONFIG	0xC02
>   #define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
> @@ -29,6 +34,7 @@
>   #define LT_PHY_VDR_X_DATAY(idx, y)	((0xC06 + (3 - (y))) + 0x6 * (idx))
>   
>   #define LT_PHY_RATE_UPDATE		0xCC4
> +#define    LT_PHY_RATE_CONTROL_VDR_UPDATE	REG_BIT8(0)
>   
>   #define _XE3PLPD_PORT_BUF_CTL5(idx)	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>   								 _XELPDP_PORT_BUF_CTL1_LN0_A, \
> @@ -41,4 +47,13 @@
>   #define  XE3PLPD_MACCLK_RATE_MASK	REG_GENMASK(4, 0)
>   #define  XE3PLPD_MACCLK_RATE_DEF	REG_FIELD_PREP(XE3PLPD_MACCLK_RATE_MASK, 0x1F)
>   
> +#define _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(idx, lane)	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
> +										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
> +										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
> +										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
> +										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) \
> +										 + 0x60 + (lane) * 0x4)
> +#define XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(port, lane)	 _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(__xe2lpd_port_idx(port), \
> +											    lane)
> +#define   XE3LPD_PORT_P2M_ADDR_MASK			REG_GENMASK(11, 0)
>   #endif /* __INTEL_LT_PHY_REGS_H__ */

RE: [PATCH 12/25] drm/i915/ltphy: Program the P2P Transaction flow for LT Phy

[Kandpal, Suraj]

> > +
> > +	/*
> > +	 * This needs to be added to give PHY time to set everything up this
> was a requirement
> > +	 * to get the display up and running.
> > +	 */
> > +	udelay(150);
> 
> How was this delay value derived?

While doing power on we came up with this empirical value after a lot of trial and error.

Regards,
Suraj Kandpal

> 
> Thanks and Regards,
> Arun R Murthy
> -------------------
> 
> > +	intel_clear_response_ready_flag(encoder, lane);
> > +	intel_lt_phy_clear_status_p2p(encoder, lane);
> > +
> > +	return 0;
> > +}
> > +
> > +static void __intel_lt_phy_p2p_write(struct intel_encoder *encoder,
> > +				     int lane, u16 addr, u8 data,
> > +				     i915_reg_t mac_reg_addr,
> > +				     u8 expected_mac_val)
> > +{
> > +	struct intel_display *display = to_intel_display(encoder);
> > +	enum phy phy = intel_encoder_to_phy(encoder);
> > +	int i, status;
> > +
> > +	assert_dc_off(display);
> > +
> > +	/* 3 tries is assumed to be enough to write successfully */
> > +	for (i = 0; i < 3; i++) {
> > +		status = __intel_lt_phy_p2p_write_once(encoder, lane, addr,
> data, mac_reg_addr,
> > +						       expected_mac_val);
> > +
> > +		if (status == 0)
> > +			return;
> > +	}
> > +
> > +	drm_err_once(display->drm,
> > +		     "PHY %c P2P Write %04x failed after %d retries.\n",
> > +phy_name(phy), addr, i); }
> > +
> > +static void intel_lt_phy_p2p_write(struct intel_encoder *encoder,
> > +				   u8 lane_mask, u16 addr, u8 data,
> > +				   i915_reg_t mac_reg_addr,
> > +				   u8 expected_mac_val)
> > +{
> > +	int lane;
> > +
> > +	for_each_lt_phy_lane_in_mask(lane_mask, lane)
> > +		__intel_lt_phy_p2p_write(encoder, lane, addr, data,
> mac_reg_addr,
> > +expected_mac_val); }
> > +
> >   static void
> >   intel_lt_phy_setup_powerdown(struct intel_encoder *encoder, u8
> lane_count)
> >   {
> > @@ -1417,6 +1528,10 @@ void intel_lt_phy_pll_enable(struct
> intel_encoder *encoder,
> >   		 * register at offset 0xC00 for Owned PHY Lanes*.
> >   		 */
> >   		/* 6.3. Clear P2P transaction Ready bit. */
> > +		intel_lt_phy_p2p_write(encoder, owned_lane_mask,
> LT_PHY_RATE_UPDATE,
> > +				       LT_PHY_RATE_CONTROL_VDR_UPDATE,
> LT_PHY_MAC_VDR,
> > +				       LT_PHY_PCLKIN_GATE);
> > +
> >   		/* 7. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0.
> */
> >   		/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
> >   		/*
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > index a4aa2a3e0425..5fb4331c387f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > @@ -9,12 +9,17 @@
> >   #include "i915_reg_defs.h"
> >   #include "intel_display_limits.h"
> >
> > +#define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
> >   #define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
> >   #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
> >   #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
> >   #define XE3PLPD_RESET_START_LATENCY_US	10
> >   #define XE3PLPD_RESET_END_LATENCY_US	200
> >
> > +/* LT Phy MAC Register */
> > +#define LT_PHY_MAC_VDR			_MMIO(0xC00)
> > +#define    LT_PHY_PCLKIN_GATE		REG_BIT8(0)
> > +
> >   /* LT Phy Vendor Register */
> >   #define LT_PHY_VDR_0_CONFIG	0xC02
> >   #define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
> > @@ -29,6 +34,7 @@
> >   #define LT_PHY_VDR_X_DATAY(idx, y)	((0xC06 + (3 - (y))) + 0x6 *
> (idx))
> >
> >   #define LT_PHY_RATE_UPDATE		0xCC4
> > +#define    LT_PHY_RATE_CONTROL_VDR_UPDATE	REG_BIT8(0)
> >
> >   #define _XE3PLPD_PORT_BUF_CTL5(idx)
> 	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
> >
> _XELPDP_PORT_BUF_CTL1_LN0_A, \ @@ -41,4 +47,13 @@
> >   #define  XE3PLPD_MACCLK_RATE_MASK	REG_GENMASK(4, 0)
> >   #define  XE3PLPD_MACCLK_RATE_DEF
> 	REG_FIELD_PREP(XE3PLPD_MACCLK_RATE_MASK, 0x1F)
> >
> > +#define _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(idx, lane)
> 	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
> > +
> 	 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
> > +
> 	 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
> > +
> 	 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
> > +
> 	 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) \
> > +
> 	 + 0x60 + (lane) * 0x4)
> > +#define XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(port, lane)
> _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(__xe2lpd_port_idx(port), \
> > +
> 		    lane)
> > +#define   XE3LPD_PORT_P2M_ADDR_MASK
> 	REG_GENMASK(11, 0)
> >   #endif /* __INTEL_LT_PHY_REGS_H__ */

Re: [PATCH 12/25] drm/i915/ltphy: Program the P2P Transaction flow for LT Phy

[Murthy, Arun R]

On 23-10-2025 14:54, Kandpal, Suraj wrote:
>>> +
>>> +	/*
>>> +	 * This needs to be added to give PHY time to set everything up this
>> was a requirement
>>> +	 * to get the display up and running.
>>> +	 */
>>> +	udelay(150);
>> How was this delay value derived?
> While doing power on we came up with this empirical value after a lot of trial and error.

Might be the settling time required for the PHY. Please add a Re-visit/TODO

Thanks and Regards,
Arun R Murthy
-------------------

> Regards,
> Suraj Kandpal
>
>> Thanks and Regards,
>> Arun R Murthy
>> -------------------
>>
>>> +	intel_clear_response_ready_flag(encoder, lane);
>>> +	intel_lt_phy_clear_status_p2p(encoder, lane);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static void __intel_lt_phy_p2p_write(struct intel_encoder *encoder,
>>> +				     int lane, u16 addr, u8 data,
>>> +				     i915_reg_t mac_reg_addr,
>>> +				     u8 expected_mac_val)
>>> +{
>>> +	struct intel_display *display = to_intel_display(encoder);
>>> +	enum phy phy = intel_encoder_to_phy(encoder);
>>> +	int i, status;
>>> +
>>> +	assert_dc_off(display);
>>> +
>>> +	/* 3 tries is assumed to be enough to write successfully */
>>> +	for (i = 0; i < 3; i++) {
>>> +		status = __intel_lt_phy_p2p_write_once(encoder, lane, addr,
>> data, mac_reg_addr,
>>> +						       expected_mac_val);
>>> +
>>> +		if (status == 0)
>>> +			return;
>>> +	}
>>> +
>>> +	drm_err_once(display->drm,
>>> +		     "PHY %c P2P Write %04x failed after %d retries.\n",
>>> +phy_name(phy), addr, i); }
>>> +
>>> +static void intel_lt_phy_p2p_write(struct intel_encoder *encoder,
>>> +				   u8 lane_mask, u16 addr, u8 data,
>>> +				   i915_reg_t mac_reg_addr,
>>> +				   u8 expected_mac_val)
>>> +{
>>> +	int lane;
>>> +
>>> +	for_each_lt_phy_lane_in_mask(lane_mask, lane)
>>> +		__intel_lt_phy_p2p_write(encoder, lane, addr, data,
>> mac_reg_addr,
>>> +expected_mac_val); }
>>> +
>>>    static void
>>>    intel_lt_phy_setup_powerdown(struct intel_encoder *encoder, u8
>> lane_count)
>>>    {
>>> @@ -1417,6 +1528,10 @@ void intel_lt_phy_pll_enable(struct
>> intel_encoder *encoder,
>>>    		 * register at offset 0xC00 for Owned PHY Lanes*.
>>>    		 */
>>>    		/* 6.3. Clear P2P transaction Ready bit. */
>>> +		intel_lt_phy_p2p_write(encoder, owned_lane_mask,
>> LT_PHY_RATE_UPDATE,
>>> +				       LT_PHY_RATE_CONTROL_VDR_UPDATE,
>> LT_PHY_MAC_VDR,
>>> +				       LT_PHY_PCLKIN_GATE);
>>> +
>>>    		/* 7. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0.
>> */
>>>    		/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
>>>    		/*
>>> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
>>> b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
>>> index a4aa2a3e0425..5fb4331c387f 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
>>> @@ -9,12 +9,17 @@
>>>    #include "i915_reg_defs.h"
>>>    #include "intel_display_limits.h"
>>>
>>> +#define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
>>>    #define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
>>>    #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
>>>    #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
>>>    #define XE3PLPD_RESET_START_LATENCY_US	10
>>>    #define XE3PLPD_RESET_END_LATENCY_US	200
>>>
>>> +/* LT Phy MAC Register */
>>> +#define LT_PHY_MAC_VDR			_MMIO(0xC00)
>>> +#define    LT_PHY_PCLKIN_GATE		REG_BIT8(0)
>>> +
>>>    /* LT Phy Vendor Register */
>>>    #define LT_PHY_VDR_0_CONFIG	0xC02
>>>    #define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
>>> @@ -29,6 +34,7 @@
>>>    #define LT_PHY_VDR_X_DATAY(idx, y)	((0xC06 + (3 - (y))) + 0x6 *
>> (idx))
>>>    #define LT_PHY_RATE_UPDATE		0xCC4
>>> +#define    LT_PHY_RATE_CONTROL_VDR_UPDATE	REG_BIT8(0)
>>>
>>>    #define _XE3PLPD_PORT_BUF_CTL5(idx)
>> 	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>> _XELPDP_PORT_BUF_CTL1_LN0_A, \ @@ -41,4 +47,13 @@
>>>    #define  XE3PLPD_MACCLK_RATE_MASK	REG_GENMASK(4, 0)
>>>    #define  XE3PLPD_MACCLK_RATE_DEF
>> 	REG_FIELD_PREP(XE3PLPD_MACCLK_RATE_MASK, 0x1F)
>>> +#define _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(idx, lane)
>> 	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>>> +
>> 	 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
>>> +
>> 	 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
>>> +
>> 	 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
>>> +
>> 	 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) \
>>> +
>> 	 + 0x60 + (lane) * 0x4)
>>> +#define XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(port, lane)
>> _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(__xe2lpd_port_idx(port), \
>>> +
>> 		    lane)
>>> +#define   XE3LPD_PORT_P2M_ADDR_MASK
>> 	REG_GENMASK(11, 0)
>>>    #endif /* __INTEL_LT_PHY_REGS_H__ */

[PATCH 13/25] drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL steps

[Suraj Kandpal]

Program the rest of the steps with regards to PORT_CLOCK_CTL in
Non-TBT PLL enable sequence.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 25 +++++++++++++++++++
 .../gpu/drm/i915/display/intel_lt_phy_regs.h  |  1 +
 2 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 32a5a60fe92f..08a5ed27d2d7 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1493,6 +1493,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	bool lane_reversal = dig_port->lane_reversal;
 	u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
+	enum phy phy = intel_encoder_to_phy(encoder);
+	enum port port = encoder->port;
 	intel_wakeref_t wakeref = 0;
 
 	wakeref = intel_lt_phy_transaction_begin(encoder);
@@ -1533,19 +1535,42 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 				       LT_PHY_PCLKIN_GATE);
 
 		/* 7. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0. */
+		intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
+			     XELPDP_LANE_PCLK_PLL_REQUEST(0), 0);
+
 		/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
+		if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
+					 XELPDP_LANE_PCLK_PLL_ACK(0), 0,
+					 XE3PLPD_MACCLK_TURNOFF_LATENCY_US, 0, NULL))
+			drm_warn(display->drm, "PHY %c PLL MacCLK Ack deassertion Timeout after %dus.\n",
+				 phy_name(phy), XE3PLPD_MACCLK_TURNOFF_LATENCY_US);
+
 		/*
 		 * 9. Follow the Display Voltage Frequency Switching - Sequence Before Frequency
 		 * Change. We handle this step in bxt_set_cdclk().
 		 */
 		/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
 		/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
+		intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
+			     XELPDP_LANE_PCLK_PLL_REQUEST(0),
+			     XELPDP_LANE_PCLK_PLL_REQUEST(0));
+
 		/* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */
+		if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
+					 XELPDP_LANE_PCLK_PLL_ACK(0),
+					 XELPDP_LANE_PCLK_PLL_ACK(0),
+					 XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
+			drm_warn(display->drm, "PHY %c PLL MacCLK Ack assertion Timeout after %dus.\n",
+				 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
 	} else {
 		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), crtc_state->port_clock);
 	}
 
 	/* 13. Ungate the forward clock by setting PORT_CLOCK_CTL[Forward Clock Ungate] = 1. */
+	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
+		     XELPDP_FORWARD_CLOCK_UNGATE,
+		     XELPDP_FORWARD_CLOCK_UNGATE);
+
 	/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
 	/*
 	 * 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over PHY message bus for
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
index 5fb4331c387f..283ee0c55724 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
@@ -12,6 +12,7 @@
 #define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
 #define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
 #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
+#define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
 #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
 #define XE3PLPD_RESET_START_LATENCY_US	10
 #define XE3PLPD_RESET_END_LATENCY_US	200
-- 
2.34.1

Re: [PATCH 13/25] drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL steps

[Murthy, Arun R]

On 15-10-2025 09:38, Suraj Kandpal wrote:
> Program the rest of the steps with regards to PORT_CLOCK_CTL in
> Non-TBT PLL enable sequence.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>   drivers/gpu/drm/i915/display/intel_lt_phy.c   | 25 +++++++++++++++++++
>   .../gpu/drm/i915/display/intel_lt_phy_regs.h  |  1 +
>   2 files changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 32a5a60fe92f..08a5ed27d2d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1493,6 +1493,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>   	bool lane_reversal = dig_port->lane_reversal;
>   	u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
> +	enum phy phy = intel_encoder_to_phy(encoder);
> +	enum port port = encoder->port;
>   	intel_wakeref_t wakeref = 0;
>   
>   	wakeref = intel_lt_phy_transaction_begin(encoder);
> @@ -1533,19 +1535,42 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   				       LT_PHY_PCLKIN_GATE);
>   
>   		/* 7. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0. */
> +		intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> +			     XELPDP_LANE_PCLK_PLL_REQUEST(0), 0);
> +
>   		/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
> +		if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
> +					 XELPDP_LANE_PCLK_PLL_ACK(0), 0,
> +					 XE3PLPD_MACCLK_TURNOFF_LATENCY_US, 0, NULL))
> +			drm_warn(display->drm, "PHY %c PLL MacCLK Ack deassertion Timeout after %dus.\n",
> +				 phy_name(phy), XE3PLPD_MACCLK_TURNOFF_LATENCY_US);
> +
>   		/*
>   		 * 9. Follow the Display Voltage Frequency Switching - Sequence Before Frequency
>   		 * Change. We handle this step in bxt_set_cdclk().
>   		 */
>   		/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
>   		/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
> +		intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> +			     XELPDP_LANE_PCLK_PLL_REQUEST(0),
> +			     XELPDP_LANE_PCLK_PLL_REQUEST(0));
> +
>   		/* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */
> +		if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
> +					 XELPDP_LANE_PCLK_PLL_ACK(0),
> +					 XELPDP_LANE_PCLK_PLL_ACK(0),
> +					 XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
> +			drm_warn(display->drm, "PHY %c PLL MacCLK Ack assertion Timeout after %dus.\n",
> +				 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
>   	} else {
>   		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), crtc_state->port_clock);
>   	}
>   
>   	/* 13. Ungate the forward clock by setting PORT_CLOCK_CTL[Forward Clock Ungate] = 1. */
> +	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> +		     XELPDP_FORWARD_CLOCK_UNGATE,
> +		     XELPDP_FORWARD_CLOCK_UNGATE);
> +
>   	/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
>   	/*
>   	 * 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over PHY message bus for
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> index 5fb4331c387f..283ee0c55724 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> @@ -12,6 +12,7 @@
>   #define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
>   #define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
>   #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
> +#define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
>   #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
>   #define XE3PLPD_RESET_START_LATENCY_US	10
>   #define XE3PLPD_RESET_END_LATENCY_US	200

[PATCH 14/25] drm/i915/ltphy: Program the rest of the LT Phy Enable sequence

[Suraj Kandpal]

Program the rest of the LT Phy Non TBT PLL Enable sequence. This
can be done in a single patch since the rest of the prequistie
functions are already coded in.

Bspec: 74492, 69701
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c |  4 +--
 drivers/gpu/drm/i915/display/intel_cx0_phy.h |  2 ++
 drivers/gpu/drm/i915/display/intel_lt_phy.c  | 28 ++++++++++++++++++++
 3 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index b060a5007921..914b215d8bd4 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -409,8 +409,8 @@ static void __intel_cx0_rmw(struct intel_encoder *encoder,
 		__intel_cx0_write(encoder, lane, addr, val, committed);
 }
 
-static void intel_cx0_rmw(struct intel_encoder *encoder,
-			  u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed)
+void intel_cx0_rmw(struct intel_encoder *encoder,
+		   u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed)
 {
 	u8 lane;
 
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index a5446686b23b..f0f0efa2d48b 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -53,6 +53,8 @@ void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
 bool intel_cx0_is_hdmi_frl(u32 clock);
 u8 intel_cx0_read(struct intel_encoder *encoder,
 		  u8 lane_mask, u16 addr);
+void intel_cx0_rmw(struct intel_encoder *encoder,
+		   u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed);
 void intel_cx0_write(struct intel_encoder *encoder,
 		     u8 lane_mask, u16 addr, u8 data, bool committed);
 int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 08a5ed27d2d7..9e4868a15e7d 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1496,6 +1496,11 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 	enum phy phy = intel_encoder_to_phy(encoder);
 	enum port port = encoder->port;
 	intel_wakeref_t wakeref = 0;
+	u32 lane_phy_pulse_status = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES
+					? (XE3PLPDP_LANE_PHY_PULSE_STATUS(0) |
+					   XE3PLPDP_LANE_PHY_PULSE_STATUS(1))
+					: XE3PLPDP_LANE_PHY_PULSE_STATUS(0);
+	u8 rate_update;
 
 	wakeref = intel_lt_phy_transaction_begin(encoder);
 
@@ -1550,6 +1555,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 		 * Change. We handle this step in bxt_set_cdclk().
 		 */
 		/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
+		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
+			       crtc_state->port_clock);
+
 		/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
 		intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
 			     XELPDP_LANE_PCLK_PLL_REQUEST(0),
@@ -1572,17 +1580,37 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 		     XELPDP_FORWARD_CLOCK_UNGATE);
 
 	/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
+	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
+		     lane_phy_pulse_status,
+		     lane_phy_pulse_status);
 	/*
 	 * 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over PHY message bus for
 	 * Owned PHY Lanes.
 	 */
+	rate_update = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_RATE_UPDATE);
+	rate_update &= ~LT_PHY_RATE_CONTROL_VDR_UPDATE;
+	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_RATE_UPDATE,
+			   rate_update, MB_WRITE_COMMITTED);
+
 	/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
+	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
+				 lane_phy_pulse_status, lane_phy_pulse_status,
+				 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
+		drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
+			 phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
+
 	/* 17. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
+	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
+		     lane_phy_pulse_status,
+		     lane_phy_pulse_status);
+
 	/*
 	 * 18. Follow the Display Voltage Frequency Switching - Sequence After Frequency Change.
 	 * We handle this step in bxt_set_cdclk()
 	 */
 	/* 19. Move the PHY powerdown state to Active and program to enable/disable transmitters */
+	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
+					       XELPDP_P0_STATE_ACTIVE);
 
 	intel_lt_phy_transaction_end(encoder, wakeref);
 }
-- 
2.34.1

Re: [PATCH 14/25] drm/i915/ltphy: Program the rest of the LT Phy Enable sequence

[Murthy, Arun R]

On 15-10-2025 09:38, Suraj Kandpal wrote:
> Program the rest of the LT Phy Non TBT PLL Enable sequence. This
> can be done in a single patch since the rest of the prequistie
> functions are already coded in.
>
> Bspec: 74492, 69701
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>   drivers/gpu/drm/i915/display/intel_cx0_phy.c |  4 +--
>   drivers/gpu/drm/i915/display/intel_cx0_phy.h |  2 ++
>   drivers/gpu/drm/i915/display/intel_lt_phy.c  | 28 ++++++++++++++++++++
>   3 files changed, 32 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index b060a5007921..914b215d8bd4 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -409,8 +409,8 @@ static void __intel_cx0_rmw(struct intel_encoder *encoder,
>   		__intel_cx0_write(encoder, lane, addr, val, committed);
>   }
>   
> -static void intel_cx0_rmw(struct intel_encoder *encoder,
> -			  u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed)
> +void intel_cx0_rmw(struct intel_encoder *encoder,
> +		   u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed)
>   {
>   	u8 lane;
>   
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index a5446686b23b..f0f0efa2d48b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -53,6 +53,8 @@ void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
>   bool intel_cx0_is_hdmi_frl(u32 clock);
>   u8 intel_cx0_read(struct intel_encoder *encoder,
>   		  u8 lane_mask, u16 addr);
> +void intel_cx0_rmw(struct intel_encoder *encoder,
> +		   u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed);
>   void intel_cx0_write(struct intel_encoder *encoder,
>   		     u8 lane_mask, u16 addr, u8 data, bool committed);
>   int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 08a5ed27d2d7..9e4868a15e7d 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1496,6 +1496,11 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   	enum phy phy = intel_encoder_to_phy(encoder);
>   	enum port port = encoder->port;
>   	intel_wakeref_t wakeref = 0;
> +	u32 lane_phy_pulse_status = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES
> +					? (XE3PLPDP_LANE_PHY_PULSE_STATUS(0) |
> +					   XE3PLPDP_LANE_PHY_PULSE_STATUS(1))
> +					: XE3PLPDP_LANE_PHY_PULSE_STATUS(0);
> +	u8 rate_update;
>   
>   	wakeref = intel_lt_phy_transaction_begin(encoder);
>   
> @@ -1550,6 +1555,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   		 * Change. We handle this step in bxt_set_cdclk().
>   		 */
>   		/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
> +		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> +			       crtc_state->port_clock);
> +
>   		/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
>   		intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
>   			     XELPDP_LANE_PCLK_PLL_REQUEST(0),
> @@ -1572,17 +1580,37 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   		     XELPDP_FORWARD_CLOCK_UNGATE);
>   
>   	/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
> +	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> +		     lane_phy_pulse_status,
> +		     lane_phy_pulse_status);
>   	/*
>   	 * 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over PHY message bus for
>   	 * Owned PHY Lanes.
>   	 */
> +	rate_update = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_RATE_UPDATE);
> +	rate_update &= ~LT_PHY_RATE_CONTROL_VDR_UPDATE;
> +	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_RATE_UPDATE,
> +			   rate_update, MB_WRITE_COMMITTED);
> +
>   	/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
> +	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
> +				 lane_phy_pulse_status, lane_phy_pulse_status,
> +				 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
> +		drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
> +			 phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
> +
>   	/* 17. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
> +	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> +		     lane_phy_pulse_status,
> +		     lane_phy_pulse_status);
> +
>   	/*
>   	 * 18. Follow the Display Voltage Frequency Switching - Sequence After Frequency Change.
>   	 * We handle this step in bxt_set_cdclk()
>   	 */
>   	/* 19. Move the PHY powerdown state to Active and program to enable/disable transmitters */
> +	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
> +					       XELPDP_P0_STATE_ACTIVE);
>   
>   	intel_lt_phy_transaction_end(encoder, wakeref);
>   }

[PATCH 15/25] drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequence

[Suraj Kandpal]

Program in the steps for Non TBT PLL disable sequence.
The whole function can be defined in one shot since most of
prequiste functions are already coded in.

Bspec: 74492
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 78 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |  1 +
 .../gpu/drm/i915/display/intel_lt_phy_regs.h  |  1 +
 3 files changed, 80 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 9e4868a15e7d..747cce4a484a 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1614,3 +1614,81 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 
 	intel_lt_phy_transaction_end(encoder, wakeref);
 }
+
+void intel_lt_phy_pll_disable(struct intel_encoder *encoder)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	enum phy phy = intel_encoder_to_phy(encoder);
+	enum port port = encoder->port;
+	intel_wakeref_t wakeref;
+	u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
+	u32 lane_pipe_reset = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES
+				? (XELPDP_LANE_PIPE_RESET(0) |
+				   XELPDP_LANE_PIPE_RESET(1))
+				: XELPDP_LANE_PIPE_RESET(0);
+	u32 lane_phy_current_status = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES
+					? (XELPDP_LANE_PHY_CURRENT_STATUS(0) |
+					   XELPDP_LANE_PHY_CURRENT_STATUS(1))
+					: XELPDP_LANE_PHY_CURRENT_STATUS(0);
+	u32 lane_phy_pulse_status = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES
+					? (XE3PLPDP_LANE_PHY_PULSE_STATUS(0) |
+					   XE3PLPDP_LANE_PHY_PULSE_STATUS(1))
+					: XE3PLPDP_LANE_PHY_PULSE_STATUS(0);
+
+	wakeref = intel_lt_phy_transaction_begin(encoder);
+
+	/* 1. Clear PORT_BUF_CTL2 [PHY Pulse Status]. */
+	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
+		     lane_phy_pulse_status,
+		     lane_phy_pulse_status);
+
+	/* 2. Set PORT_BUF_CTL2<port> Lane<PHY Lanes Owned> Pipe Reset to 1. */
+	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset,
+		     lane_pipe_reset);
+
+	/* 3. Poll for PORT_BUF_CTL2<port> Lane<PHY Lanes Owned> PHY Current Status == 1. */
+	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
+				 lane_phy_current_status,
+				 lane_phy_current_status,
+				 XE3PLPD_RESET_START_LATENCY_US, 0, NULL))
+		drm_warn(display->drm,
+			 "PHY %c failed to reset Lane after %dms.\n",
+			 phy_name(phy), XE3PLPD_RESET_START_LATENCY_US);
+
+	/* 4. Clear for PHY pulse status on owned PHY lanes. */
+	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
+		     lane_phy_pulse_status,
+		     lane_phy_pulse_status);
+
+	/*
+	 * 5. Follow the Display Voltage Frequency Switching -
+	 * Sequence Before Frequency Change. We handle this step in bxt_set_cdclk().
+	 */
+	/* 6. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0. */
+	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
+		     XELPDP_LANE_PCLK_PLL_REQUEST(0), 0);
+
+	/* 7. Program DDI_CLK_VALFREQ to 0. */
+	intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
+
+	/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
+	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
+				 XELPDP_LANE_PCLK_PLL_ACK(0), 0,
+				 XE3PLPD_MACCLK_TURNOFF_LATENCY_US, 0, NULL))
+		drm_warn(display->drm, "PHY %c PLL MacCLK Ack deassertion Timeout after %dus.\n",
+			 phy_name(phy), XE3PLPD_MACCLK_TURNOFF_LATENCY_US);
+
+	/*
+	 *  9. Follow the Display Voltage Frequency Switching -
+	 *  Sequence After Frequency Change. We handle this step in bxt_set_cdclk().
+	 */
+	/* 10. Program PORT_CLOCK_CTL register to disable and gate clocks. */
+	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
+		     XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_FORWARD_CLOCK_UNGATE, 0);
+
+	/* 11. Program PORT_BUF_CTL5[MacCLK Reset_0] = 1 to assert MacCLK reset. */
+	intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port),
+		     XE3PLPD_MACCLK_RESET_0, XE3PLPD_MACCLK_RESET_0);
+
+	intel_lt_phy_transaction_end(encoder, wakeref);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 5b4e0d9c940f..499091e04e82 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -14,6 +14,7 @@ struct intel_lt_phy_pll_state;
 
 void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 			     const struct intel_crtc_state *crtc_state);
+void intel_lt_phy_pll_disable(struct intel_encoder *encoder);
 int
 intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 			    struct intel_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
index 283ee0c55724..c641cc957f1b 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
@@ -15,6 +15,7 @@
 #define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
 #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
 #define XE3PLPD_RESET_START_LATENCY_US	10
+#define XE3PLPD_PWRDN_TO_RDY_LATENCY_US	4
 #define XE3PLPD_RESET_END_LATENCY_US	200
 
 /* LT Phy MAC Register */
-- 
2.34.1

Re: [PATCH 15/25] drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequence

[Murthy, Arun R]

On 15-10-2025 09:38, Suraj Kandpal wrote:
> Program in the steps for Non TBT PLL disable sequence.
> The whole function can be defined in one shot since most of
> prequiste functions are already coded in.
>
> Bspec: 74492
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

> ---
>   drivers/gpu/drm/i915/display/intel_lt_phy.c   | 78 +++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_lt_phy.h   |  1 +
>   .../gpu/drm/i915/display/intel_lt_phy_regs.h  |  1 +
>   3 files changed, 80 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 9e4868a15e7d..747cce4a484a 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1614,3 +1614,81 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   
>   	intel_lt_phy_transaction_end(encoder, wakeref);
>   }
> +
> +void intel_lt_phy_pll_disable(struct intel_encoder *encoder)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	enum phy phy = intel_encoder_to_phy(encoder);
> +	enum port port = encoder->port;
> +	intel_wakeref_t wakeref;
> +	u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
> +	u32 lane_pipe_reset = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES
> +				? (XELPDP_LANE_PIPE_RESET(0) |
> +				   XELPDP_LANE_PIPE_RESET(1))
> +				: XELPDP_LANE_PIPE_RESET(0);
> +	u32 lane_phy_current_status = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES
> +					? (XELPDP_LANE_PHY_CURRENT_STATUS(0) |
> +					   XELPDP_LANE_PHY_CURRENT_STATUS(1))
> +					: XELPDP_LANE_PHY_CURRENT_STATUS(0);
> +	u32 lane_phy_pulse_status = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES
> +					? (XE3PLPDP_LANE_PHY_PULSE_STATUS(0) |
> +					   XE3PLPDP_LANE_PHY_PULSE_STATUS(1))
> +					: XE3PLPDP_LANE_PHY_PULSE_STATUS(0);
> +
> +	wakeref = intel_lt_phy_transaction_begin(encoder);
> +
> +	/* 1. Clear PORT_BUF_CTL2 [PHY Pulse Status]. */
> +	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> +		     lane_phy_pulse_status,
> +		     lane_phy_pulse_status);
> +
> +	/* 2. Set PORT_BUF_CTL2<port> Lane<PHY Lanes Owned> Pipe Reset to 1. */
> +	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset,
> +		     lane_pipe_reset);
> +
> +	/* 3. Poll for PORT_BUF_CTL2<port> Lane<PHY Lanes Owned> PHY Current Status == 1. */
> +	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
> +				 lane_phy_current_status,
> +				 lane_phy_current_status,
> +				 XE3PLPD_RESET_START_LATENCY_US, 0, NULL))
> +		drm_warn(display->drm,
> +			 "PHY %c failed to reset Lane after %dms.\n",
> +			 phy_name(phy), XE3PLPD_RESET_START_LATENCY_US);
> +
> +	/* 4. Clear for PHY pulse status on owned PHY lanes. */
> +	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> +		     lane_phy_pulse_status,
> +		     lane_phy_pulse_status);
> +
> +	/*
> +	 * 5. Follow the Display Voltage Frequency Switching -
> +	 * Sequence Before Frequency Change. We handle this step in bxt_set_cdclk().
> +	 */
> +	/* 6. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0. */
> +	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> +		     XELPDP_LANE_PCLK_PLL_REQUEST(0), 0);
> +
> +	/* 7. Program DDI_CLK_VALFREQ to 0. */
> +	intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
> +
> +	/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
> +	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
> +				 XELPDP_LANE_PCLK_PLL_ACK(0), 0,
> +				 XE3PLPD_MACCLK_TURNOFF_LATENCY_US, 0, NULL))
> +		drm_warn(display->drm, "PHY %c PLL MacCLK Ack deassertion Timeout after %dus.\n",
> +			 phy_name(phy), XE3PLPD_MACCLK_TURNOFF_LATENCY_US);
> +
> +	/*
> +	 *  9. Follow the Display Voltage Frequency Switching -
> +	 *  Sequence After Frequency Change. We handle this step in bxt_set_cdclk().
> +	 */
> +	/* 10. Program PORT_CLOCK_CTL register to disable and gate clocks. */
> +	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> +		     XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_FORWARD_CLOCK_UNGATE, 0);
> +
> +	/* 11. Program PORT_BUF_CTL5[MacCLK Reset_0] = 1 to assert MacCLK reset. */
> +	intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port),
> +		     XE3PLPD_MACCLK_RESET_0, XE3PLPD_MACCLK_RESET_0);
> +
> +	intel_lt_phy_transaction_end(encoder, wakeref);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index 5b4e0d9c940f..499091e04e82 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -14,6 +14,7 @@ struct intel_lt_phy_pll_state;
>   
>   void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   			     const struct intel_crtc_state *crtc_state);
> +void intel_lt_phy_pll_disable(struct intel_encoder *encoder);
>   int
>   intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
>   			    struct intel_encoder *encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> index 283ee0c55724..c641cc957f1b 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> @@ -15,6 +15,7 @@
>   #define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
>   #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
>   #define XE3PLPD_RESET_START_LATENCY_US	10
> +#define XE3PLPD_PWRDN_TO_RDY_LATENCY_US	4
>   #define XE3PLPD_RESET_END_LATENCY_US	200
>   
>   /* LT Phy MAC Register */

[PATCH 16/25] drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences

[Suraj Kandpal]

Hook up the LT Phy enable and disable sequences using encoder->
enable/disable_clock and reusing the TBT enable disable sequence from
cx0 PHY since it remains the same.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c |  7 ++++---
 drivers/gpu/drm/i915/display/intel_cx0_phy.h |  3 +++
 drivers/gpu/drm/i915/display/intel_ddi.c     |  7 ++++++-
 drivers/gpu/drm/i915/display/intel_lt_phy.c  | 21 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h  |  3 +++
 5 files changed, 37 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 914b215d8bd4..986da034d4de 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -18,6 +18,7 @@
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_hdmi.h"
+#include "intel_lt_phy.h"
 #include "intel_panel.h"
 #include "intel_psr.h"
 #include "intel_snps_hdmi_pll.h"
@@ -3155,8 +3156,8 @@ static int intel_mtl_tbt_clock_select(struct intel_display *display,
 	}
 }
 
-static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
-				     const struct intel_crtc_state *crtc_state)
+void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
@@ -3340,7 +3341,7 @@ static bool intel_cx0_pll_is_enabled(struct intel_encoder *encoder)
 			     intel_cx0_get_pclk_pll_request(lane);
 }
 
-static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
+void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index f0f0efa2d48b..a37827482a32 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -64,5 +64,8 @@ int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
 void intel_cx0_pll_power_save_wa(struct intel_display *display);
 void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state);
+void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state);
+void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder);
 
 #endif /* __INTEL_CX0_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c09aa759f4d4..6fcfdd0b0103 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -72,6 +72,7 @@
 #include "intel_hotplug.h"
 #include "intel_hti.h"
 #include "intel_lspcon.h"
+#include "intel_lt_phy.h"
 #include "intel_mg_phy_regs.h"
 #include "intel_modeset_lock.h"
 #include "intel_panel.h"
@@ -5224,7 +5225,11 @@ void intel_ddi_init(struct intel_display *display,
 	encoder->cloneable = 0;
 	encoder->pipe_mask = ~0;
 
-	if (DISPLAY_VER(display) >= 14) {
+	if (HAS_LT_PHY(display)) {
+		encoder->enable_clock = intel_xe3plpd_pll_enable;
+		encoder->disable_clock = intel_xe3plpd_pll_disable;
+		encoder->port_pll_type = intel_mtl_port_pll_type;
+	} else if (DISPLAY_VER(display) >= 14) {
 		encoder->enable_clock = intel_mtl_pll_enable;
 		encoder->disable_clock = intel_mtl_pll_disable;
 		encoder->port_pll_type = intel_mtl_port_pll_type;
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 747cce4a484a..d458909b5f12 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1692,3 +1692,24 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder)
 
 	intel_lt_phy_transaction_end(encoder, wakeref);
 }
+
+void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state)
+{
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+	if (intel_tc_port_in_tbt_alt_mode(dig_port))
+		intel_mtl_tbt_pll_enable(encoder, crtc_state);
+	else
+		intel_lt_phy_pll_enable(encoder, crtc_state);
+}
+
+void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
+{
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+	if (intel_tc_port_in_tbt_alt_mode(dig_port))
+		intel_mtl_tbt_pll_disable(encoder);
+	else
+		intel_lt_phy_pll_disable(encoder);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 499091e04e82..15d3d680871c 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -20,6 +20,9 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 			    struct intel_encoder *encoder);
 int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state);
+void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state);
+void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
 
 #define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35)
 
-- 
2.34.1

Re: [PATCH 16/25] drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences

[Murthy, Arun R]

On 15-10-2025 09:38, Suraj Kandpal wrote:
> Hook up the LT Phy enable and disable sequences using encoder->
> enable/disable_clock and reusing the TBT enable disable sequence from
> cx0 PHY since it remains the same.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>   drivers/gpu/drm/i915/display/intel_cx0_phy.c |  7 ++++---
>   drivers/gpu/drm/i915/display/intel_cx0_phy.h |  3 +++
>   drivers/gpu/drm/i915/display/intel_ddi.c     |  7 ++++++-
>   drivers/gpu/drm/i915/display/intel_lt_phy.c  | 21 ++++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_lt_phy.h  |  3 +++
>   5 files changed, 37 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 914b215d8bd4..986da034d4de 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -18,6 +18,7 @@
>   #include "intel_display_types.h"
>   #include "intel_dp.h"
>   #include "intel_hdmi.h"
> +#include "intel_lt_phy.h"
>   #include "intel_panel.h"
>   #include "intel_psr.h"
>   #include "intel_snps_hdmi_pll.h"
> @@ -3155,8 +3156,8 @@ static int intel_mtl_tbt_clock_select(struct intel_display *display,
>   	}
>   }
>   
> -static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
> -				     const struct intel_crtc_state *crtc_state)
> +void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
> +			      const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(encoder);
>   	enum phy phy = intel_encoder_to_phy(encoder);
> @@ -3340,7 +3341,7 @@ static bool intel_cx0_pll_is_enabled(struct intel_encoder *encoder)
>   			     intel_cx0_get_pclk_pll_request(lane);
>   }
>   
> -static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
> +void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
>   {
>   	struct intel_display *display = to_intel_display(encoder);
>   	enum phy phy = intel_encoder_to_phy(encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index f0f0efa2d48b..a37827482a32 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -64,5 +64,8 @@ int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
>   void intel_cx0_pll_power_save_wa(struct intel_display *display);
>   void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
>   				 const struct intel_crtc_state *crtc_state);
> +void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
> +			      const struct intel_crtc_state *crtc_state);
> +void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder);
>   
>   #endif /* __INTEL_CX0_PHY_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c09aa759f4d4..6fcfdd0b0103 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -72,6 +72,7 @@
>   #include "intel_hotplug.h"
>   #include "intel_hti.h"
>   #include "intel_lspcon.h"
> +#include "intel_lt_phy.h"
>   #include "intel_mg_phy_regs.h"
>   #include "intel_modeset_lock.h"
>   #include "intel_panel.h"
> @@ -5224,7 +5225,11 @@ void intel_ddi_init(struct intel_display *display,
>   	encoder->cloneable = 0;
>   	encoder->pipe_mask = ~0;
>   
> -	if (DISPLAY_VER(display) >= 14) {
> +	if (HAS_LT_PHY(display)) {
> +		encoder->enable_clock = intel_xe3plpd_pll_enable;
> +		encoder->disable_clock = intel_xe3plpd_pll_disable;
> +		encoder->port_pll_type = intel_mtl_port_pll_type;
> +	} else if (DISPLAY_VER(display) >= 14) {
>   		encoder->enable_clock = intel_mtl_pll_enable;
>   		encoder->disable_clock = intel_mtl_pll_disable;
>   		encoder->port_pll_type = intel_mtl_port_pll_type;
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 747cce4a484a..d458909b5f12 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1692,3 +1692,24 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder)
>   
>   	intel_lt_phy_transaction_end(encoder, wakeref);
>   }
> +
> +void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
> +			      const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +
> +	if (intel_tc_port_in_tbt_alt_mode(dig_port))
> +		intel_mtl_tbt_pll_enable(encoder, crtc_state);
> +	else
> +		intel_lt_phy_pll_enable(encoder, crtc_state);
> +}
> +
> +void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
> +{
> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +
> +	if (intel_tc_port_in_tbt_alt_mode(dig_port))
> +		intel_mtl_tbt_pll_disable(encoder);
> +	else
> +		intel_lt_phy_pll_disable(encoder);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index 499091e04e82..15d3d680871c 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -20,6 +20,9 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
>   			    struct intel_encoder *encoder);
>   int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
>   				 const struct intel_crtc_state *crtc_state);
> +void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
> +			      const struct intel_crtc_state *crtc_state);
> +void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
>   
>   #define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35)
>   

[PATCH 17/25] drm/i915/ddi: Define LT Phy Swing tables

[Suraj Kandpal]

Define and initialize LT Phy Swing tables for DP 1.4, 2.1 and eDp.
HDMI TMDS is not needed since LT Phy H/w handles that.

Bspec: 74493
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../drm/i915/display/intel_ddi_buf_trans.c    | 81 ++++++++++++++++++-
 .../drm/i915/display/intel_ddi_buf_trans.h    |  9 +++
 2 files changed, 89 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index a238be5bc455..f39e690e9ed2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -10,6 +10,7 @@
 #include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
+#include "intel_lt_phy.h"
 
 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  * them for both DP and FDI transports, allowing those ports to
@@ -1115,6 +1116,69 @@ static const struct intel_ddi_buf_trans mtl_c20_trans_uhbr = {
 	.num_entries = ARRAY_SIZE(_mtl_c20_trans_uhbr),
 };
 
+/* DP1.4 */
+static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_dp14[] = {
+	{ .lt = { 1, 0, 0, 21, 0  } },
+	{ .lt = { 1, 1, 0, 24, 3  } },
+	{ .lt = { 1, 2, 0, 28, 7  } },
+	{ .lt = { 0, 3, 0, 35, 13 } },
+	{ .lt = { 1, 1, 0, 27, 0  } },
+	{ .lt = { 1, 2, 0, 31, 4  } },
+	{ .lt = { 0, 3, 0, 39, 9  } },
+	{ .lt = { 1, 2, 0, 35, 0  } },
+	{ .lt = { 0, 3, 0, 41, 7  } },
+	{ .lt = { 0, 3, 0, 48, 0  } },
+};
+
+/* DP2.1 */
+static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_uhbr[] = {
+	{ .lt = { 0, 0, 0, 48, 0  } },
+	{ .lt = { 0, 0, 0, 43, 5  } },
+	{ .lt = { 0, 0, 0, 40, 8  } },
+	{ .lt = { 0, 0, 0, 37, 11 } },
+	{ .lt = { 0, 0, 0, 33, 15 } },
+	{ .lt = { 0, 0, 2, 46, 0  } },
+	{ .lt = { 0, 0, 2, 42, 4  } },
+	{ .lt = { 0, 0, 2, 38, 8  } },
+	{ .lt = { 0, 0, 2, 35, 11 } },
+	{ .lt = { 0, 0, 2, 33, 13 } },
+	{ .lt = { 0, 0, 4, 44, 0  } },
+	{ .lt = { 0, 0, 4, 40, 4  } },
+	{ .lt = { 0, 0, 4, 37, 7  } },
+	{ .lt = { 0, 0, 4, 33, 11 } },
+	{ .lt = { 0, 0, 8, 40, 0  } },
+	{ .lt = { 1, 0, 2, 26, 2  } },
+};
+
+/* eDp */
+static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_edp[] = {
+	{ .lt = { 1, 0, 0, 12, 0 } },
+	{ .lt = { 1, 1, 0, 13, 1 } },
+	{ .lt = { 1, 2, 0, 15, 3 } },
+	{ .lt = { 1, 3, 0, 19, 7 } },
+	{ .lt = { 1, 1, 0, 14, 0 } },
+	{ .lt = { 1, 2, 0, 16, 2 } },
+	{ .lt = { 1, 3, 0, 21, 5 } },
+	{ .lt = { 1, 2, 0, 18, 0 } },
+	{ .lt = { 1, 3, 0, 22, 4 } },
+	{ .lt = { 1, 3, 0, 26, 0 } },
+};
+
+static const struct intel_ddi_buf_trans xe3plpd_lt_trans_dp14 = {
+	.entries = _xe3plpd_lt_trans_dp14,
+	.num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_dp14),
+};
+
+static const struct intel_ddi_buf_trans xe3plpd_lt_trans_uhbr = {
+	.entries = _xe3plpd_lt_trans_uhbr,
+	.num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_uhbr),
+};
+
+static const struct intel_ddi_buf_trans xe3plpd_lt_trans_edp = {
+	.entries = _xe3plpd_lt_trans_edp,
+	.num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_edp),
+};
+
 bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
 {
 	return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
@@ -1707,11 +1771,26 @@ mtl_get_c20_buf_trans(struct intel_encoder *encoder,
 		return intel_get_buf_trans(&mtl_c20_trans_dp14, n_entries);
 }
 
+static const struct intel_ddi_buf_trans *
+xe3plpd_get_lt_buf_trans(struct intel_encoder *encoder,
+			 const struct intel_crtc_state *crtc_state,
+			 int *n_entries)
+{
+	if (intel_crtc_has_dp_encoder(crtc_state) && intel_dp_is_uhbr(crtc_state))
+		return intel_get_buf_trans(&xe3plpd_lt_trans_uhbr, n_entries);
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+		return intel_get_buf_trans(&xe3plpd_lt_trans_edp, n_entries);
+	else
+		return intel_get_buf_trans(&xe3plpd_lt_trans_dp14, n_entries);
+}
+
 void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
 
-	if (DISPLAY_VER(display) >= 14) {
+	if (HAS_LT_PHY(display)) {
+		encoder->get_buf_trans = xe3plpd_get_lt_buf_trans;
+	} else if (DISPLAY_VER(display) >= 14) {
 		if (intel_encoder_is_c10phy(encoder))
 			encoder->get_buf_trans = mtl_get_c10_buf_trans;
 		else
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
index 29a190390192..cec332090a20 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
@@ -50,6 +50,14 @@ struct dg2_snps_phy_buf_trans {
 	u8 post_cursor;
 };
 
+struct xe3plpd_lt_phy_buf_trans {
+	u8 txswing;
+	u8 txswing_level;
+	u8 pre_cursor;
+	u8 main_cursor;
+	u8 post_cursor;
+};
+
 union intel_ddi_buf_trans_entry {
 	struct hsw_ddi_buf_trans hsw;
 	struct bxt_ddi_buf_trans bxt;
@@ -57,6 +65,7 @@ union intel_ddi_buf_trans_entry {
 	struct icl_mg_phy_ddi_buf_trans mg;
 	struct tgl_dkl_phy_ddi_buf_trans dkl;
 	struct dg2_snps_phy_buf_trans snps;
+	struct xe3plpd_lt_phy_buf_trans lt;
 };
 
 struct intel_ddi_buf_trans {
-- 
2.34.1

Re: [PATCH 17/25] drm/i915/ddi: Define LT Phy Swing tables

[Murthy, Arun R]

On 15-10-2025 09:38, Suraj Kandpal wrote:
> Define and initialize LT Phy Swing tables for DP 1.4, 2.1 and eDp.
> HDMI TMDS is not needed since LT Phy H/w handles that.
>
> Bspec: 74493
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>   .../drm/i915/display/intel_ddi_buf_trans.c    | 81 ++++++++++++++++++-
>   .../drm/i915/display/intel_ddi_buf_trans.h    |  9 +++
>   2 files changed, 89 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index a238be5bc455..f39e690e9ed2 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -10,6 +10,7 @@
>   #include "intel_de.h"
>   #include "intel_display_types.h"
>   #include "intel_dp.h"
> +#include "intel_lt_phy.h"
>   
>   /* HDMI/DVI modes ignore everything but the last 2 items. So we share
>    * them for both DP and FDI transports, allowing those ports to
> @@ -1115,6 +1116,69 @@ static const struct intel_ddi_buf_trans mtl_c20_trans_uhbr = {
>   	.num_entries = ARRAY_SIZE(_mtl_c20_trans_uhbr),
>   };
>   
> +/* DP1.4 */
> +static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_dp14[] = {
> +	{ .lt = { 1, 0, 0, 21, 0  } },
> +	{ .lt = { 1, 1, 0, 24, 3  } },
> +	{ .lt = { 1, 2, 0, 28, 7  } },
> +	{ .lt = { 0, 3, 0, 35, 13 } },
> +	{ .lt = { 1, 1, 0, 27, 0  } },
> +	{ .lt = { 1, 2, 0, 31, 4  } },
> +	{ .lt = { 0, 3, 0, 39, 9  } },
> +	{ .lt = { 1, 2, 0, 35, 0  } },
> +	{ .lt = { 0, 3, 0, 41, 7  } },
> +	{ .lt = { 0, 3, 0, 48, 0  } },
> +};
> +
> +/* DP2.1 */
> +static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_uhbr[] = {
> +	{ .lt = { 0, 0, 0, 48, 0  } },
> +	{ .lt = { 0, 0, 0, 43, 5  } },
> +	{ .lt = { 0, 0, 0, 40, 8  } },
> +	{ .lt = { 0, 0, 0, 37, 11 } },
> +	{ .lt = { 0, 0, 0, 33, 15 } },
> +	{ .lt = { 0, 0, 2, 46, 0  } },
> +	{ .lt = { 0, 0, 2, 42, 4  } },
> +	{ .lt = { 0, 0, 2, 38, 8  } },
> +	{ .lt = { 0, 0, 2, 35, 11 } },
> +	{ .lt = { 0, 0, 2, 33, 13 } },
> +	{ .lt = { 0, 0, 4, 44, 0  } },
> +	{ .lt = { 0, 0, 4, 40, 4  } },
> +	{ .lt = { 0, 0, 4, 37, 7  } },
> +	{ .lt = { 0, 0, 4, 33, 11 } },
> +	{ .lt = { 0, 0, 8, 40, 0  } },
> +	{ .lt = { 1, 0, 2, 26, 2  } },
> +};
> +
> +/* eDp */
> +static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_edp[] = {
> +	{ .lt = { 1, 0, 0, 12, 0 } },
> +	{ .lt = { 1, 1, 0, 13, 1 } },
> +	{ .lt = { 1, 2, 0, 15, 3 } },
> +	{ .lt = { 1, 3, 0, 19, 7 } },
> +	{ .lt = { 1, 1, 0, 14, 0 } },
> +	{ .lt = { 1, 2, 0, 16, 2 } },
> +	{ .lt = { 1, 3, 0, 21, 5 } },
> +	{ .lt = { 1, 2, 0, 18, 0 } },
> +	{ .lt = { 1, 3, 0, 22, 4 } },
> +	{ .lt = { 1, 3, 0, 26, 0 } },
> +};
> +
> +static const struct intel_ddi_buf_trans xe3plpd_lt_trans_dp14 = {
> +	.entries = _xe3plpd_lt_trans_dp14,
> +	.num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_dp14),
> +};
> +
> +static const struct intel_ddi_buf_trans xe3plpd_lt_trans_uhbr = {
> +	.entries = _xe3plpd_lt_trans_uhbr,
> +	.num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_uhbr),
> +};
> +
> +static const struct intel_ddi_buf_trans xe3plpd_lt_trans_edp = {
> +	.entries = _xe3plpd_lt_trans_edp,
> +	.num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_edp),
> +};
> +
>   bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
>   {
>   	return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
> @@ -1707,11 +1771,26 @@ mtl_get_c20_buf_trans(struct intel_encoder *encoder,
>   		return intel_get_buf_trans(&mtl_c20_trans_dp14, n_entries);
>   }
>   
> +static const struct intel_ddi_buf_trans *
> +xe3plpd_get_lt_buf_trans(struct intel_encoder *encoder,
> +			 const struct intel_crtc_state *crtc_state,
> +			 int *n_entries)
> +{
> +	if (intel_crtc_has_dp_encoder(crtc_state) && intel_dp_is_uhbr(crtc_state))
> +		return intel_get_buf_trans(&xe3plpd_lt_trans_uhbr, n_entries);
> +	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> +		return intel_get_buf_trans(&xe3plpd_lt_trans_edp, n_entries);
> +	else
> +		return intel_get_buf_trans(&xe3plpd_lt_trans_dp14, n_entries);
> +}
> +
>   void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
>   {
>   	struct intel_display *display = to_intel_display(encoder);
>   
> -	if (DISPLAY_VER(display) >= 14) {
> +	if (HAS_LT_PHY(display)) {
> +		encoder->get_buf_trans = xe3plpd_get_lt_buf_trans;
> +	} else if (DISPLAY_VER(display) >= 14) {
>   		if (intel_encoder_is_c10phy(encoder))
>   			encoder->get_buf_trans = mtl_get_c10_buf_trans;
>   		else
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> index 29a190390192..cec332090a20 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> @@ -50,6 +50,14 @@ struct dg2_snps_phy_buf_trans {
>   	u8 post_cursor;
>   };
>   
> +struct xe3plpd_lt_phy_buf_trans {
> +	u8 txswing;
> +	u8 txswing_level;
> +	u8 pre_cursor;
> +	u8 main_cursor;
> +	u8 post_cursor;
> +};
> +
>   union intel_ddi_buf_trans_entry {
>   	struct hsw_ddi_buf_trans hsw;
>   	struct bxt_ddi_buf_trans bxt;
> @@ -57,6 +65,7 @@ union intel_ddi_buf_trans_entry {
>   	struct icl_mg_phy_ddi_buf_trans mg;
>   	struct tgl_dkl_phy_ddi_buf_trans dkl;
>   	struct dg2_snps_phy_buf_trans snps;
> +	struct xe3plpd_lt_phy_buf_trans lt;
>   };
>   
>   struct intel_ddi_buf_trans {

[PATCH 18/25] drm/i915/ltphy: Program LT Phy Voltage Swing

[Suraj Kandpal]

Program LT Phy voltage swing using the Swing tables and plug in the
function at encoder->set_signal_level

Bspec: 74493
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      | 13 +++-
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 63 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |  2 +
 .../gpu/drm/i915/display/intel_lt_phy_regs.h  | 13 ++++
 4 files changed, 88 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6fcfdd0b0103..b6345508cb66 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1467,10 +1467,15 @@ static int translate_signal_level(struct intel_dp *intel_dp,
 				  u8 signal_levels)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
+	const u8 *signal_array;
+	size_t array_size;
 	int i;
 
-	for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
-		if (index_to_dp_signal_levels[i] == signal_levels)
+	signal_array = index_to_dp_signal_levels;
+	array_size = ARRAY_SIZE(index_to_dp_signal_levels);
+
+	for (i = 0; i < array_size; i++) {
+		if (signal_array[i] == signal_levels)
 			return i;
 	}
 
@@ -5294,7 +5299,9 @@ void intel_ddi_init(struct intel_display *display,
 		encoder->get_config = hsw_ddi_get_config;
 	}
 
-	if (DISPLAY_VER(display) >= 14) {
+	if (HAS_LT_PHY(display)) {
+		encoder->set_signal_levels = intel_lt_phy_set_signal_levels;
+	} else if (DISPLAY_VER(display) >= 14) {
 		encoder->set_signal_levels = intel_cx0_phy_set_signal_levels;
 	} else if (display->platform.dg2) {
 		encoder->set_signal_levels = intel_snps_phy_set_signal_levels;
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index d458909b5f12..359a2dbf0847 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -9,6 +9,8 @@
 #include "i915_utils.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
+#include "intel_ddi.h"
+#include "intel_ddi_buf_trans.h"
 #include "intel_de.h"
 #include "intel_display.h"
 #include "intel_display_types.h"
@@ -1003,6 +1005,12 @@ static void intel_lt_phy_write(struct intel_encoder *encoder,
 	intel_cx0_write(encoder, lane_mask, addr, data, committed);
 }
 
+static void intel_lt_phy_rmw(struct intel_encoder *encoder,
+			     u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed)
+{
+	intel_cx0_rmw(encoder, lane_mask, addr, clear, set, committed);
+}
+
 static void intel_lt_phy_clear_status_p2p(struct intel_encoder *encoder,
 					  int lane)
 {
@@ -1693,6 +1701,61 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder)
 	intel_lt_phy_transaction_end(encoder, wakeref);
 }
 
+void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
+				    const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	const struct intel_ddi_buf_trans *trans;
+	u8 owned_lane_mask;
+	intel_wakeref_t wakeref;
+	int n_entries, ln;
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+	if (intel_tc_port_in_tbt_alt_mode(dig_port))
+		return;
+
+	owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
+
+	wakeref = intel_lt_phy_transaction_begin(encoder);
+
+	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
+	if (drm_WARN_ON_ONCE(display->drm, !trans)) {
+		intel_lt_phy_transaction_end(encoder, wakeref);
+		return;
+	}
+
+	for (ln = 0; ln < crtc_state->lane_count; ln++) {
+		int level = intel_ddi_level(encoder, crtc_state, ln);
+		int lane = ln / 2;
+		int tx = ln % 2;
+		u8 lane_mask = lane == 0 ? INTEL_LT_PHY_LANE0 : INTEL_LT_PHY_LANE1;
+
+		if (!(lane_mask & owned_lane_mask))
+			continue;
+
+		intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL8(tx),
+				 LT_PHY_TX_SWING_LEVEL_MASK | LT_PHY_TX_SWING_MASK,
+				 LT_PHY_TX_SWING_LEVEL(trans->entries[level].lt.txswing_level) |
+				 LT_PHY_TX_SWING(trans->entries[level].lt.txswing),
+				 MB_WRITE_COMMITTED);
+
+		intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL2(tx),
+				 LT_PHY_TX_CURSOR_MASK,
+				 LT_PHY_TX_CURSOR(trans->entries[level].lt.pre_cursor),
+				 MB_WRITE_COMMITTED);
+		intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL3(tx),
+				 LT_PHY_TX_CURSOR_MASK,
+				 LT_PHY_TX_CURSOR(trans->entries[level].lt.main_cursor),
+				 MB_WRITE_COMMITTED);
+		intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL4(tx),
+				 LT_PHY_TX_CURSOR_MASK,
+				 LT_PHY_TX_CURSOR(trans->entries[level].lt.post_cursor),
+				 MB_WRITE_COMMITTED);
+	}
+
+	intel_lt_phy_transaction_end(encoder, wakeref);
+}
+
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 15d3d680871c..6e67ae78801c 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -20,6 +20,8 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 			    struct intel_encoder *encoder);
 int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state);
+void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
+				    const struct intel_crtc_state *crtc_state);
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state);
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
index c641cc957f1b..1eab328c70f4 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
@@ -22,6 +22,19 @@
 #define LT_PHY_MAC_VDR			_MMIO(0xC00)
 #define    LT_PHY_PCLKIN_GATE		REG_BIT8(0)
 
+/* LT Phy Pipe Spec Registers */
+#define LT_PHY_TXY_CTL8(idx)		(0x408 + (0x200 * (idx)))
+#define  LT_PHY_TX_SWING_LEVEL_MASK	REG_GENMASK8(7, 4)
+#define  LT_PHY_TX_SWING_LEVEL(val)	REG_FIELD_PREP8(LT_PHY_TX_SWING_LEVEL_MASK, val)
+#define  LT_PHY_TX_SWING_MASK		REG_BIT8(3)
+#define  LT_PHY_TX_SWING(val)		REG_FIELD_PREP8(LT_PHY_TX_SWING_MASK, val)
+
+#define LT_PHY_TXY_CTL2(idx)		(0x402 + (0x200 * (idx)))
+#define LT_PHY_TXY_CTL3(idx)		(0x403 + (0x200 * (idx)))
+#define LT_PHY_TXY_CTL4(idx)		(0x404 + (0x200 * (idx)))
+#define  LT_PHY_TX_CURSOR_MASK		REG_GENMASK8(5, 0)
+#define  LT_PHY_TX_CURSOR(val)		REG_FIELD_PREP8(LT_PHY_TX_CURSOR_MASK, val)
+
 /* LT Phy Vendor Register */
 #define LT_PHY_VDR_0_CONFIG	0xC02
 #define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
-- 
2.34.1

Re: [PATCH 18/25] drm/i915/ltphy: Program LT Phy Voltage Swing

[Murthy, Arun R]

On 15-10-2025 09:38, Suraj Kandpal wrote:
> Program LT Phy voltage swing using the Swing tables and plug in the
> function at encoder->set_signal_level
>
> Bspec: 74493
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>   drivers/gpu/drm/i915/display/intel_ddi.c      | 13 +++-
>   drivers/gpu/drm/i915/display/intel_lt_phy.c   | 63 +++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_lt_phy.h   |  2 +
>   .../gpu/drm/i915/display/intel_lt_phy_regs.h  | 13 ++++
>   4 files changed, 88 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 6fcfdd0b0103..b6345508cb66 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1467,10 +1467,15 @@ static int translate_signal_level(struct intel_dp *intel_dp,
>   				  u8 signal_levels)
>   {
>   	struct intel_display *display = to_intel_display(intel_dp);
> +	const u8 *signal_array;
> +	size_t array_size;
>   	int i;
>   
> -	for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
> -		if (index_to_dp_signal_levels[i] == signal_levels)
> +	signal_array = index_to_dp_signal_levels;
> +	array_size = ARRAY_SIZE(index_to_dp_signal_levels);
> +
> +	for (i = 0; i < array_size; i++) {
> +		if (signal_array[i] == signal_levels)
>   			return i;
>   	}
>   
> @@ -5294,7 +5299,9 @@ void intel_ddi_init(struct intel_display *display,
>   		encoder->get_config = hsw_ddi_get_config;
>   	}
>   
> -	if (DISPLAY_VER(display) >= 14) {
> +	if (HAS_LT_PHY(display)) {
> +		encoder->set_signal_levels = intel_lt_phy_set_signal_levels;
> +	} else if (DISPLAY_VER(display) >= 14) {
>   		encoder->set_signal_levels = intel_cx0_phy_set_signal_levels;
>   	} else if (display->platform.dg2) {
>   		encoder->set_signal_levels = intel_snps_phy_set_signal_levels;
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index d458909b5f12..359a2dbf0847 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -9,6 +9,8 @@
>   #include "i915_utils.h"
>   #include "intel_cx0_phy.h"
>   #include "intel_cx0_phy_regs.h"
> +#include "intel_ddi.h"
> +#include "intel_ddi_buf_trans.h"
>   #include "intel_de.h"
>   #include "intel_display.h"
>   #include "intel_display_types.h"
> @@ -1003,6 +1005,12 @@ static void intel_lt_phy_write(struct intel_encoder *encoder,
>   	intel_cx0_write(encoder, lane_mask, addr, data, committed);
>   }
>   
> +static void intel_lt_phy_rmw(struct intel_encoder *encoder,
> +			     u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed)
> +{
> +	intel_cx0_rmw(encoder, lane_mask, addr, clear, set, committed);
> +}
> +
>   static void intel_lt_phy_clear_status_p2p(struct intel_encoder *encoder,
>   					  int lane)
>   {
> @@ -1693,6 +1701,61 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder)
>   	intel_lt_phy_transaction_end(encoder, wakeref);
>   }
>   
> +void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
> +				    const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	const struct intel_ddi_buf_trans *trans;
> +	u8 owned_lane_mask;
> +	intel_wakeref_t wakeref;
> +	int n_entries, ln;
> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +
> +	if (intel_tc_port_in_tbt_alt_mode(dig_port))
> +		return;
> +
> +	owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
> +
> +	wakeref = intel_lt_phy_transaction_begin(encoder);
> +
> +	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
> +	if (drm_WARN_ON_ONCE(display->drm, !trans)) {
> +		intel_lt_phy_transaction_end(encoder, wakeref);
> +		return;
> +	}
> +
> +	for (ln = 0; ln < crtc_state->lane_count; ln++) {
> +		int level = intel_ddi_level(encoder, crtc_state, ln);
> +		int lane = ln / 2;
> +		int tx = ln % 2;
> +		u8 lane_mask = lane == 0 ? INTEL_LT_PHY_LANE0 : INTEL_LT_PHY_LANE1;
> +
> +		if (!(lane_mask & owned_lane_mask))
> +			continue;
> +
> +		intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL8(tx),
> +				 LT_PHY_TX_SWING_LEVEL_MASK | LT_PHY_TX_SWING_MASK,
> +				 LT_PHY_TX_SWING_LEVEL(trans->entries[level].lt.txswing_level) |
> +				 LT_PHY_TX_SWING(trans->entries[level].lt.txswing),
> +				 MB_WRITE_COMMITTED);
> +
> +		intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL2(tx),
> +				 LT_PHY_TX_CURSOR_MASK,
> +				 LT_PHY_TX_CURSOR(trans->entries[level].lt.pre_cursor),
> +				 MB_WRITE_COMMITTED);
> +		intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL3(tx),
> +				 LT_PHY_TX_CURSOR_MASK,
> +				 LT_PHY_TX_CURSOR(trans->entries[level].lt.main_cursor),
> +				 MB_WRITE_COMMITTED);
> +		intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL4(tx),
> +				 LT_PHY_TX_CURSOR_MASK,
> +				 LT_PHY_TX_CURSOR(trans->entries[level].lt.post_cursor),
> +				 MB_WRITE_COMMITTED);
> +	}
> +
> +	intel_lt_phy_transaction_end(encoder, wakeref);
> +}
> +
>   void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
>   			      const struct intel_crtc_state *crtc_state)
>   {
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index 15d3d680871c..6e67ae78801c 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -20,6 +20,8 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
>   			    struct intel_encoder *encoder);
>   int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
>   				 const struct intel_crtc_state *crtc_state);
> +void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
> +				    const struct intel_crtc_state *crtc_state);
>   void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
>   			      const struct intel_crtc_state *crtc_state);
>   void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> index c641cc957f1b..1eab328c70f4 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> @@ -22,6 +22,19 @@
>   #define LT_PHY_MAC_VDR			_MMIO(0xC00)
>   #define    LT_PHY_PCLKIN_GATE		REG_BIT8(0)
>   
> +/* LT Phy Pipe Spec Registers */
> +#define LT_PHY_TXY_CTL8(idx)		(0x408 + (0x200 * (idx)))
> +#define  LT_PHY_TX_SWING_LEVEL_MASK	REG_GENMASK8(7, 4)
> +#define  LT_PHY_TX_SWING_LEVEL(val)	REG_FIELD_PREP8(LT_PHY_TX_SWING_LEVEL_MASK, val)
> +#define  LT_PHY_TX_SWING_MASK		REG_BIT8(3)
> +#define  LT_PHY_TX_SWING(val)		REG_FIELD_PREP8(LT_PHY_TX_SWING_MASK, val)
> +
> +#define LT_PHY_TXY_CTL2(idx)		(0x402 + (0x200 * (idx)))
> +#define LT_PHY_TXY_CTL3(idx)		(0x403 + (0x200 * (idx)))
> +#define LT_PHY_TXY_CTL4(idx)		(0x404 + (0x200 * (idx)))
> +#define  LT_PHY_TX_CURSOR_MASK		REG_GENMASK8(5, 0)
> +#define  LT_PHY_TX_CURSOR(val)		REG_FIELD_PREP8(LT_PHY_TX_CURSOR_MASK, val)
> +
>   /* LT Phy Vendor Register */
>   #define LT_PHY_VDR_0_CONFIG	0xC02
>   #define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)

[PATCH 19/25] drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence

[Suraj Kandpal]

We need to enable and disable the Tx for each active lane after the
Non-TBT enable sequence is done.

Bspec: 74500, 74497, 74701
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 87 +++++++++++++++++++
 .../gpu/drm/i915/display/intel_lt_phy_regs.h  |  4 +
 2 files changed, 91 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 359a2dbf0847..f1e41f009bb5 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1494,6 +1494,92 @@ intel_lt_phy_program_pll(struct intel_encoder *encoder,
 	}
 }
 
+static void
+intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
+			       const struct intel_crtc_state *crtc_state)
+{
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+	bool lane_reversal = dig_port->lane_reversal;
+	u8 lane_count = crtc_state->lane_count;
+	bool is_dp_alt =
+		intel_tc_port_in_dp_alt_mode(dig_port);
+	enum intel_tc_pin_assignment tc_pin =
+		intel_tc_port_get_pin_assignment(dig_port);
+	u8 transmitter_mask = 0;
+
+	/*
+	 * We have a two transmitters per lane and total of 2 PHY lanes so a total
+	 * of 4 transmitters. We prepare a mask of the lanes that need to be activated
+	 * and the transmitter which need to be activated for each lane. TX 0,1 correspond
+	 * to LANE0 and TX 2, 3 correspond to LANE1.
+	 */
+
+	switch (lane_count) {
+	case 1:
+		transmitter_mask = lane_reversal ? REG_BIT8(3) : REG_BIT8(0);
+		if (is_dp_alt) {
+			if (tc_pin == INTEL_TC_PIN_ASSIGNMENT_D)
+				transmitter_mask = REG_BIT8(0);
+			else
+				transmitter_mask = REG_BIT8(1);
+		}
+		break;
+	case 2:
+		transmitter_mask = lane_reversal ? REG_GENMASK8(3, 2) : REG_GENMASK8(1, 0);
+		if (is_dp_alt)
+			transmitter_mask = REG_GENMASK8(1, 0);
+		break;
+	case 3:
+		transmitter_mask = lane_reversal ? REG_GENMASK8(3, 1) : REG_GENMASK8(2, 0);
+		if (is_dp_alt)
+			transmitter_mask = REG_GENMASK8(2, 0);
+		break;
+	case 4:
+		transmitter_mask = REG_GENMASK8(3, 0);
+		break;
+	default:
+		MISSING_CASE(lane_count);
+		transmitter_mask = REG_GENMASK8(3, 0);
+		break;
+	}
+
+	if (transmitter_mask & BIT(0)) {
+		intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(0),
+				       LT_PHY_TX_LANE_ENABLE, LT_PHY_TXY_CTL10_MAC(0),
+				       LT_PHY_TX_LANE_ENABLE);
+	} else {
+		intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(0),
+				       0, LT_PHY_TXY_CTL10_MAC(0), 0);
+	}
+
+	if (transmitter_mask & BIT(1)) {
+		intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(1),
+				       LT_PHY_TX_LANE_ENABLE, LT_PHY_TXY_CTL10_MAC(1),
+				       LT_PHY_TX_LANE_ENABLE);
+	} else {
+		intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(1),
+				       0, LT_PHY_TXY_CTL10_MAC(1), 0);
+	}
+
+	if (transmitter_mask & BIT(2)) {
+		intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE1, LT_PHY_TXY_CTL10(0),
+				       LT_PHY_TX_LANE_ENABLE, LT_PHY_TXY_CTL10_MAC(0),
+				       LT_PHY_TX_LANE_ENABLE);
+	} else {
+		intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE1, LT_PHY_TXY_CTL10(0),
+				       0, LT_PHY_TXY_CTL10_MAC(0), 0);
+	}
+
+	if (transmitter_mask & BIT(3)) {
+		intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE1, LT_PHY_TXY_CTL10(1),
+				       LT_PHY_TX_LANE_ENABLE, LT_PHY_TXY_CTL10_MAC(1),
+				       LT_PHY_TX_LANE_ENABLE);
+	} else {
+		intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE1, LT_PHY_TXY_CTL10(1),
+				       0, LT_PHY_TXY_CTL10_MAC(1), 0);
+	}
+}
+
 void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 			     const struct intel_crtc_state *crtc_state)
 {
@@ -1620,6 +1706,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
 					       XELPDP_P0_STATE_ACTIVE);
 
+	intel_lt_phy_enable_disable_tx(encoder, crtc_state);
 	intel_lt_phy_transaction_end(encoder, wakeref);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
index 1eab328c70f4..b8d02c39e738 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
@@ -35,6 +35,10 @@
 #define  LT_PHY_TX_CURSOR_MASK		REG_GENMASK8(5, 0)
 #define  LT_PHY_TX_CURSOR(val)		REG_FIELD_PREP8(LT_PHY_TX_CURSOR_MASK, val)
 
+#define LT_PHY_TXY_CTL10(idx)		(0x40A + (0x200 * (idx)))
+#define LT_PHY_TXY_CTL10_MAC(idx)	_MMIO(LT_PHY_TXY_CTL10(idx))
+#define  LT_PHY_TX_LANE_ENABLE		REG_BIT8(0)
+
 /* LT Phy Vendor Register */
 #define LT_PHY_VDR_0_CONFIG	0xC02
 #define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
-- 
2.34.1

Re: [PATCH 19/25] drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence

[Murthy, Arun R]

On 15-10-2025 09:38, Suraj Kandpal wrote:
> We need to enable and disable the Tx for each active lane after the
> Non-TBT enable sequence is done.
>
> Bspec: 74500, 74497, 74701
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>   drivers/gpu/drm/i915/display/intel_lt_phy.c   | 87 +++++++++++++++++++
>   .../gpu/drm/i915/display/intel_lt_phy_regs.h  |  4 +
>   2 files changed, 91 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 359a2dbf0847..f1e41f009bb5 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1494,6 +1494,92 @@ intel_lt_phy_program_pll(struct intel_encoder *encoder,
>   	}
>   }
>   
> +static void
> +intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
> +			       const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +	bool lane_reversal = dig_port->lane_reversal;
> +	u8 lane_count = crtc_state->lane_count;
> +	bool is_dp_alt =
> +		intel_tc_port_in_dp_alt_mode(dig_port);
> +	enum intel_tc_pin_assignment tc_pin =
> +		intel_tc_port_get_pin_assignment(dig_port);
> +	u8 transmitter_mask = 0;
> +
> +	/*
> +	 * We have a two transmitters per lane and total of 2 PHY lanes so a total
> +	 * of 4 transmitters. We prepare a mask of the lanes that need to be activated
> +	 * and the transmitter which need to be activated for each lane. TX 0,1 correspond
> +	 * to LANE0 and TX 2, 3 correspond to LANE1.
> +	 */
> +
> +	switch (lane_count) {
> +	case 1:
> +		transmitter_mask = lane_reversal ? REG_BIT8(3) : REG_BIT8(0);
> +		if (is_dp_alt) {
> +			if (tc_pin == INTEL_TC_PIN_ASSIGNMENT_D)
> +				transmitter_mask = REG_BIT8(0);
> +			else
> +				transmitter_mask = REG_BIT8(1);
> +		}
> +		break;
> +	case 2:
> +		transmitter_mask = lane_reversal ? REG_GENMASK8(3, 2) : REG_GENMASK8(1, 0);
> +		if (is_dp_alt)
> +			transmitter_mask = REG_GENMASK8(1, 0);
> +		break;
> +	case 3:
> +		transmitter_mask = lane_reversal ? REG_GENMASK8(3, 1) : REG_GENMASK8(2, 0);
> +		if (is_dp_alt)
> +			transmitter_mask = REG_GENMASK8(2, 0);
> +		break;
> +	case 4:
> +		transmitter_mask = REG_GENMASK8(3, 0);
> +		break;
> +	default:
> +		MISSING_CASE(lane_count);
> +		transmitter_mask = REG_GENMASK8(3, 0);
> +		break;
> +	}
> +
> +	if (transmitter_mask & BIT(0)) {
> +		intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(0),
> +				       LT_PHY_TX_LANE_ENABLE, LT_PHY_TXY_CTL10_MAC(0),
> +				       LT_PHY_TX_LANE_ENABLE);
> +	} else {
> +		intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(0),
> +				       0, LT_PHY_TXY_CTL10_MAC(0), 0);
> +	}
> +
> +	if (transmitter_mask & BIT(1)) {
> +		intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(1),
> +				       LT_PHY_TX_LANE_ENABLE, LT_PHY_TXY_CTL10_MAC(1),
> +				       LT_PHY_TX_LANE_ENABLE);
> +	} else {
> +		intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(1),
> +				       0, LT_PHY_TXY_CTL10_MAC(1), 0);
> +	}
> +
> +	if (transmitter_mask & BIT(2)) {
> +		intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE1, LT_PHY_TXY_CTL10(0),
> +				       LT_PHY_TX_LANE_ENABLE, LT_PHY_TXY_CTL10_MAC(0),
> +				       LT_PHY_TX_LANE_ENABLE);
> +	} else {
> +		intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE1, LT_PHY_TXY_CTL10(0),
> +				       0, LT_PHY_TXY_CTL10_MAC(0), 0);
> +	}
> +
> +	if (transmitter_mask & BIT(3)) {
> +		intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE1, LT_PHY_TXY_CTL10(1),
> +				       LT_PHY_TX_LANE_ENABLE, LT_PHY_TXY_CTL10_MAC(1),
> +				       LT_PHY_TX_LANE_ENABLE);
> +	} else {
> +		intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE1, LT_PHY_TXY_CTL10(1),
> +				       0, LT_PHY_TXY_CTL10_MAC(1), 0);
> +	}
> +}
> +
>   void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   			     const struct intel_crtc_state *crtc_state)
>   {
> @@ -1620,6 +1706,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   	intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
>   					       XELPDP_P0_STATE_ACTIVE);
>   
> +	intel_lt_phy_enable_disable_tx(encoder, crtc_state);
>   	intel_lt_phy_transaction_end(encoder, wakeref);
>   }
>   
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> index 1eab328c70f4..b8d02c39e738 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> @@ -35,6 +35,10 @@
>   #define  LT_PHY_TX_CURSOR_MASK		REG_GENMASK8(5, 0)
>   #define  LT_PHY_TX_CURSOR(val)		REG_FIELD_PREP8(LT_PHY_TX_CURSOR_MASK, val)
>   
> +#define LT_PHY_TXY_CTL10(idx)		(0x40A + (0x200 * (idx)))
> +#define LT_PHY_TXY_CTL10_MAC(idx)	_MMIO(LT_PHY_TXY_CTL10(idx))
> +#define  LT_PHY_TX_LANE_ENABLE		REG_BIT8(0)
> +
>   /* LT Phy Vendor Register */
>   #define LT_PHY_VDR_0_CONFIG	0xC02
>   #define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)

[PATCH 20/25] drm/i915/ltphy: Define the LT Phy state compare function

[Suraj Kandpal]

Define function to compare the state and if mismatch is detected
dump both the states.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 33 +++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_lt_phy.c  | 30 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h  |  6 ++++
 3 files changed, 68 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d5b2612d4ec2..b05f70582788 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -99,6 +99,7 @@
 #include "intel_hdmi.h"
 #include "intel_hotplug.h"
 #include "intel_link_bw.h"
+#include "intel_lt_phy.h"
 #include "intel_lvds.h"
 #include "intel_lvds_regs.h"
 #include "intel_modeset_setup.h"
@@ -4963,6 +4964,24 @@ static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_s
 		!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
 }
 
+static void
+pipe_config_lt_phy_pll_mismatch(struct drm_printer *p, bool fastset,
+				const struct intel_crtc *crtc,
+				const char *name,
+				const struct intel_lt_phy_pll_state *a,
+				const struct intel_lt_phy_pll_state *b)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	char *chipname = "LTPHY";
+
+	pipe_config_mismatch(p, fastset, crtc, name, chipname);
+
+	drm_printf(p, "expected:\n");
+	intel_lt_phy_dump_hw_state(display, a);
+	drm_printf(p, "found:\n");
+	intel_lt_phy_dump_hw_state(display, b);
+}
+
 bool
 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 			  const struct intel_crtc_state *pipe_config,
@@ -5087,6 +5106,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	} \
 } while (0)
 
+#define PIPE_CONF_CHECK_PLL_LT(name) do { \
+	if (!intel_lt_phy_pll_compare_hw_state(&current_config->name, \
+					       &pipe_config->name)) { \
+		pipe_config_lt_phy_pll_mismatch(&p, fastset, crtc, __stringify(name), \
+						&current_config->name, \
+						&pipe_config->name); \
+		ret = false; \
+	} \
+} while (0)
+
 #define PIPE_CONF_CHECK_TIMINGS(name) do {     \
 	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
 	PIPE_CONF_CHECK_I(name.crtc_htotal); \
@@ -5311,7 +5340,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_PLL(dpll_hw_state);
 
 	/* FIXME convert MTL+ platforms over to dpll_mgr */
-	if (DISPLAY_VER(display) >= 14)
+	if (HAS_LT_PHY(display))
+		PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll);
+	else if (DISPLAY_VER(display) >= 14)
 		PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll);
 
 	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index f1e41f009bb5..0be4aad0efcc 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1843,6 +1843,36 @@ void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
 	intel_lt_phy_transaction_end(encoder, wakeref);
 }
 
+void intel_lt_phy_dump_hw_state(struct intel_display *display,
+				const struct intel_lt_phy_pll_state *hw_state)
+{
+	int i, j;
+
+	drm_dbg_kms(display->drm, "lt_phy_pll_hw_state:\n");
+	for (i = 0; i < 3; i++) {
+		drm_dbg_kms(display->drm, "config[%d] = 0x%.4x,\n",
+			    i, hw_state->config[i]);
+	}
+
+	for (i = 0; i <= 12; i++)
+		for (j = 3; j >= 0; j--)
+			drm_dbg_kms(display->drm, "vdr_data[%d][%d] = 0x%.4x,\n",
+				    i, j, hw_state->data[i][j]);
+}
+
+bool
+intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
+				  const struct intel_lt_phy_pll_state *b)
+{
+	if (memcmp(&a->config, &b->config, sizeof(a->config)) != 0)
+		return false;
+
+	if (memcmp(&a->data, &b->data, sizeof(a->data)) != 0)
+		return false;
+
+	return true;
+}
+
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 6e67ae78801c..e93e5becc316 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -8,6 +8,7 @@
 
 #include <linux/types.h>
 
+struct intel_display;
 struct intel_encoder;
 struct intel_crtc_state;
 struct intel_lt_phy_pll_state;
@@ -22,6 +23,11 @@ int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state);
 void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
 				    const struct intel_crtc_state *crtc_state);
+void intel_lt_phy_dump_hw_state(struct intel_display *display,
+				const struct intel_lt_phy_pll_state *hw_state);
+bool
+intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
+				  const struct intel_lt_phy_pll_state *b);
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state);
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
-- 
2.34.1

Re: [PATCH 20/25] drm/i915/ltphy: Define the LT Phy state compare function

[Murthy, Arun R]

On 15-10-2025 09:38, Suraj Kandpal wrote:
> Define function to compare the state and if mismatch is detected
> dump both the states.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>   drivers/gpu/drm/i915/display/intel_display.c | 33 +++++++++++++++++++-
>   drivers/gpu/drm/i915/display/intel_lt_phy.c  | 30 ++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_lt_phy.h  |  6 ++++
>   3 files changed, 68 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index d5b2612d4ec2..b05f70582788 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -99,6 +99,7 @@
>   #include "intel_hdmi.h"
>   #include "intel_hotplug.h"
>   #include "intel_link_bw.h"
> +#include "intel_lt_phy.h"
>   #include "intel_lvds.h"
>   #include "intel_lvds_regs.h"
>   #include "intel_modeset_setup.h"
> @@ -4963,6 +4964,24 @@ static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_s
>   		!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
>   }
>   
> +static void
> +pipe_config_lt_phy_pll_mismatch(struct drm_printer *p, bool fastset,
> +				const struct intel_crtc *crtc,
> +				const char *name,
> +				const struct intel_lt_phy_pll_state *a,
> +				const struct intel_lt_phy_pll_state *b)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	char *chipname = "LTPHY";
> +
> +	pipe_config_mismatch(p, fastset, crtc, name, chipname);
> +
> +	drm_printf(p, "expected:\n");
> +	intel_lt_phy_dump_hw_state(display, a);
> +	drm_printf(p, "found:\n");
> +	intel_lt_phy_dump_hw_state(display, b);
> +}
> +
>   bool
>   intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>   			  const struct intel_crtc_state *pipe_config,
> @@ -5087,6 +5106,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>   	} \
>   } while (0)
>   
> +#define PIPE_CONF_CHECK_PLL_LT(name) do { \
> +	if (!intel_lt_phy_pll_compare_hw_state(&current_config->name, \
> +					       &pipe_config->name)) { \
> +		pipe_config_lt_phy_pll_mismatch(&p, fastset, crtc, __stringify(name), \
> +						&current_config->name, \
> +						&pipe_config->name); \
> +		ret = false; \
> +	} \
> +} while (0)
> +
>   #define PIPE_CONF_CHECK_TIMINGS(name) do {     \
>   	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
>   	PIPE_CONF_CHECK_I(name.crtc_htotal); \
> @@ -5311,7 +5340,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>   		PIPE_CONF_CHECK_PLL(dpll_hw_state);
>   
>   	/* FIXME convert MTL+ platforms over to dpll_mgr */
> -	if (DISPLAY_VER(display) >= 14)
> +	if (HAS_LT_PHY(display))
> +		PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll);
> +	else if (DISPLAY_VER(display) >= 14)
>   		PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll);
>   
>   	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index f1e41f009bb5..0be4aad0efcc 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1843,6 +1843,36 @@ void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
>   	intel_lt_phy_transaction_end(encoder, wakeref);
>   }
>   
> +void intel_lt_phy_dump_hw_state(struct intel_display *display,
> +				const struct intel_lt_phy_pll_state *hw_state)
> +{
> +	int i, j;
> +
> +	drm_dbg_kms(display->drm, "lt_phy_pll_hw_state:\n");
> +	for (i = 0; i < 3; i++) {
> +		drm_dbg_kms(display->drm, "config[%d] = 0x%.4x,\n",
> +			    i, hw_state->config[i]);
> +	}
> +
> +	for (i = 0; i <= 12; i++)
> +		for (j = 3; j >= 0; j--)
> +			drm_dbg_kms(display->drm, "vdr_data[%d][%d] = 0x%.4x,\n",
> +				    i, j, hw_state->data[i][j]);
> +}
> +
> +bool
> +intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
> +				  const struct intel_lt_phy_pll_state *b)
> +{
> +	if (memcmp(&a->config, &b->config, sizeof(a->config)) != 0)
> +		return false;
> +
> +	if (memcmp(&a->data, &b->data, sizeof(a->data)) != 0)
> +		return false;
> +
> +	return true;
> +}
> +
>   void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
>   			      const struct intel_crtc_state *crtc_state)
>   {
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index 6e67ae78801c..e93e5becc316 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -8,6 +8,7 @@
>   
>   #include <linux/types.h>
>   
> +struct intel_display;
>   struct intel_encoder;
>   struct intel_crtc_state;
>   struct intel_lt_phy_pll_state;
> @@ -22,6 +23,11 @@ int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
>   				 const struct intel_crtc_state *crtc_state);
>   void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
>   				    const struct intel_crtc_state *crtc_state);
> +void intel_lt_phy_dump_hw_state(struct intel_display *display,
> +				const struct intel_lt_phy_pll_state *hw_state);
> +bool
> +intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
> +				  const struct intel_lt_phy_pll_state *b);
>   void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
>   			      const struct intel_crtc_state *crtc_state);
>   void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);

[PATCH 21/25] drm/i915/ltphy: Define function to readout LT Phy PLL state

[Suraj Kandpal]

Define a function to readout hw state for LT Phy PLL which
can be used in get_config function call.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c    | 14 +++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 33 +++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h |  3 ++
 3 files changed, 50 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b6345508cb66..e226ba8a4348 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4246,6 +4246,19 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
 						     &crtc_state->dpll_hw_state);
 }
 
+static void xe3plpd_ddi_get_config(struct intel_encoder *encoder,
+				   struct intel_crtc_state *crtc_state)
+{
+	intel_lt_phy_pll_readout_hw_state(encoder, crtc_state, &crtc_state->dpll_hw_state.ltpll);
+
+	if (crtc_state->dpll_hw_state.ltpll.tbt_mode)
+		crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
+	else
+		crtc_state->port_clock =
+			intel_lt_phy_calc_port_clock(encoder, crtc_state);
+	intel_ddi_get_config(encoder, crtc_state);
+}
+
 static void mtl_ddi_get_config(struct intel_encoder *encoder,
 			       struct intel_crtc_state *crtc_state)
 {
@@ -5234,6 +5247,7 @@ void intel_ddi_init(struct intel_display *display,
 		encoder->enable_clock = intel_xe3plpd_pll_enable;
 		encoder->disable_clock = intel_xe3plpd_pll_disable;
 		encoder->port_pll_type = intel_mtl_port_pll_type;
+		encoder->get_config = xe3plpd_ddi_get_config;
 	} else if (DISPLAY_VER(display) >= 14) {
 		encoder->enable_clock = intel_mtl_pll_enable;
 		encoder->disable_clock = intel_mtl_pll_disable;
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 0be4aad0efcc..11178cd00a5b 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1873,6 +1873,39 @@ intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
 	return true;
 }
 
+void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
+				       const struct intel_crtc_state *crtc_state,
+				       struct intel_lt_phy_pll_state *pll_state)
+{
+	u8 owned_lane_mask;
+	u8 lane;
+	intel_wakeref_t wakeref;
+	int i, j, k;
+
+	pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
+	if (pll_state->tbt_mode)
+		return;
+
+	owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
+	lane = owned_lane_mask & INTEL_LT_PHY_LANE0 ? : INTEL_LT_PHY_LANE1;
+	wakeref = intel_lt_phy_transaction_begin(encoder);
+
+	pll_state->config[0] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_0_CONFIG);
+	pll_state->config[1] = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG);
+	pll_state->config[2] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_2_CONFIG);
+
+	for (i = 0; i <= 12; i++) {
+		for (j = 3, k = 0; j >= 0; j--, k++)
+			pll_state->data[i][k] =
+				intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,
+						  LT_PHY_VDR_X_DATAY(i, j));
+	}
+
+	pll_state->clock =
+		intel_lt_phy_calc_port_clock(encoder, crtc_state);
+	intel_lt_phy_transaction_end(encoder, wakeref);
+}
+
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index e93e5becc316..dd8cbb151b23 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -28,6 +28,9 @@ void intel_lt_phy_dump_hw_state(struct intel_display *display,
 bool
 intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
 				  const struct intel_lt_phy_pll_state *b);
+void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
+				       const struct intel_crtc_state *crtc_state,
+				       struct intel_lt_phy_pll_state *pll_state);
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state);
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
-- 
2.34.1

Re: [PATCH 21/25] drm/i915/ltphy: Define function to readout LT Phy PLL state

[Murthy, Arun R]

On 15-10-2025 09:38, Suraj Kandpal wrote:
> Define a function to readout hw state for LT Phy PLL which
> can be used in get_config function call.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>   drivers/gpu/drm/i915/display/intel_ddi.c    | 14 +++++++++
>   drivers/gpu/drm/i915/display/intel_lt_phy.c | 33 +++++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_lt_phy.h |  3 ++
>   3 files changed, 50 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index b6345508cb66..e226ba8a4348 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4246,6 +4246,19 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
>   						     &crtc_state->dpll_hw_state);
>   }
>   
> +static void xe3plpd_ddi_get_config(struct intel_encoder *encoder,
> +				   struct intel_crtc_state *crtc_state)
> +{
> +	intel_lt_phy_pll_readout_hw_state(encoder, crtc_state, &crtc_state->dpll_hw_state.ltpll);
> +
> +	if (crtc_state->dpll_hw_state.ltpll.tbt_mode)
> +		crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
> +	else
> +		crtc_state->port_clock =
> +			intel_lt_phy_calc_port_clock(encoder, crtc_state);
> +	intel_ddi_get_config(encoder, crtc_state);
> +}
> +
>   static void mtl_ddi_get_config(struct intel_encoder *encoder,
>   			       struct intel_crtc_state *crtc_state)
>   {
> @@ -5234,6 +5247,7 @@ void intel_ddi_init(struct intel_display *display,
>   		encoder->enable_clock = intel_xe3plpd_pll_enable;
>   		encoder->disable_clock = intel_xe3plpd_pll_disable;
>   		encoder->port_pll_type = intel_mtl_port_pll_type;
> +		encoder->get_config = xe3plpd_ddi_get_config;
>   	} else if (DISPLAY_VER(display) >= 14) {
>   		encoder->enable_clock = intel_mtl_pll_enable;
>   		encoder->disable_clock = intel_mtl_pll_disable;
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 0be4aad0efcc..11178cd00a5b 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1873,6 +1873,39 @@ intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
>   	return true;
>   }
>   
> +void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
> +				       const struct intel_crtc_state *crtc_state,
> +				       struct intel_lt_phy_pll_state *pll_state)
> +{
> +	u8 owned_lane_mask;
> +	u8 lane;
> +	intel_wakeref_t wakeref;
> +	int i, j, k;
> +
> +	pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
> +	if (pll_state->tbt_mode)
> +		return;
> +
> +	owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
> +	lane = owned_lane_mask & INTEL_LT_PHY_LANE0 ? : INTEL_LT_PHY_LANE1;
> +	wakeref = intel_lt_phy_transaction_begin(encoder);
> +
> +	pll_state->config[0] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_0_CONFIG);
> +	pll_state->config[1] = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG);
> +	pll_state->config[2] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_2_CONFIG);
> +
> +	for (i = 0; i <= 12; i++) {
> +		for (j = 3, k = 0; j >= 0; j--, k++)
> +			pll_state->data[i][k] =
> +				intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,
> +						  LT_PHY_VDR_X_DATAY(i, j));
> +	}
> +
> +	pll_state->clock =
> +		intel_lt_phy_calc_port_clock(encoder, crtc_state);
> +	intel_lt_phy_transaction_end(encoder, wakeref);
> +}
> +
>   void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
>   			      const struct intel_crtc_state *crtc_state)
>   {
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index e93e5becc316..dd8cbb151b23 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -28,6 +28,9 @@ void intel_lt_phy_dump_hw_state(struct intel_display *display,
>   bool
>   intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
>   				  const struct intel_lt_phy_pll_state *b);
> +void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
> +				       const struct intel_crtc_state *crtc_state,
> +				       struct intel_lt_phy_pll_state *pll_state);
>   void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
>   			      const struct intel_crtc_state *crtc_state);
>   void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);

[PATCH 22/25] drm/i915/ltphy: Define LT PHY PLL state verify function

[Suraj Kandpal]

Define function to verify the LT PHY PLL state function and call it
in intel_modeset_verify_crtc.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 56 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |  4 ++
 .../drm/i915/display/intel_modeset_verify.c   |  2 +
 4 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 986da034d4de..fc6cdf026a34 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3580,7 +3580,7 @@ void intel_cx0pll_state_verify(struct intel_atomic_state *state,
 	struct intel_encoder *encoder;
 	struct intel_cx0pll_state mpll_hw_state = {};
 
-	if (DISPLAY_VER(display) < 14)
+	if (!IS_DISPLAY_VER(display, 14, 30))
 		return;
 
 	if (!new_crtc_state->hw.active)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 11178cd00a5b..72c3ba787e2a 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1906,6 +1906,61 @@ void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 	intel_lt_phy_transaction_end(encoder, wakeref);
 }
 
+void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
+				   struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(state);
+	struct intel_digital_port *dig_port;
+	const struct intel_crtc_state *new_crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	struct intel_encoder *encoder;
+	struct intel_lt_phy_pll_state pll_hw_state = {};
+	const struct intel_lt_phy_pll_state *pll_sw_state = &new_crtc_state->dpll_hw_state.ltpll;
+	int clock;
+	int i, j;
+
+	if (DISPLAY_VER(display) < 35)
+		return;
+
+	if (!new_crtc_state->hw.active)
+		return;
+
+	/* intel_get_crtc_new_encoder() only works for modeset/fastset commits */
+	if (!intel_crtc_needs_modeset(new_crtc_state) &&
+	    !intel_crtc_needs_fastset(new_crtc_state))
+		return;
+
+	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
+	intel_lt_phy_pll_readout_hw_state(encoder, new_crtc_state, &pll_hw_state);
+	clock = intel_lt_phy_calc_port_clock(encoder, new_crtc_state);
+
+	dig_port = enc_to_dig_port(encoder);
+	if (intel_tc_port_in_tbt_alt_mode(dig_port))
+		return;
+
+	INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.clock != clock,
+				 "[CRTC:%d:%s] mismatch in LT PHY: Register CLOCK (expected %d, found %d)",
+				 crtc->base.base.id, crtc->base.name,
+				 pll_sw_state->clock, pll_hw_state.clock);
+
+	for (i = 0; i < 3; i++) {
+		INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[i] != pll_sw_state->config[i],
+					 "[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG%d: (expected 0x%04x, found 0x%04x)",
+					 crtc->base.base.id, crtc->base.name, i,
+					 pll_sw_state->config[i], pll_hw_state.config[i]);
+	}
+
+	for (i = 0; i <= 12; i++) {
+		for (j = 3; j >= 0; j--)
+			INTEL_DISPLAY_STATE_WARN(display,
+						 pll_hw_state.data[i][j] !=
+						 pll_sw_state->data[i][j],
+						 "[CRTC:%d:%s] mismatch in LT PHY PLL DATA[%d][%d]: (expected 0x%04x, found 0x%04x)",
+						 crtc->base.base.id, crtc->base.name, i, j,
+						 pll_sw_state->data[i][j], pll_hw_state.data[i][j]);
+	}
+}
+
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state)
 {
@@ -1925,4 +1980,5 @@ void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
 		intel_mtl_tbt_pll_disable(encoder);
 	else
 		intel_lt_phy_pll_disable(encoder);
+
 }
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index dd8cbb151b23..a538d4c69210 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -8,9 +8,11 @@
 
 #include <linux/types.h>
 
+struct intel_atomic_state;
 struct intel_display;
 struct intel_encoder;
 struct intel_crtc_state;
+struct intel_crtc;
 struct intel_lt_phy_pll_state;
 
 void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
@@ -31,6 +33,8 @@ intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
 void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 				       const struct intel_crtc_state *crtc_state,
 				       struct intel_lt_phy_pll_state *pll_state);
+void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
+				   struct intel_crtc *crtc);
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state);
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index f2f6b9d9afa1..b361a77cd235 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -16,6 +16,7 @@
 #include "intel_display_core.h"
 #include "intel_display_types.h"
 #include "intel_fdi.h"
+#include "intel_lt_phy.h"
 #include "intel_modeset_verify.h"
 #include "intel_snps_phy.h"
 #include "skl_watermark.h"
@@ -246,6 +247,7 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state,
 	intel_dpll_state_verify(state, crtc);
 	intel_mpllb_state_verify(state, crtc);
 	intel_cx0pll_state_verify(state, crtc);
+	intel_lt_phy_pll_state_verify(state, crtc);
 }
 
 void intel_modeset_verify_disabled(struct intel_atomic_state *state)
-- 
2.34.1

Re: [PATCH 22/25] drm/i915/ltphy: Define LT PHY PLL state verify function

[Murthy, Arun R]

On 15-10-2025 09:38, Suraj Kandpal wrote:
> Define function to verify the LT PHY PLL state function and call it
> in intel_modeset_verify_crtc.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

>   drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  2 +-
>   drivers/gpu/drm/i915/display/intel_lt_phy.c   | 56 +++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_lt_phy.h   |  4 ++
>   .../drm/i915/display/intel_modeset_verify.c   |  2 +
>   4 files changed, 63 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 986da034d4de..fc6cdf026a34 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3580,7 +3580,7 @@ void intel_cx0pll_state_verify(struct intel_atomic_state *state,
>   	struct intel_encoder *encoder;
>   	struct intel_cx0pll_state mpll_hw_state = {};
>   
> -	if (DISPLAY_VER(display) < 14)
> +	if (!IS_DISPLAY_VER(display, 14, 30))
>   		return;
>   
>   	if (!new_crtc_state->hw.active)
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 11178cd00a5b..72c3ba787e2a 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1906,6 +1906,61 @@ void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
>   	intel_lt_phy_transaction_end(encoder, wakeref);
>   }
>   
> +void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
> +				   struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(state);
> +	struct intel_digital_port *dig_port;
> +	const struct intel_crtc_state *new_crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	struct intel_encoder *encoder;
> +	struct intel_lt_phy_pll_state pll_hw_state = {};
> +	const struct intel_lt_phy_pll_state *pll_sw_state = &new_crtc_state->dpll_hw_state.ltpll;
> +	int clock;
> +	int i, j;
> +
> +	if (DISPLAY_VER(display) < 35)
> +		return;
> +
> +	if (!new_crtc_state->hw.active)
> +		return;
> +
> +	/* intel_get_crtc_new_encoder() only works for modeset/fastset commits */
> +	if (!intel_crtc_needs_modeset(new_crtc_state) &&
> +	    !intel_crtc_needs_fastset(new_crtc_state))
> +		return;
> +
> +	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
> +	intel_lt_phy_pll_readout_hw_state(encoder, new_crtc_state, &pll_hw_state);
> +	clock = intel_lt_phy_calc_port_clock(encoder, new_crtc_state);
> +
> +	dig_port = enc_to_dig_port(encoder);
> +	if (intel_tc_port_in_tbt_alt_mode(dig_port))
> +		return;
> +
> +	INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.clock != clock,
> +				 "[CRTC:%d:%s] mismatch in LT PHY: Register CLOCK (expected %d, found %d)",
> +				 crtc->base.base.id, crtc->base.name,
> +				 pll_sw_state->clock, pll_hw_state.clock);
> +
> +	for (i = 0; i < 3; i++) {
> +		INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[i] != pll_sw_state->config[i],
> +					 "[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG%d: (expected 0x%04x, found 0x%04x)",
> +					 crtc->base.base.id, crtc->base.name, i,
> +					 pll_sw_state->config[i], pll_hw_state.config[i]);
> +	}
> +
> +	for (i = 0; i <= 12; i++) {
> +		for (j = 3; j >= 0; j--)
> +			INTEL_DISPLAY_STATE_WARN(display,
> +						 pll_hw_state.data[i][j] !=
> +						 pll_sw_state->data[i][j],
> +						 "[CRTC:%d:%s] mismatch in LT PHY PLL DATA[%d][%d]: (expected 0x%04x, found 0x%04x)",
> +						 crtc->base.base.id, crtc->base.name, i, j,
> +						 pll_sw_state->data[i][j], pll_hw_state.data[i][j]);
> +	}
> +}
> +
>   void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
>   			      const struct intel_crtc_state *crtc_state)
>   {
> @@ -1925,4 +1980,5 @@ void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
>   		intel_mtl_tbt_pll_disable(encoder);
>   	else
>   		intel_lt_phy_pll_disable(encoder);
> +
>   }
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index dd8cbb151b23..a538d4c69210 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -8,9 +8,11 @@
>   
>   #include <linux/types.h>
>   
> +struct intel_atomic_state;
>   struct intel_display;
>   struct intel_encoder;
>   struct intel_crtc_state;
> +struct intel_crtc;
>   struct intel_lt_phy_pll_state;
>   
>   void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> @@ -31,6 +33,8 @@ intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
>   void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
>   				       const struct intel_crtc_state *crtc_state,
>   				       struct intel_lt_phy_pll_state *pll_state);
> +void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
> +				   struct intel_crtc *crtc);
>   void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
>   			      const struct intel_crtc_state *crtc_state);
>   void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> index f2f6b9d9afa1..b361a77cd235 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> @@ -16,6 +16,7 @@
>   #include "intel_display_core.h"
>   #include "intel_display_types.h"
>   #include "intel_fdi.h"
> +#include "intel_lt_phy.h"
>   #include "intel_modeset_verify.h"
>   #include "intel_snps_phy.h"
>   #include "skl_watermark.h"
> @@ -246,6 +247,7 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state,
>   	intel_dpll_state_verify(state, crtc);
>   	intel_mpllb_state_verify(state, crtc);
>   	intel_cx0pll_state_verify(state, crtc);
> +	intel_lt_phy_pll_state_verify(state, crtc);
>   }
>   
>   void intel_modeset_verify_disabled(struct intel_atomic_state *state)

[PATCH 23/25] drm/i915/display: Aux Enable and Display powerwell timeouts

[Suraj Kandpal]

From XE3P we can now poll if the AUX power is up or down define the
timeouts for each respectively.

Bspec: 68967
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../i915/display/intel_display_power_well.c   | 23 +++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 5e88b930f5aa..1fc2e9450f03 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1864,18 +1864,37 @@ static void xelpdp_aux_power_well_enable(struct intel_display *display,
 	 * expected to just wait a fixed 600us after raising the request
 	 * bit.
 	 */
-	usleep_range(600, 1200);
+
+	if (DISPLAY_VER(display) >= 35) {
+		if (intel_de_wait_for_set(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
+					  XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 2))
+			drm_warn(display->drm,
+				 "Timeout waiting for PHY %c AUX channel power to be up\n",
+				 phy_name(phy));
+	} else {
+		usleep_range(600, 1200);
+	}
 }
 
 static void xelpdp_aux_power_well_disable(struct intel_display *display,
 					  struct i915_power_well *power_well)
 {
 	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
+	enum phy phy = icl_aux_pw_to_phy(display, power_well);
 
 	intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
 		     0);
-	usleep_range(10, 30);
+
+	if (DISPLAY_VER(display) >= 35) {
+		if (intel_de_wait_for_clear(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
+					    XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1))
+			drm_warn(display->drm,
+				 "Timeout waiting for PHY %c AUX channel to powerdown\n",
+				 phy_name(phy));
+	} else {
+		usleep_range(10, 30);
+	}
 }
 
 static bool xelpdp_aux_power_well_enabled(struct intel_display *display,
-- 
2.34.1

Re: [PATCH 23/25] drm/i915/display: Aux Enable and Display powerwell timeouts

[Murthy, Arun R]

On 15-10-2025 09:38, Suraj Kandpal wrote:
>  From XE3P we can now poll if the AUX power is up or down define the
> timeouts for each respectively.
>
> Bspec: 68967
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>   .../i915/display/intel_display_power_well.c   | 23 +++++++++++++++++--
>   1 file changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 5e88b930f5aa..1fc2e9450f03 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1864,18 +1864,37 @@ static void xelpdp_aux_power_well_enable(struct intel_display *display,
>   	 * expected to just wait a fixed 600us after raising the request
>   	 * bit.
>   	 */
> -	usleep_range(600, 1200);
> +

Un-necessary blank line and place the comment properly!

Thanks and Regards,
Arun R Murthy
-------------------

> +	if (DISPLAY_VER(display) >= 35) {
> +		if (intel_de_wait_for_set(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
> +					  XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 2))
> +			drm_warn(display->drm,
> +				 "Timeout waiting for PHY %c AUX channel power to be up\n",
> +				 phy_name(phy));
> +	} else {
> +		usleep_range(600, 1200);
> +	}
>   }
>   
>   static void xelpdp_aux_power_well_disable(struct intel_display *display,
>   					  struct i915_power_well *power_well)
>   {
>   	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
> +	enum phy phy = icl_aux_pw_to_phy(display, power_well);
>   
>   	intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
>   		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
>   		     0);
> -	usleep_range(10, 30);
> +
> +	if (DISPLAY_VER(display) >= 35) {
> +		if (intel_de_wait_for_clear(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
> +					    XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1))
> +			drm_warn(display->drm,
> +				 "Timeout waiting for PHY %c AUX channel to powerdown\n",
> +				 phy_name(phy));
> +	} else {
> +		usleep_range(10, 30);
> +	}
>   }
>   
>   static bool xelpdp_aux_power_well_enabled(struct intel_display *display,

[PATCH 24/25] drm/i915/ltphy: Modify the step that need to by skipped

[Suraj Kandpal]

Bspec has changed the non tbt pll enable sequence now we skip
steps 5-17 if no config change has occurred.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 63 +++++++++++----------
 1 file changed, 33 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 72c3ba787e2a..0262c3a97020 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1664,40 +1664,43 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 					 XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
 			drm_warn(display->drm, "PHY %c PLL MacCLK Ack assertion Timeout after %dus.\n",
 				 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
+
+		/*
+		 * 13. Ungate the forward clock by setting
+		 * PORT_CLOCK_CTL[Forward Clock Ungate] = 1.
+		 */
+		intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
+			     XELPDP_FORWARD_CLOCK_UNGATE,
+			     XELPDP_FORWARD_CLOCK_UNGATE);
+
+		/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
+		intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
+			     lane_phy_pulse_status,
+			     lane_phy_pulse_status);
+		/*
+		 * 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over
+		 * PHY message bus for Owned PHY Lanes.
+		 */
+		rate_update = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_RATE_UPDATE);
+		rate_update &= ~LT_PHY_RATE_CONTROL_VDR_UPDATE;
+		intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_RATE_UPDATE,
+				   rate_update, MB_WRITE_COMMITTED);
+
+		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
+		if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
+					 lane_phy_pulse_status, lane_phy_pulse_status,
+					 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
+			drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
+				 phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
+
+		/* 17. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
+		intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
+			     lane_phy_pulse_status,
+			     lane_phy_pulse_status);
 	} else {
 		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), crtc_state->port_clock);
 	}
 
-	/* 13. Ungate the forward clock by setting PORT_CLOCK_CTL[Forward Clock Ungate] = 1. */
-	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
-		     XELPDP_FORWARD_CLOCK_UNGATE,
-		     XELPDP_FORWARD_CLOCK_UNGATE);
-
-	/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
-	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
-		     lane_phy_pulse_status,
-		     lane_phy_pulse_status);
-	/*
-	 * 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over PHY message bus for
-	 * Owned PHY Lanes.
-	 */
-	rate_update = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_RATE_UPDATE);
-	rate_update &= ~LT_PHY_RATE_CONTROL_VDR_UPDATE;
-	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_RATE_UPDATE,
-			   rate_update, MB_WRITE_COMMITTED);
-
-	/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
-	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
-				 lane_phy_pulse_status, lane_phy_pulse_status,
-				 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
-		drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
-			 phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
-
-	/* 17. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
-	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
-		     lane_phy_pulse_status,
-		     lane_phy_pulse_status);
-
 	/*
 	 * 18. Follow the Display Voltage Frequency Switching - Sequence After Frequency Change.
 	 * We handle this step in bxt_set_cdclk()
-- 
2.34.1

Re: [PATCH 24/25] drm/i915/ltphy: Modify the step that need to by skipped

[Murthy, Arun R]

On 15-10-2025 09:38, Suraj Kandpal wrote:
> Bspec has changed the non tbt pll enable sequence now we skip
> steps 5-17 if no config change has occurred.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>   drivers/gpu/drm/i915/display/intel_lt_phy.c | 63 +++++++++++----------
>   1 file changed, 33 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 72c3ba787e2a..0262c3a97020 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1664,40 +1664,43 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>   					 XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
>   			drm_warn(display->drm, "PHY %c PLL MacCLK Ack assertion Timeout after %dus.\n",
>   				 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
> +
> +		/*
> +		 * 13. Ungate the forward clock by setting
> +		 * PORT_CLOCK_CTL[Forward Clock Ungate] = 1.
> +		 */
> +		intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> +			     XELPDP_FORWARD_CLOCK_UNGATE,
> +			     XELPDP_FORWARD_CLOCK_UNGATE);
> +
> +		/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
> +		intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> +			     lane_phy_pulse_status,
> +			     lane_phy_pulse_status);
> +		/*
> +		 * 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over
> +		 * PHY message bus for Owned PHY Lanes.
> +		 */
> +		rate_update = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_RATE_UPDATE);
> +		rate_update &= ~LT_PHY_RATE_CONTROL_VDR_UPDATE;
> +		intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_RATE_UPDATE,
> +				   rate_update, MB_WRITE_COMMITTED);
> +
> +		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
> +		if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
> +					 lane_phy_pulse_status, lane_phy_pulse_status,
> +					 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
> +			drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
> +				 phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
> +
> +		/* 17. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
> +		intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> +			     lane_phy_pulse_status,
> +			     lane_phy_pulse_status);
>   	} else {
>   		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), crtc_state->port_clock);
>   	}
>   
> -	/* 13. Ungate the forward clock by setting PORT_CLOCK_CTL[Forward Clock Ungate] = 1. */
> -	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> -		     XELPDP_FORWARD_CLOCK_UNGATE,
> -		     XELPDP_FORWARD_CLOCK_UNGATE);
> -
> -	/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
> -	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> -		     lane_phy_pulse_status,
> -		     lane_phy_pulse_status);
> -	/*
> -	 * 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over PHY message bus for
> -	 * Owned PHY Lanes.
> -	 */
> -	rate_update = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_RATE_UPDATE);
> -	rate_update &= ~LT_PHY_RATE_CONTROL_VDR_UPDATE;
> -	intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_RATE_UPDATE,
> -			   rate_update, MB_WRITE_COMMITTED);
> -
> -	/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
> -	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
> -				 lane_phy_pulse_status, lane_phy_pulse_status,
> -				 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
> -		drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
> -			 phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
> -
> -	/* 17. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
> -	intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> -		     lane_phy_pulse_status,
> -		     lane_phy_pulse_status);
> -
>   	/*
>   	 * 18. Follow the Display Voltage Frequency Switching - Sequence After Frequency Change.
>   	 * We handle this step in bxt_set_cdclk()

[PATCH 25/25] drm/i915/ltphy: Implement HDMI Algo for Pll state

[Suraj Kandpal]

Implement the HDMI Algorithm to dynamically create LT PHY state
based on the port clock provided.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 318 +++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_lt_phy.h |   3 +
 2 files changed, 320 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 0262c3a97020..adc119cfd1fa 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1355,6 +1355,318 @@ intel_lt_phy_pll_is_ssc_enabled(struct intel_crtc_state *crtc_state,
 	return false;
 }
 
+void
+intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
+				  u32 frequency_khz)
+{
+#define DATA_ASSIGN(i, val)	\
+	do {			\
+		lt_state->data[i][0] = (u8)(((val) & 0xFF000000) >> 24); \
+		lt_state->data[i][1] = (u8)(((val) & 0x00FF0000) >> 16); \
+		lt_state->data[i][2] = (u8)(((val) & 0x0000FF00) >> 8); \
+		lt_state->data[i][3] = (u8)(((val) & 0x000000FF));	\
+	} while (0)
+#define MULQ32_U32(x, y)	\
+	(((u64)((x) >> 32) * (y) << 32) + (u64)((x) & 0xFFFFFFFF) * (y))
+#define Q32_TO_INT(x)	((x) >> 32)
+#define Q32_TO_FRAC(x)	((x) & 0xFFFFFFFF)
+	bool found = false;
+	u32 ppm_value = 1;
+	u32 dco_min_freq = 11850;
+	u32 dco_max_freq = 16200;
+	u32 dco_min_freq_low = 10000;
+	u32 dco_max_freq_low = 12000;
+	u32 dcofmin = dco_min_freq;
+	u64 val = 0;
+	u64 refclk_khz = 38400;
+	u64 m2div = 0;
+	u64 val_with_frac = 0;
+	u64 ppm = 0;
+	u64 target_dco_mhz = 0;
+	u64 tdc_fine;
+	u64 iref_ndiv;
+	u64 tdc_targetcnt;
+	u64 feedfwdgain;
+	u64 feedfwd_cal_en;
+	u64 tdc_res = 30;
+	u32 prop_coeff;
+	u32 int_coeff;
+	u32 ndiv = 1;
+	u32 m1div = 1;
+	u32 m2div_int;
+	u32 m2div_frac;
+	u32 frac_en;
+	u32 settlingtime = 0;
+	u32 ana_cfg;
+	u32 loop_cnt = 0;
+	u32 dcofine0_tune_2_0 = 0;
+	u32 dcofine1_tune_2_0 = 0;
+	u32 dcofine2_tune_2_0 = 0;
+	u32 dcofine3_tune_2_0 = 0;
+	u32 dcodith0_tune_2_0 = 0;
+	u32 dcodith1_tune_2_0 = 0;
+	u32 gain_ctrl = 2;
+	u32 refclk_mhz_int = 38;
+	u32 pll_reg4 = (refclk_mhz_int << 17) +
+		(ndiv << 9) + (1 << 4);
+	u32 pll_bias2_addr = 0;
+	u32 pll_biastrim_addr = 0;
+	u32 pll_dco_med_addr = 0;
+	u32 pll_dcofine_addr = 0;
+	u32 pll_sscinj_addr = 0;
+	u32 pll_surv_bonus_addr = 0;
+	u32 pll_lf_addr = 0;
+	u32 pll_reg3_addr = 0;
+	u32 pll_reg4_addr = 0;
+	u32 pll_reg57_addr = 0;
+	u32 pll_reg5_addr = 0;
+	u32 pll_ssc_addr = 0;
+	u32 pll_tdc_addr = 0;
+	u32 pll_reg3 = 0;
+	u32 pll_reg5 = 0;
+	u32 postdiv = 0;
+	u32 d6_new = 0;
+	u32 pll_reg57 = 0;
+	u32 dco12g = 0;
+	u32 pll_type = 0;
+	u32 d1 = 2;
+	u32 d3 = 5;
+	u32 d5 = 0;
+	u32 d6 = 0;
+	u32 d7;
+	u32 d8 = 0;
+	u32 d4 = 0;
+	u32 lf = 0;
+	int ssc_stepsize = 0;
+	int ssc_steplen = 0;
+	int ssc_steplog = 0;
+	u32 ssc = 0;
+	u32 lockthr = 0;
+	u32 unlockthr = 0;
+	u32 earlylock = 1;
+	u32 truelock = 2;
+	u32 lockovr_en = 1;
+	u32 biasovr_en = 1;
+	u32 coldstart = 1;
+	u32 ssc_en_local = 0;
+	u64 dynctrl_ovrd_en = 0;
+	u32 bias2 = 0;
+	u32 tdc = 0;
+	u32 cselmedthr = 8;
+	u32 cselmedratio = 39;
+	u32 cselmed_dynadj = 0;
+	u32 cselmed_en = 0;
+	u32 dco_med = 0;
+	u32 bonus_7_0 = 0;
+	u32 surv_bonus = (bonus_7_0 << 16);
+	u32 csel2fo = 11;
+	u32 csel2fo_ovrd_en = 1;
+	u32 biastrim = (csel2fo_ovrd_en << 30) + (csel2fo << 24);
+	u32 dcofine = 0;
+	int ppm_cnt, dcocount, y;
+	u64 refclk_mhz = div64_u64(refclk_khz, 1000);
+	u64 frequency_mhz = div64_u64(frequency_khz, 1000);
+	u64 temp0, temp1, temp2, temp3, scale;
+
+	settlingtime = 15;
+	for (ppm_cnt = 0; ppm_cnt < 5; ppm_cnt++) {
+		switch (ppm_cnt) {
+		case 0:
+			ppm_value = 1;
+			break;
+		case 1:
+			ppm_value = 1;
+			break;
+		case 2:
+			ppm_value = 2;
+			break;
+		default:
+			ppm_value = 1;
+			break;
+		}
+
+		for (dcocount = 0; dcocount < 2; dcocount++) {
+			if (dcocount == 1) {
+				dco_min_freq = dco_min_freq_low;
+				dco_max_freq = dco_max_freq_low;
+			}
+			for (y = 2; y <= 255; y += 2) {
+				val = ((u64)y * frequency_mhz * 5);
+				m2div = div64_u64(((val) << 32), 2 * refclk_mhz);
+				val_with_frac = MULQ32_U32(m2div, refclk_mhz * 2);
+				temp1 = Q32_TO_INT(val_with_frac);
+				temp0 = (temp1 > val) ? (temp1 - val) :
+					(val - temp1);
+				ppm = div64_u64(temp0, val);
+				if (temp1 >= dco_min_freq &&
+				    temp1 <= dco_max_freq &&
+				    ppm < ppm_value) {
+					/* Round to two places */
+					scale = (1ULL << 32) / 100;
+					temp0 = DIV_ROUND_CLOSEST_ULL(val_with_frac,
+								      scale);
+					target_dco_mhz = temp0 * scale;
+					loop_cnt = y;
+					found = true;
+					break;
+				}
+			}
+			if (found)
+				break;
+		}
+		if (found)
+			break;
+	}
+
+	if (!found)
+		return;
+
+	m2div = div64_u64(target_dco_mhz, (refclk_mhz * ndiv * m1div));
+	if (Q32_TO_INT(m2div) > 511)
+		return;
+
+	m2div_int = (u32)Q32_TO_INT(m2div);
+	m2div_frac = (u32)(Q32_TO_FRAC(m2div));
+	frac_en = (m2div_frac > 0) ? 1 : 0;
+
+	if (frac_en > 0)
+		tdc_res = 70;
+	else
+		tdc_res = 36;
+	tdc_fine = tdc_res > 50 ? 1 : 0;
+	iref_ndiv = (refclk_khz > 80000) ? 4 : (refclk_khz > 38000) ? 2 : 1;
+	temp0 = tdc_res * 40 * 11;
+	temp1 = div64_u64((40000000ULL + temp0),  2 * temp0 * refclk_mhz);
+	temp2 = temp0 * refclk_mhz;
+	temp3 = div64_u64((80000000ULL + temp2), temp2);
+	tdc_targetcnt = tdc_res < 50 ? (int)(temp1) : (int)(temp3);
+	tdc_targetcnt = (refclk_khz < 25000) ? (int)(tdc_targetcnt / 4) :
+			(refclk_khz < 50000) ? (int)(tdc_targetcnt / 2) :
+			tdc_targetcnt;
+	temp0 = MULQ32_U32(target_dco_mhz, tdc_res);
+	temp0 >>= 32;
+	feedfwdgain = (m2div_frac > 0) ? div64_u64(m1div * 10000000ULL, temp0) : 0;
+	feedfwd_cal_en = frac_en;
+	settlingtime = (u32)div64_u64(refclk_khz, iref_ndiv * 1000);
+
+	temp0 = (u32)Q32_TO_INT(target_dco_mhz);
+	prop_coeff = (temp0 >= dcofmin) ? 3 : 4;
+	int_coeff = (temp0 >= dcofmin) ? 7 : 8;
+	ana_cfg = (temp0 >= dcofmin) ? 8 : 6;
+	dco12g = (temp0 >= dcofmin) ? 0 : 1;
+
+	if (temp0 > 12960)
+		d7 = 10;
+	else
+		d7 = 8;
+
+	d8 = loop_cnt / 2;
+	d4 = d8 * 2;
+
+	/* Compute pll_reg3,5,57 & lf */
+	pll_reg3 = (u32)((d4 << 21) + (d3 << 18) + (d1 << 15) + (m2div_int << 5));
+	pll_reg5 = m2div_frac;
+	postdiv = (d5 == 0) ? 9 : d5;
+	d6_new = (d6 == 0) ? 40 : d6;
+	pll_reg57 = (d7 << 24) + (postdiv << 15) + (d8 << 7) + d6_new;
+	lf = (u32)((frac_en << 31) + (1 << 30) + (frac_en << 29) +
+		   (feedfwd_cal_en << 28) + (tdc_fine << 27) +
+		   (gain_ctrl << 24) + (feedfwdgain << 16) +
+		   (int_coeff << 12) + (prop_coeff << 8) + tdc_targetcnt);
+
+	/* Compute ssc / bias2 */
+	ssc = (1 << 31) + (ana_cfg << 24) + (ssc_steplog << 16) +
+		(ssc_stepsize << 8) + ssc_steplen;
+	bias2 = (u32)((dynctrl_ovrd_en << 31) + (ssc_en_local << 30) +
+		      (1 << 23) + (1 << 24) + (32 << 16) + (1 << 8));
+
+	lockthr = tdc_fine ? 3 : 5;
+	unlockthr = tdc_fine ? 5 : 11;
+	settlingtime = 15;
+
+	/* Compute tdc/dco_med */
+	tdc = (u32)((2 << 30) + (settlingtime << 16) + (biasovr_en << 15) +
+		    (lockovr_en << 14) + (coldstart << 12) + (truelock << 10) +
+		    (earlylock << 8) + (unlockthr << 4) + lockthr);
+
+	dco_med = (cselmed_en << 31) + (cselmed_dynadj << 30) +
+		(cselmedratio << 24) + (cselmedthr << 21);
+
+	/* Compute dcofine */
+	dcofine0_tune_2_0 = dco12g ? 4 : 3;
+	dcofine1_tune_2_0 = dco12g ? 2 : 2;
+	dcofine2_tune_2_0 = dco12g ? 2 : 1;
+	dcofine3_tune_2_0 = dco12g ? 5 : 5;
+	dcodith0_tune_2_0 = dco12g ? 4 : 3;
+	dcodith1_tune_2_0 = dco12g ? 2 : 2;
+
+	dcofine = (dcodith1_tune_2_0 << 19)
+		+ (dcodith0_tune_2_0 << 16)
+		+ (dcofine3_tune_2_0 << 11)
+		+ (dcofine2_tune_2_0 << 8)
+		+ (dcofine1_tune_2_0 << 3)
+		+ dcofine0_tune_2_0;
+
+	pll_type = ((frequency_khz == 10000) || (frequency_khz == 20000) ||
+		    (frequency_khz == 2500) || (dco12g == 1)) ? 0 : 1;
+
+	pll_reg4_addr = pll_type ? 34576 : 34064;
+	pll_reg3_addr = pll_type ? 34572 : 34060;
+	pll_reg5_addr = pll_type ? 34580 : 34068;
+	pll_reg57_addr = pll_type ? 34788 : 34276;
+	pll_lf_addr = pll_type ? 34828 : 34316;
+	pll_tdc_addr = pll_type ? 34832 : 34320;
+	pll_ssc_addr = pll_type ? 34836 : 34324;
+	pll_bias2_addr = pll_type ? 34840 : 34328;
+	pll_biastrim_addr = pll_type ? 34888 : 34376;
+	pll_dco_med_addr = pll_type ? 34880 : 34368;
+	pll_dcofine_addr = pll_type ? 34892 : 34380;
+	pll_sscinj_addr = pll_type ? 34852 : 34340;
+	pll_surv_bonus_addr = pll_type ? 34884 : 34372;
+
+	lt_state->config[0] = 0x84;
+	lt_state->config[1] = 0x2d;
+	lt_state->addr_msb[0] = (pll_reg4_addr >> 8) & 0xFF;
+	lt_state->addr_lsb[0] = pll_reg4_addr & 0xFF;
+	lt_state->addr_msb[1] = (pll_reg3_addr >> 8) & 0xFF;
+	lt_state->addr_lsb[1] = pll_reg3_addr & 0xFF;
+	lt_state->addr_msb[2] = (pll_reg5_addr >> 8) & 0xFF;
+	lt_state->addr_lsb[2] = pll_reg5_addr & 0xFF;
+	lt_state->addr_msb[3] = (pll_reg57_addr >> 8) & 0xFF;
+	lt_state->addr_lsb[3] = pll_reg57_addr & 0xFF;
+	lt_state->addr_msb[4] = (pll_lf_addr >> 8) & 0xFF;
+	lt_state->addr_lsb[4] = pll_lf_addr & 0xFF;
+	lt_state->addr_msb[5] = (pll_tdc_addr >> 8) & 0xFF;
+	lt_state->addr_lsb[5] = pll_tdc_addr & 0xFF;
+	lt_state->addr_msb[6] = (pll_ssc_addr >> 8) & 0xFF;
+	lt_state->addr_lsb[6] = pll_ssc_addr & 0xFF;
+	lt_state->addr_msb[7] = (pll_bias2_addr >> 8) & 0xFF;
+	lt_state->addr_lsb[7] = pll_bias2_addr & 0xFF;
+	lt_state->addr_msb[8] = (pll_biastrim_addr >> 8) & 0xFF;
+	lt_state->addr_lsb[8] = pll_biastrim_addr & 0xFF;
+	lt_state->addr_msb[9] = (pll_dco_med_addr >> 8) & 0xFF;
+	lt_state->addr_lsb[9] = pll_dco_med_addr & 0xFF;
+	lt_state->addr_msb[10] = (pll_dcofine_addr >> 8) & 0xFF;
+	lt_state->addr_lsb[10] = pll_dcofine_addr & 0xFF;
+	lt_state->addr_msb[11] = (pll_sscinj_addr >> 8) & 0xFF;
+	lt_state->addr_lsb[11] = pll_sscinj_addr & 0xFF;
+	lt_state->addr_msb[12] = (pll_surv_bonus_addr >> 8) & 0xFF;
+	lt_state->addr_lsb[12] = pll_surv_bonus_addr & 0xFF;
+	DATA_ASSIGN(0, pll_reg4);
+	DATA_ASSIGN(1, pll_reg3);
+	DATA_ASSIGN(2, pll_reg5);
+	DATA_ASSIGN(3, pll_reg57);
+	DATA_ASSIGN(4, lf);
+	DATA_ASSIGN(5, tdc);
+	DATA_ASSIGN(6, ssc);
+	DATA_ASSIGN(7, bias2);
+	DATA_ASSIGN(8, biastrim);
+	DATA_ASSIGN(9, dco_med);
+	DATA_ASSIGN(10, dcofine);
+	DATA_ASSIGN(11, 0);
+	DATA_ASSIGN(12, surv_bonus);
+}
+
 static int
 intel_lt_phy_calc_hdmi_port_clock(const struct intel_lt_phy_pll_state *lt_state)
 {
@@ -1459,7 +1771,11 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 		}
 	}
 
-	/* TODO: Add a function to compute the data for HDMI TMDS*/
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+		intel_lt_phy_calculate_hdmi_state(&crtc_state->dpll_hw_state.ltpll,
+						  crtc_state->port_clock);
+		return 0;
+	}
 
 	return -EINVAL;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index a538d4c69210..1693e9f2bc6c 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -35,6 +35,9 @@ void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
 				       struct intel_lt_phy_pll_state *pll_state);
 void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
 				   struct intel_crtc *crtc);
+void
+intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
+				  u32 frequency_khz);
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state);
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
-- 
2.34.1

✗ CI.checkpatch: warning for Enable LT PHY

[Patchwork]

== Series Details ==

Series: Enable LT PHY
URL   : https://patchwork.freedesktop.org/series/155954/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
fbd08a78c3a3bb17964db2a326514c69c1dca660
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 538b63b073a20c64edcf306d7619eb74f96ee571
Author: Suraj Kandpal <suraj.kandpal@intel.com>
Date:   Wed Oct 15 09:38:17 2025 +0530

    drm/i915/ltphy: Implement HDMI Algo for Pll state
    
    Implement the HDMI Algorithm to dynamically create LT PHY state
    based on the port clock provided.
    
    Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
+ /mt/dim checkpatch c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb drm-intel
b42665161ef4 drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers
-:12: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#12: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 27 lines checked
ca5a3eed9faa drm/i915/cx0: Change register bit naming for powerdown values
141cad4df386 drm/i915/ltphy: Phy lane reset for LT Phy
-:82: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#82: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 255 lines checked
32e341bc8c17 drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT Phy
fa6aa8e026e6 drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence
586ae5f3eebd drm/i915/ltphy: Read PHY_VDR_0_CONFIG register
e5a4a562ff43 drm/i915/ltphy: Add LT Phy Programming recipe tables
abf863cf8ab9 drm/i915/ltphy: Program the VDR PLL registers for LT PHY
4e20c036f784 drm/i915/ltphy: Update the ltpll config table value for eDP
5101d1f6ab2c drm/i915/ltphy: Enable SSC during port clock programming
2ba7aed6e698 drm/i915/ltphy: Add function to calculate LT PHY port clock
-:40: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i' - possible side-effects?
#40: FILE: drivers/gpu/drm/i915/display/intel_lt_phy.c:1244:
+#define REGVAL(i) (				\
+	(lt_state->data[i][3])		|	\
+	(lt_state->data[i][2] << 8)	|	\
+	(lt_state->data[i][1] << 16)	|	\
+	(lt_state->data[i][0] << 24)		\
+)

total: 0 errors, 0 warnings, 1 checks, 109 lines checked
d85f6c05355f drm/i915/ltphy: Program the P2P Transaction flow for LT Phy
-:91: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__lane' - possible side-effects?
#91: FILE: drivers/gpu/drm/i915/display/intel_lt_phy.c:22:
+#define for_each_lt_phy_lane_in_mask(__lane_mask, __lane) \
+	for ((__lane) = 0; (__lane) < 2; (__lane)++) \
+		for_each_if((__lane_mask) & BIT(__lane))

-:167: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see function description of usleep_range() and udelay().
#167: FILE: drivers/gpu/drm/i915/display/intel_lt_phy.c:1071:
+	udelay(150);

-:258: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#258: FILE: drivers/gpu/drm/i915/display/intel_lt_phy_regs.h:51:
+										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \

-:259: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#259: FILE: drivers/gpu/drm/i915/display/intel_lt_phy_regs.h:52:
+										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \

-:260: WARNING:LONG_LINE: line length of 121 exceeds 100 columns
#260: FILE: drivers/gpu/drm/i915/display/intel_lt_phy_regs.h:53:
+										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \

-:261: WARNING:LONG_LINE: line length of 121 exceeds 100 columns
#261: FILE: drivers/gpu/drm/i915/display/intel_lt_phy_regs.h:54:
+										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) \

-:262: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#262: FILE: drivers/gpu/drm/i915/display/intel_lt_phy_regs.h:55:
+										 + 0x60 + (lane) * 0x4)

-:263: WARNING:LONG_LINE: line length of 119 exceeds 100 columns
#263: FILE: drivers/gpu/drm/i915/display/intel_lt_phy_regs.h:56:
+#define XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(port, lane)	 _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(__xe2lpd_port_idx(port), \

total: 0 errors, 6 warnings, 2 checks, 222 lines checked
467948560db9 drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL steps
10605e3e945e drm/i915/ltphy: Program the rest of the LT Phy Enable sequence
72d440c3f1e0 drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequence
6c75c1fc9141 drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences
0000b57e505a drm/i915/ddi: Define LT Phy Swing tables
dfbbd574527f drm/i915/ltphy: Program LT Phy Voltage Swing
83cc06c167b2 drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence
e21ffd93b8e4 drm/i915/ltphy: Define the LT Phy state compare function
-:52: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#52: FILE: drivers/gpu/drm/i915/display/intel_display.c:5109:
+#define PIPE_CONF_CHECK_PLL_LT(name) do { \
+	if (!intel_lt_phy_pll_compare_hw_state(&current_config->name, \
+					       &pipe_config->name)) { \
+		pipe_config_lt_phy_pll_mismatch(&p, fastset, crtc, __stringify(name), \
+						&current_config->name, \
+						&pipe_config->name); \
+		ret = false; \
+	} \
+} while (0)

-:52: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues
#52: FILE: drivers/gpu/drm/i915/display/intel_display.c:5109:
+#define PIPE_CONF_CHECK_PLL_LT(name) do { \
+	if (!intel_lt_phy_pll_compare_hw_state(&current_config->name, \
+					       &pipe_config->name)) { \
+		pipe_config_lt_phy_pll_mismatch(&p, fastset, crtc, __stringify(name), \
+						&current_config->name, \
+						&pipe_config->name); \
+		ret = false; \
+	} \
+} while (0)

total: 0 errors, 0 warnings, 2 checks, 111 lines checked
56140e7f1b08 drm/i915/ltphy: Define function to readout LT Phy PLL state
bf377842dc72 drm/i915/ltphy: Define LT PHY PLL state verify function
027b7b82ae30 drm/i915/display: Aux Enable and Display powerwell timeouts
dd038b2eaf40 drm/i915/ltphy: Modify the step that need to by skipped
538b63b073a2 drm/i915/ltphy: Implement HDMI Algo for Pll state
-:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i' - possible side-effects?
#23: FILE: drivers/gpu/drm/i915/display/intel_lt_phy.c:1362:
+#define DATA_ASSIGN(i, val)	\
+	do {			\
+		lt_state->data[i][0] = (u8)(((val) & 0xFF000000) >> 24); \
+		lt_state->data[i][1] = (u8)(((val) & 0x00FF0000) >> 16); \
+		lt_state->data[i][2] = (u8)(((val) & 0x0000FF00) >> 8); \
+		lt_state->data[i][3] = (u8)(((val) & 0x000000FF));	\
+	} while (0)

-:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'val' - possible side-effects?
#23: FILE: drivers/gpu/drm/i915/display/intel_lt_phy.c:1362:
+#define DATA_ASSIGN(i, val)	\
+	do {			\
+		lt_state->data[i][0] = (u8)(((val) & 0xFF000000) >> 24); \
+		lt_state->data[i][1] = (u8)(((val) & 0x00FF0000) >> 16); \
+		lt_state->data[i][2] = (u8)(((val) & 0x0000FF00) >> 8); \
+		lt_state->data[i][3] = (u8)(((val) & 0x000000FF));	\
+	} while (0)

-:30: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects?
#30: FILE: drivers/gpu/drm/i915/display/intel_lt_phy.c:1369:
+#define MULQ32_U32(x, y)	\
+	(((u64)((x) >> 32) * (y) << 32) + (u64)((x) & 0xFFFFFFFF) * (y))

-:30: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'y' - possible side-effects?
#30: FILE: drivers/gpu/drm/i915/display/intel_lt_phy.c:1369:
+#define MULQ32_U32(x, y)	\
+	(((u64)((x) >> 32) * (y) << 32) + (u64)((x) & 0xFFFFFFFF) * (y))

total: 0 errors, 0 warnings, 4 checks, 339 lines checked

✓ CI.KUnit: success for Enable LT PHY

[Patchwork]

== Series Details ==

Series: Enable LT PHY
URL   : https://patchwork.freedesktop.org/series/155954/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[04:22:03] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:22:07] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:22:38] Starting KUnit Kernel (1/1)...
[04:22:38] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:22:38] ================== guc_buf (11 subtests) ===================
[04:22:38] [PASSED] test_smallest
[04:22:38] [PASSED] test_largest
[04:22:38] [PASSED] test_granular
[04:22:38] [PASSED] test_unique
[04:22:38] [PASSED] test_overlap
[04:22:38] [PASSED] test_reusable
[04:22:38] [PASSED] test_too_big
[04:22:38] [PASSED] test_flush
[04:22:38] [PASSED] test_lookup
[04:22:38] [PASSED] test_data
[04:22:38] [PASSED] test_class
[04:22:38] ===================== [PASSED] guc_buf =====================
[04:22:38] =================== guc_dbm (7 subtests) ===================
[04:22:38] [PASSED] test_empty
[04:22:38] [PASSED] test_default
[04:22:38] ======================== test_size  ========================
[04:22:38] [PASSED] 4
[04:22:38] [PASSED] 8
[04:22:38] [PASSED] 32
[04:22:38] [PASSED] 256
[04:22:38] ==================== [PASSED] test_size ====================
[04:22:38] ======================= test_reuse  ========================
[04:22:38] [PASSED] 4
[04:22:38] [PASSED] 8
[04:22:38] [PASSED] 32
[04:22:38] [PASSED] 256
[04:22:38] =================== [PASSED] test_reuse ====================
[04:22:38] =================== test_range_overlap  ====================
[04:22:38] [PASSED] 4
[04:22:38] [PASSED] 8
[04:22:38] [PASSED] 32
[04:22:38] [PASSED] 256
[04:22:38] =============== [PASSED] test_range_overlap ================
[04:22:38] =================== test_range_compact  ====================
[04:22:38] [PASSED] 4
[04:22:38] [PASSED] 8
[04:22:38] [PASSED] 32
[04:22:38] [PASSED] 256
[04:22:38] =============== [PASSED] test_range_compact ================
[04:22:38] ==================== test_range_spare  =====================
[04:22:38] [PASSED] 4
[04:22:38] [PASSED] 8
[04:22:38] [PASSED] 32
[04:22:38] [PASSED] 256
[04:22:38] ================ [PASSED] test_range_spare =================
[04:22:38] ===================== [PASSED] guc_dbm =====================
[04:22:38] =================== guc_idm (6 subtests) ===================
[04:22:38] [PASSED] bad_init
[04:22:38] [PASSED] no_init
[04:22:38] [PASSED] init_fini
[04:22:38] [PASSED] check_used
[04:22:38] [PASSED] check_quota
[04:22:38] [PASSED] check_all
[04:22:38] ===================== [PASSED] guc_idm =====================
[04:22:38] ================== no_relay (3 subtests) ===================
[04:22:38] [PASSED] xe_drops_guc2pf_if_not_ready
[04:22:38] [PASSED] xe_drops_guc2vf_if_not_ready
[04:22:38] [PASSED] xe_rejects_send_if_not_ready
[04:22:38] ==================== [PASSED] no_relay =====================
[04:22:38] ================== pf_relay (14 subtests) ==================
[04:22:38] [PASSED] pf_rejects_guc2pf_too_short
[04:22:38] [PASSED] pf_rejects_guc2pf_too_long
[04:22:38] [PASSED] pf_rejects_guc2pf_no_payload
[04:22:38] [PASSED] pf_fails_no_payload
[04:22:38] [PASSED] pf_fails_bad_origin
[04:22:38] [PASSED] pf_fails_bad_type
[04:22:38] [PASSED] pf_txn_reports_error
[04:22:38] [PASSED] pf_txn_sends_pf2guc
[04:22:38] [PASSED] pf_sends_pf2guc
[04:22:38] [SKIPPED] pf_loopback_nop
[04:22:38] [SKIPPED] pf_loopback_echo
[04:22:38] [SKIPPED] pf_loopback_fail
[04:22:38] [SKIPPED] pf_loopback_busy
[04:22:38] [SKIPPED] pf_loopback_retry
[04:22:38] ==================== [PASSED] pf_relay =====================
[04:22:38] ================== vf_relay (3 subtests) ===================
[04:22:38] [PASSED] vf_rejects_guc2vf_too_short
[04:22:38] [PASSED] vf_rejects_guc2vf_too_long
[04:22:38] [PASSED] vf_rejects_guc2vf_no_payload
[04:22:38] ==================== [PASSED] vf_relay =====================
[04:22:38] ===================== lmtt (1 subtest) =====================
[04:22:38] ======================== test_ops  =========================
[04:22:38] [PASSED] 2-level
[04:22:38] [PASSED] multi-level
[04:22:38] ==================== [PASSED] test_ops =====================
[04:22:38] ====================== [PASSED] lmtt =======================
[04:22:38] ================= pf_service (11 subtests) =================
[04:22:38] [PASSED] pf_negotiate_any
[04:22:38] [PASSED] pf_negotiate_base_match
[04:22:38] [PASSED] pf_negotiate_base_newer
[04:22:38] [PASSED] pf_negotiate_base_next
[04:22:38] [SKIPPED] pf_negotiate_base_older
[04:22:38] [PASSED] pf_negotiate_base_prev
[04:22:38] [PASSED] pf_negotiate_latest_match
[04:22:38] [PASSED] pf_negotiate_latest_newer
[04:22:38] [PASSED] pf_negotiate_latest_next
[04:22:38] [SKIPPED] pf_negotiate_latest_older
[04:22:38] [SKIPPED] pf_negotiate_latest_prev
[04:22:38] =================== [PASSED] pf_service ====================
[04:22:38] ================= xe_guc_g2g (2 subtests) ==================
[04:22:38] ============== xe_live_guc_g2g_kunit_default  ==============
[04:22:38] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[04:22:38] ============== xe_live_guc_g2g_kunit_allmem  ===============
[04:22:38] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[04:22:38] =================== [SKIPPED] xe_guc_g2g ===================
[04:22:38] =================== xe_mocs (2 subtests) ===================
[04:22:38] ================ xe_live_mocs_kernel_kunit  ================
[04:22:38] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[04:22:38] ================ xe_live_mocs_reset_kunit  =================
[04:22:38] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[04:22:38] ==================== [SKIPPED] xe_mocs =====================
[04:22:38] ================= xe_migrate (2 subtests) ==================
[04:22:38] ================= xe_migrate_sanity_kunit  =================
[04:22:38] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[04:22:38] ================== xe_validate_ccs_kunit  ==================
[04:22:38] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[04:22:38] =================== [SKIPPED] xe_migrate ===================
[04:22:38] ================== xe_dma_buf (1 subtest) ==================
[04:22:38] ==================== xe_dma_buf_kunit  =====================
[04:22:38] ================ [SKIPPED] xe_dma_buf_kunit ================
[04:22:38] =================== [SKIPPED] xe_dma_buf ===================
[04:22:38] ================= xe_bo_shrink (1 subtest) =================
[04:22:38] =================== xe_bo_shrink_kunit  ====================
[04:22:38] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[04:22:38] ================== [SKIPPED] xe_bo_shrink ==================
[04:22:38] ==================== xe_bo (2 subtests) ====================
[04:22:38] ================== xe_ccs_migrate_kunit  ===================
[04:22:38] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[04:22:38] ==================== xe_bo_evict_kunit  ====================
[04:22:38] =============== [SKIPPED] xe_bo_evict_kunit ================
[04:22:38] ===================== [SKIPPED] xe_bo ======================
[04:22:38] ==================== args (11 subtests) ====================
[04:22:38] [PASSED] count_args_test
[04:22:38] [PASSED] call_args_example
[04:22:38] [PASSED] call_args_test
[04:22:38] [PASSED] drop_first_arg_example
[04:22:38] [PASSED] drop_first_arg_test
[04:22:38] [PASSED] first_arg_example
[04:22:38] [PASSED] first_arg_test
[04:22:38] [PASSED] last_arg_example
[04:22:38] [PASSED] last_arg_test
[04:22:38] [PASSED] pick_arg_example
[04:22:38] [PASSED] sep_comma_example
[04:22:38] ====================== [PASSED] args =======================
[04:22:38] =================== xe_pci (3 subtests) ====================
[04:22:38] ==================== check_graphics_ip  ====================
[04:22:38] [PASSED] 12.00 Xe_LP
[04:22:38] [PASSED] 12.10 Xe_LP+
[04:22:38] [PASSED] 12.55 Xe_HPG
[04:22:38] [PASSED] 12.60 Xe_HPC
[04:22:38] [PASSED] 12.70 Xe_LPG
[04:22:38] [PASSED] 12.71 Xe_LPG
[04:22:38] [PASSED] 12.74 Xe_LPG+
[04:22:38] [PASSED] 20.01 Xe2_HPG
[04:22:38] [PASSED] 20.02 Xe2_HPG
[04:22:38] [PASSED] 20.04 Xe2_LPG
[04:22:38] [PASSED] 30.00 Xe3_LPG
[04:22:38] [PASSED] 30.01 Xe3_LPG
[04:22:38] [PASSED] 30.03 Xe3_LPG
[04:22:38] ================ [PASSED] check_graphics_ip ================
[04:22:38] ===================== check_media_ip  ======================
[04:22:38] [PASSED] 12.00 Xe_M
[04:22:38] [PASSED] 12.55 Xe_HPM
[04:22:38] [PASSED] 13.00 Xe_LPM+
[04:22:38] [PASSED] 13.01 Xe2_HPM
[04:22:38] [PASSED] 20.00 Xe2_LPM
[04:22:38] [PASSED] 30.00 Xe3_LPM
[04:22:38] [PASSED] 30.02 Xe3_LPM
[04:22:38] ================= [PASSED] check_media_ip ==================
[04:22:38] ================= check_platform_gt_count  =================
[04:22:38] [PASSED] 0x9A60 (TIGERLAKE)
[04:22:38] [PASSED] 0x9A68 (TIGERLAKE)
[04:22:38] [PASSED] 0x9A70 (TIGERLAKE)
[04:22:38] [PASSED] 0x9A40 (TIGERLAKE)
[04:22:38] [PASSED] 0x9A49 (TIGERLAKE)
[04:22:38] [PASSED] 0x9A59 (TIGERLAKE)
[04:22:38] [PASSED] 0x9A78 (TIGERLAKE)
[04:22:38] [PASSED] 0x9AC0 (TIGERLAKE)
[04:22:38] [PASSED] 0x9AC9 (TIGERLAKE)
[04:22:38] [PASSED] 0x9AD9 (TIGERLAKE)
[04:22:38] [PASSED] 0x9AF8 (TIGERLAKE)
[04:22:38] [PASSED] 0x4C80 (ROCKETLAKE)
[04:22:38] [PASSED] 0x4C8A (ROCKETLAKE)
[04:22:38] [PASSED] 0x4C8B (ROCKETLAKE)
[04:22:38] [PASSED] 0x4C8C (ROCKETLAKE)
[04:22:38] [PASSED] 0x4C90 (ROCKETLAKE)
[04:22:38] [PASSED] 0x4C9A (ROCKETLAKE)
[04:22:38] [PASSED] 0x4680 (ALDERLAKE_S)
[04:22:38] [PASSED] 0x4682 (ALDERLAKE_S)
[04:22:38] [PASSED] 0x4688 (ALDERLAKE_S)
[04:22:38] [PASSED] 0x468A (ALDERLAKE_S)
[04:22:38] [PASSED] 0x468B (ALDERLAKE_S)
[04:22:38] [PASSED] 0x4690 (ALDERLAKE_S)
[04:22:38] [PASSED] 0x4692 (ALDERLAKE_S)
[04:22:38] [PASSED] 0x4693 (ALDERLAKE_S)
[04:22:38] [PASSED] 0x46A0 (ALDERLAKE_P)
[04:22:38] [PASSED] 0x46A1 (ALDERLAKE_P)
[04:22:38] [PASSED] 0x46A2 (ALDERLAKE_P)
[04:22:38] [PASSED] 0x46A3 (ALDERLAKE_P)
[04:22:38] [PASSED] 0x46A6 (ALDERLAKE_P)
[04:22:38] [PASSED] 0x46A8 (ALDERLAKE_P)
[04:22:38] [PASSED] 0x46AA (ALDERLAKE_P)
[04:22:38] [PASSED] 0x462A (ALDERLAKE_P)
[04:22:38] [PASSED] 0x4626 (ALDERLAKE_P)
[04:22:38] [PASSED] 0x4628 (ALDERLAKE_P)
[04:22:38] [PASSED] 0x46B0 (ALDERLAKE_P)
[04:22:38] [PASSED] 0x46B1 (ALDERLAKE_P)
[04:22:38] [PASSED] 0x46B2 (ALDERLAKE_P)
[04:22:38] [PASSED] 0x46B3 (ALDERLAKE_P)
[04:22:38] [PASSED] 0x46C0 (ALDERLAKE_P)
[04:22:38] [PASSED] 0x46C1 (ALDERLAKE_P)
[04:22:38] [PASSED] 0x46C2 (ALDERLAKE_P)
[04:22:38] [PASSED] 0x46C3 (ALDERLAKE_P)
[04:22:38] [PASSED] 0x46D0 (ALDERLAKE_N)
[04:22:38] [PASSED] 0x46D1 (ALDERLAKE_N)
[04:22:38] [PASSED] 0x46D2 (ALDERLAKE_N)
[04:22:38] [PASSED] 0x46D3 (ALDERLAKE_N)
[04:22:38] [PASSED] 0x46D4 (ALDERLAKE_N)
[04:22:38] [PASSED] 0xA721 (ALDERLAKE_P)
[04:22:38] [PASSED] 0xA7A1 (ALDERLAKE_P)
[04:22:38] [PASSED] 0xA7A9 (ALDERLAKE_P)
[04:22:38] [PASSED] 0xA7AC (ALDERLAKE_P)
[04:22:38] [PASSED] 0xA7AD (ALDERLAKE_P)
[04:22:38] [PASSED] 0xA720 (ALDERLAKE_P)
[04:22:38] [PASSED] 0xA7A0 (ALDERLAKE_P)
[04:22:38] [PASSED] 0xA7A8 (ALDERLAKE_P)
[04:22:38] [PASSED] 0xA7AA (ALDERLAKE_P)
[04:22:38] [PASSED] 0xA7AB (ALDERLAKE_P)
[04:22:38] [PASSED] 0xA780 (ALDERLAKE_S)
[04:22:38] [PASSED] 0xA781 (ALDERLAKE_S)
[04:22:38] [PASSED] 0xA782 (ALDERLAKE_S)
[04:22:38] [PASSED] 0xA783 (ALDERLAKE_S)
[04:22:38] [PASSED] 0xA788 (ALDERLAKE_S)
[04:22:38] [PASSED] 0xA789 (ALDERLAKE_S)
[04:22:38] [PASSED] 0xA78A (ALDERLAKE_S)
[04:22:38] [PASSED] 0xA78B (ALDERLAKE_S)
[04:22:38] [PASSED] 0x4905 (DG1)
[04:22:38] [PASSED] 0x4906 (DG1)
[04:22:38] [PASSED] 0x4907 (DG1)
[04:22:38] [PASSED] 0x4908 (DG1)
[04:22:38] [PASSED] 0x4909 (DG1)
[04:22:38] [PASSED] 0x56C0 (DG2)
[04:22:38] [PASSED] 0x56C2 (DG2)
[04:22:38] [PASSED] 0x56C1 (DG2)
[04:22:38] [PASSED] 0x7D51 (METEORLAKE)
[04:22:38] [PASSED] 0x7DD1 (METEORLAKE)
[04:22:38] [PASSED] 0x7D41 (METEORLAKE)
[04:22:38] [PASSED] 0x7D67 (METEORLAKE)
[04:22:38] [PASSED] 0xB640 (METEORLAKE)
[04:22:38] [PASSED] 0x56A0 (DG2)
[04:22:38] [PASSED] 0x56A1 (DG2)
[04:22:38] [PASSED] 0x56A2 (DG2)
[04:22:38] [PASSED] 0x56BE (DG2)
[04:22:38] [PASSED] 0x56BF (DG2)
[04:22:38] [PASSED] 0x5690 (DG2)
[04:22:38] [PASSED] 0x5691 (DG2)
[04:22:38] [PASSED] 0x5692 (DG2)
[04:22:38] [PASSED] 0x56A5 (DG2)
[04:22:38] [PASSED] 0x56A6 (DG2)
[04:22:38] [PASSED] 0x56B0 (DG2)
[04:22:38] [PASSED] 0x56B1 (DG2)
[04:22:38] [PASSED] 0x56BA (DG2)
[04:22:38] [PASSED] 0x56BB (DG2)
[04:22:38] [PASSED] 0x56BC (DG2)
[04:22:38] [PASSED] 0x56BD (DG2)
[04:22:38] [PASSED] 0x5693 (DG2)
[04:22:38] [PASSED] 0x5694 (DG2)
[04:22:38] [PASSED] 0x5695 (DG2)
[04:22:38] [PASSED] 0x56A3 (DG2)
[04:22:38] [PASSED] 0x56A4 (DG2)
[04:22:38] [PASSED] 0x56B2 (DG2)
[04:22:38] [PASSED] 0x56B3 (DG2)
[04:22:38] [PASSED] 0x5696 (DG2)
[04:22:38] [PASSED] 0x5697 (DG2)
[04:22:38] [PASSED] 0xB69 (PVC)
[04:22:38] [PASSED] 0xB6E (PVC)
[04:22:38] [PASSED] 0xBD4 (PVC)
[04:22:38] [PASSED] 0xBD5 (PVC)
[04:22:38] [PASSED] 0xBD6 (PVC)
[04:22:38] [PASSED] 0xBD7 (PVC)
[04:22:38] [PASSED] 0xBD8 (PVC)
[04:22:38] [PASSED] 0xBD9 (PVC)
[04:22:38] [PASSED] 0xBDA (PVC)
[04:22:38] [PASSED] 0xBDB (PVC)
[04:22:38] [PASSED] 0xBE0 (PVC)
[04:22:38] [PASSED] 0xBE1 (PVC)
[04:22:38] [PASSED] 0xBE5 (PVC)
[04:22:38] [PASSED] 0x7D40 (METEORLAKE)
[04:22:38] [PASSED] 0x7D45 (METEORLAKE)
[04:22:38] [PASSED] 0x7D55 (METEORLAKE)
[04:22:38] [PASSED] 0x7D60 (METEORLAKE)
[04:22:38] [PASSED] 0x7DD5 (METEORLAKE)
[04:22:38] [PASSED] 0x6420 (LUNARLAKE)
[04:22:38] [PASSED] 0x64A0 (LUNARLAKE)
[04:22:38] [PASSED] 0x64B0 (LUNARLAKE)
[04:22:38] [PASSED] 0xE202 (BATTLEMAGE)
[04:22:38] [PASSED] 0xE209 (BATTLEMAGE)
[04:22:38] [PASSED] 0xE20B (BATTLEMAGE)
[04:22:38] [PASSED] 0xE20C (BATTLEMAGE)
[04:22:38] [PASSED] 0xE20D (BATTLEMAGE)
[04:22:38] [PASSED] 0xE210 (BATTLEMAGE)
[04:22:38] [PASSED] 0xE211 (BATTLEMAGE)
[04:22:38] [PASSED] 0xE212 (BATTLEMAGE)
[04:22:38] [PASSED] 0xE216 (BATTLEMAGE)
[04:22:38] [PASSED] 0xE220 (BATTLEMAGE)
[04:22:38] [PASSED] 0xE221 (BATTLEMAGE)
[04:22:38] [PASSED] 0xE222 (BATTLEMAGE)
[04:22:38] [PASSED] 0xE223 (BATTLEMAGE)
[04:22:38] [PASSED] 0xB080 (PANTHERLAKE)
[04:22:38] [PASSED] 0xB081 (PANTHERLAKE)
[04:22:38] [PASSED] 0xB082 (PANTHERLAKE)
[04:22:38] [PASSED] 0xB083 (PANTHERLAKE)
[04:22:38] [PASSED] 0xB084 (PANTHERLAKE)
[04:22:38] [PASSED] 0xB085 (PANTHERLAKE)
[04:22:38] [PASSED] 0xB086 (PANTHERLAKE)
[04:22:38] [PASSED] 0xB087 (PANTHERLAKE)
[04:22:38] [PASSED] 0xB08F (PANTHERLAKE)
[04:22:38] [PASSED] 0xB090 (PANTHERLAKE)
[04:22:38] [PASSED] 0xB0A0 (PANTHERLAKE)
[04:22:38] [PASSED] 0xB0B0 (PANTHERLAKE)
[04:22:38] [PASSED] 0xFD80 (PANTHERLAKE)
[04:22:38] [PASSED] 0xFD81 (PANTHERLAKE)
[04:22:38] ============= [PASSED] check_platform_gt_count =============
[04:22:38] ===================== [PASSED] xe_pci ======================
[04:22:38] =================== xe_rtp (2 subtests) ====================
[04:22:38] =============== xe_rtp_process_to_sr_tests  ================
[04:22:38] [PASSED] coalesce-same-reg
[04:22:38] [PASSED] no-match-no-add
[04:22:38] [PASSED] match-or
[04:22:38] [PASSED] match-or-xfail
[04:22:38] [PASSED] no-match-no-add-multiple-rules
[04:22:38] [PASSED] two-regs-two-entries
[04:22:38] [PASSED] clr-one-set-other
[04:22:38] [PASSED] set-field
[04:22:38] [PASSED] conflict-duplicate
[04:22:38] [PASSED] conflict-not-disjoint
[04:22:38] [PASSED] conflict-reg-type
[04:22:38] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[04:22:38] ================== xe_rtp_process_tests  ===================
[04:22:38] [PASSED] active1
[04:22:38] [PASSED] active2
[04:22:38] [PASSED] active-inactive
[04:22:38] [PASSED] inactive-active
[04:22:38] [PASSED] inactive-1st_or_active-inactive
[04:22:38] [PASSED] inactive-2nd_or_active-inactive
[04:22:38] [PASSED] inactive-last_or_active-inactive
[04:22:38] [PASSED] inactive-no_or_active-inactive
[04:22:38] ============== [PASSED] xe_rtp_process_tests ===============
[04:22:38] ===================== [PASSED] xe_rtp ======================
[04:22:38] ==================== xe_wa (1 subtest) =====================
[04:22:38] ======================== xe_wa_gt  =========================
[04:22:38] [PASSED] TIGERLAKE B0
[04:22:38] [PASSED] DG1 A0
[04:22:38] [PASSED] DG1 B0
[04:22:38] [PASSED] ALDERLAKE_S A0
[04:22:38] [PASSED] ALDERLAKE_S B0
stty: 'standard input': Inappropriate ioctl for device
[04:22:38] [PASSED] ALDERLAKE_S C0
[04:22:38] [PASSED] ALDERLAKE_S D0
[04:22:38] [PASSED] ALDERLAKE_P A0
[04:22:38] [PASSED] ALDERLAKE_P B0
[04:22:38] [PASSED] ALDERLAKE_P C0
[04:22:38] [PASSED] ALDERLAKE_S RPLS D0
[04:22:38] [PASSED] ALDERLAKE_P RPLU E0
[04:22:38] [PASSED] DG2 G10 C0
[04:22:38] [PASSED] DG2 G11 B1
[04:22:38] [PASSED] DG2 G12 A1
[04:22:38] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[04:22:38] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[04:22:38] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[04:22:38] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[04:22:38] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[04:22:38] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[04:22:38] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[04:22:38] ==================== [PASSED] xe_wa_gt =====================
[04:22:38] ====================== [PASSED] xe_wa ======================
[04:22:38] ============================================================
[04:22:38] Testing complete. Ran 306 tests: passed: 288, skipped: 18
[04:22:38] Elapsed time: 35.082s total, 4.298s configuring, 30.417s building, 0.331s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[04:22:38] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:22:40] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:23:04] Starting KUnit Kernel (1/1)...
[04:23:04] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:23:04] ============ drm_test_pick_cmdline (2 subtests) ============
[04:23:04] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[04:23:04] =============== drm_test_pick_cmdline_named  ===============
[04:23:04] [PASSED] NTSC
[04:23:04] [PASSED] NTSC-J
[04:23:04] [PASSED] PAL
[04:23:04] [PASSED] PAL-M
[04:23:04] =========== [PASSED] drm_test_pick_cmdline_named ===========
[04:23:04] ============== [PASSED] drm_test_pick_cmdline ==============
[04:23:04] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[04:23:04] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[04:23:04] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[04:23:04] =========== drm_validate_clone_mode (2 subtests) ===========
[04:23:04] ============== drm_test_check_in_clone_mode  ===============
[04:23:04] [PASSED] in_clone_mode
[04:23:04] [PASSED] not_in_clone_mode
[04:23:04] ========== [PASSED] drm_test_check_in_clone_mode ===========
[04:23:04] =============== drm_test_check_valid_clones  ===============
[04:23:04] [PASSED] not_in_clone_mode
[04:23:04] [PASSED] valid_clone
[04:23:04] [PASSED] invalid_clone
[04:23:04] =========== [PASSED] drm_test_check_valid_clones ===========
[04:23:04] ============= [PASSED] drm_validate_clone_mode =============
[04:23:04] ============= drm_validate_modeset (1 subtest) =============
[04:23:04] [PASSED] drm_test_check_connector_changed_modeset
[04:23:04] ============== [PASSED] drm_validate_modeset ===============
[04:23:04] ====== drm_test_bridge_get_current_state (2 subtests) ======
[04:23:04] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[04:23:04] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[04:23:04] ======== [PASSED] drm_test_bridge_get_current_state ========
[04:23:04] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[04:23:04] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[04:23:04] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[04:23:04] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[04:23:04] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[04:23:04] ============== drm_bridge_alloc (2 subtests) ===============
[04:23:04] [PASSED] drm_test_drm_bridge_alloc_basic
[04:23:04] [PASSED] drm_test_drm_bridge_alloc_get_put
[04:23:04] ================ [PASSED] drm_bridge_alloc =================
[04:23:04] ================== drm_buddy (8 subtests) ==================
[04:23:04] [PASSED] drm_test_buddy_alloc_limit
[04:23:04] [PASSED] drm_test_buddy_alloc_optimistic
[04:23:04] [PASSED] drm_test_buddy_alloc_pessimistic
[04:23:04] [PASSED] drm_test_buddy_alloc_pathological
[04:23:04] [PASSED] drm_test_buddy_alloc_contiguous
[04:23:04] [PASSED] drm_test_buddy_alloc_clear
[04:23:05] [PASSED] drm_test_buddy_alloc_range_bias
[04:23:05] [PASSED] drm_test_buddy_fragmentation_performance
[04:23:05] ==================== [PASSED] drm_buddy ====================
[04:23:05] ============= drm_cmdline_parser (40 subtests) =============
[04:23:05] [PASSED] drm_test_cmdline_force_d_only
[04:23:05] [PASSED] drm_test_cmdline_force_D_only_dvi
[04:23:05] [PASSED] drm_test_cmdline_force_D_only_hdmi
[04:23:05] [PASSED] drm_test_cmdline_force_D_only_not_digital
[04:23:05] [PASSED] drm_test_cmdline_force_e_only
[04:23:05] [PASSED] drm_test_cmdline_res
[04:23:05] [PASSED] drm_test_cmdline_res_vesa
[04:23:05] [PASSED] drm_test_cmdline_res_vesa_rblank
[04:23:05] [PASSED] drm_test_cmdline_res_rblank
[04:23:05] [PASSED] drm_test_cmdline_res_bpp
[04:23:05] [PASSED] drm_test_cmdline_res_refresh
[04:23:05] [PASSED] drm_test_cmdline_res_bpp_refresh
[04:23:05] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[04:23:05] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[04:23:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[04:23:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[04:23:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[04:23:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[04:23:05] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[04:23:05] [PASSED] drm_test_cmdline_res_margins_force_on
[04:23:05] [PASSED] drm_test_cmdline_res_vesa_margins
[04:23:05] [PASSED] drm_test_cmdline_name
[04:23:05] [PASSED] drm_test_cmdline_name_bpp
[04:23:05] [PASSED] drm_test_cmdline_name_option
[04:23:05] [PASSED] drm_test_cmdline_name_bpp_option
[04:23:05] [PASSED] drm_test_cmdline_rotate_0
[04:23:05] [PASSED] drm_test_cmdline_rotate_90
[04:23:05] [PASSED] drm_test_cmdline_rotate_180
[04:23:05] [PASSED] drm_test_cmdline_rotate_270
[04:23:05] [PASSED] drm_test_cmdline_hmirror
[04:23:05] [PASSED] drm_test_cmdline_vmirror
[04:23:05] [PASSED] drm_test_cmdline_margin_options
[04:23:05] [PASSED] drm_test_cmdline_multiple_options
[04:23:05] [PASSED] drm_test_cmdline_bpp_extra_and_option
[04:23:05] [PASSED] drm_test_cmdline_extra_and_option
[04:23:05] [PASSED] drm_test_cmdline_freestanding_options
[04:23:05] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[04:23:05] [PASSED] drm_test_cmdline_panel_orientation
[04:23:05] ================ drm_test_cmdline_invalid  =================
[04:23:05] [PASSED] margin_only
[04:23:05] [PASSED] interlace_only
[04:23:05] [PASSED] res_missing_x
[04:23:05] [PASSED] res_missing_y
[04:23:05] [PASSED] res_bad_y
[04:23:05] [PASSED] res_missing_y_bpp
[04:23:05] [PASSED] res_bad_bpp
[04:23:05] [PASSED] res_bad_refresh
[04:23:05] [PASSED] res_bpp_refresh_force_on_off
[04:23:05] [PASSED] res_invalid_mode
[04:23:05] [PASSED] res_bpp_wrong_place_mode
[04:23:05] [PASSED] name_bpp_refresh
[04:23:05] [PASSED] name_refresh
[04:23:05] [PASSED] name_refresh_wrong_mode
[04:23:05] [PASSED] name_refresh_invalid_mode
[04:23:05] [PASSED] rotate_multiple
[04:23:05] [PASSED] rotate_invalid_val
[04:23:05] [PASSED] rotate_truncated
[04:23:05] [PASSED] invalid_option
[04:23:05] [PASSED] invalid_tv_option
[04:23:05] [PASSED] truncated_tv_option
[04:23:05] ============ [PASSED] drm_test_cmdline_invalid =============
[04:23:05] =============== drm_test_cmdline_tv_options  ===============
[04:23:05] [PASSED] NTSC
[04:23:05] [PASSED] NTSC_443
[04:23:05] [PASSED] NTSC_J
[04:23:05] [PASSED] PAL
[04:23:05] [PASSED] PAL_M
[04:23:05] [PASSED] PAL_N
[04:23:05] [PASSED] SECAM
[04:23:05] [PASSED] MONO_525
[04:23:05] [PASSED] MONO_625
[04:23:05] =========== [PASSED] drm_test_cmdline_tv_options ===========
[04:23:05] =============== [PASSED] drm_cmdline_parser ================
[04:23:05] ========== drmm_connector_hdmi_init (20 subtests) ==========
[04:23:05] [PASSED] drm_test_connector_hdmi_init_valid
[04:23:05] [PASSED] drm_test_connector_hdmi_init_bpc_8
[04:23:05] [PASSED] drm_test_connector_hdmi_init_bpc_10
[04:23:05] [PASSED] drm_test_connector_hdmi_init_bpc_12
[04:23:05] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[04:23:05] [PASSED] drm_test_connector_hdmi_init_bpc_null
[04:23:05] [PASSED] drm_test_connector_hdmi_init_formats_empty
[04:23:05] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[04:23:05] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[04:23:05] [PASSED] supported_formats=0x9 yuv420_allowed=1
[04:23:05] [PASSED] supported_formats=0x9 yuv420_allowed=0
[04:23:05] [PASSED] supported_formats=0x3 yuv420_allowed=1
[04:23:05] [PASSED] supported_formats=0x3 yuv420_allowed=0
[04:23:05] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[04:23:05] [PASSED] drm_test_connector_hdmi_init_null_ddc
[04:23:05] [PASSED] drm_test_connector_hdmi_init_null_product
[04:23:05] [PASSED] drm_test_connector_hdmi_init_null_vendor
[04:23:05] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[04:23:05] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[04:23:05] [PASSED] drm_test_connector_hdmi_init_product_valid
[04:23:05] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[04:23:05] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[04:23:05] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[04:23:05] ========= drm_test_connector_hdmi_init_type_valid  =========
[04:23:05] [PASSED] HDMI-A
[04:23:05] [PASSED] HDMI-B
[04:23:05] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[04:23:05] ======== drm_test_connector_hdmi_init_type_invalid  ========
[04:23:05] [PASSED] Unknown
[04:23:05] [PASSED] VGA
[04:23:05] [PASSED] DVI-I
[04:23:05] [PASSED] DVI-D
[04:23:05] [PASSED] DVI-A
[04:23:05] [PASSED] Composite
[04:23:05] [PASSED] SVIDEO
[04:23:05] [PASSED] LVDS
[04:23:05] [PASSED] Component
[04:23:05] [PASSED] DIN
[04:23:05] [PASSED] DP
[04:23:05] [PASSED] TV
[04:23:05] [PASSED] eDP
[04:23:05] [PASSED] Virtual
[04:23:05] [PASSED] DSI
[04:23:05] [PASSED] DPI
[04:23:05] [PASSED] Writeback
[04:23:05] [PASSED] SPI
[04:23:05] [PASSED] USB
[04:23:05] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[04:23:05] ============ [PASSED] drmm_connector_hdmi_init =============
[04:23:05] ============= drmm_connector_init (3 subtests) =============
[04:23:05] [PASSED] drm_test_drmm_connector_init
[04:23:05] [PASSED] drm_test_drmm_connector_init_null_ddc
[04:23:05] ========= drm_test_drmm_connector_init_type_valid  =========
[04:23:05] [PASSED] Unknown
[04:23:05] [PASSED] VGA
[04:23:05] [PASSED] DVI-I
[04:23:05] [PASSED] DVI-D
[04:23:05] [PASSED] DVI-A
[04:23:05] [PASSED] Composite
[04:23:05] [PASSED] SVIDEO
[04:23:05] [PASSED] LVDS
[04:23:05] [PASSED] Component
[04:23:05] [PASSED] DIN
[04:23:05] [PASSED] DP
[04:23:05] [PASSED] HDMI-A
[04:23:05] [PASSED] HDMI-B
[04:23:05] [PASSED] TV
[04:23:05] [PASSED] eDP
[04:23:05] [PASSED] Virtual
[04:23:05] [PASSED] DSI
[04:23:05] [PASSED] DPI
[04:23:05] [PASSED] Writeback
[04:23:05] [PASSED] SPI
[04:23:05] [PASSED] USB
[04:23:05] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[04:23:05] =============== [PASSED] drmm_connector_init ===============
[04:23:05] ========= drm_connector_dynamic_init (6 subtests) ==========
[04:23:05] [PASSED] drm_test_drm_connector_dynamic_init
[04:23:05] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[04:23:05] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[04:23:05] [PASSED] drm_test_drm_connector_dynamic_init_properties
[04:23:05] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[04:23:05] [PASSED] Unknown
[04:23:05] [PASSED] VGA
[04:23:05] [PASSED] DVI-I
[04:23:05] [PASSED] DVI-D
[04:23:05] [PASSED] DVI-A
[04:23:05] [PASSED] Composite
[04:23:05] [PASSED] SVIDEO
[04:23:05] [PASSED] LVDS
[04:23:05] [PASSED] Component
[04:23:05] [PASSED] DIN
[04:23:05] [PASSED] DP
[04:23:05] [PASSED] HDMI-A
[04:23:05] [PASSED] HDMI-B
[04:23:05] [PASSED] TV
[04:23:05] [PASSED] eDP
[04:23:05] [PASSED] Virtual
[04:23:05] [PASSED] DSI
[04:23:05] [PASSED] DPI
[04:23:05] [PASSED] Writeback
[04:23:05] [PASSED] SPI
[04:23:05] [PASSED] USB
[04:23:05] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[04:23:05] ======== drm_test_drm_connector_dynamic_init_name  =========
[04:23:05] [PASSED] Unknown
[04:23:05] [PASSED] VGA
[04:23:05] [PASSED] DVI-I
[04:23:05] [PASSED] DVI-D
[04:23:05] [PASSED] DVI-A
[04:23:05] [PASSED] Composite
[04:23:05] [PASSED] SVIDEO
[04:23:05] [PASSED] LVDS
[04:23:05] [PASSED] Component
[04:23:05] [PASSED] DIN
[04:23:05] [PASSED] DP
[04:23:05] [PASSED] HDMI-A
[04:23:05] [PASSED] HDMI-B
[04:23:05] [PASSED] TV
[04:23:05] [PASSED] eDP
[04:23:05] [PASSED] Virtual
[04:23:05] [PASSED] DSI
[04:23:05] [PASSED] DPI
[04:23:05] [PASSED] Writeback
[04:23:05] [PASSED] SPI
[04:23:05] [PASSED] USB
[04:23:05] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[04:23:05] =========== [PASSED] drm_connector_dynamic_init ============
[04:23:05] ==== drm_connector_dynamic_register_early (4 subtests) =====
[04:23:05] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[04:23:05] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[04:23:05] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[04:23:05] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[04:23:05] ====== [PASSED] drm_connector_dynamic_register_early =======
[04:23:05] ======= drm_connector_dynamic_register (7 subtests) ========
[04:23:05] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[04:23:05] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[04:23:05] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[04:23:05] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[04:23:05] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[04:23:05] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[04:23:05] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[04:23:05] ========= [PASSED] drm_connector_dynamic_register ==========
[04:23:05] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[04:23:05] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[04:23:05] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[04:23:05] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[04:23:05] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[04:23:05] ========== drm_test_get_tv_mode_from_name_valid  ===========
[04:23:05] [PASSED] NTSC
[04:23:05] [PASSED] NTSC-443
[04:23:05] [PASSED] NTSC-J
[04:23:05] [PASSED] PAL
[04:23:05] [PASSED] PAL-M
[04:23:05] [PASSED] PAL-N
[04:23:05] [PASSED] SECAM
[04:23:05] [PASSED] Mono
[04:23:05] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[04:23:05] [PASSED] drm_test_get_tv_mode_from_name_truncated
[04:23:05] ============ [PASSED] drm_get_tv_mode_from_name ============
[04:23:05] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[04:23:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[04:23:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[04:23:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[04:23:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[04:23:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[04:23:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[04:23:05] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[04:23:05] [PASSED] VIC 96
[04:23:05] [PASSED] VIC 97
[04:23:05] [PASSED] VIC 101
[04:23:05] [PASSED] VIC 102
[04:23:05] [PASSED] VIC 106
[04:23:05] [PASSED] VIC 107
[04:23:05] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[04:23:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[04:23:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[04:23:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[04:23:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[04:23:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[04:23:05] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[04:23:05] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[04:23:05] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[04:23:05] [PASSED] Automatic
[04:23:05] [PASSED] Full
[04:23:05] [PASSED] Limited 16:235
[04:23:05] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[04:23:05] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[04:23:05] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[04:23:05] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[04:23:05] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[04:23:05] [PASSED] RGB
[04:23:05] [PASSED] YUV 4:2:0
[04:23:05] [PASSED] YUV 4:2:2
[04:23:05] [PASSED] YUV 4:4:4
[04:23:05] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[04:23:05] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[04:23:05] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[04:23:05] ============= drm_damage_helper (21 subtests) ==============
[04:23:05] [PASSED] drm_test_damage_iter_no_damage
[04:23:05] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[04:23:05] [PASSED] drm_test_damage_iter_no_damage_src_moved
[04:23:05] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[04:23:05] [PASSED] drm_test_damage_iter_no_damage_not_visible
[04:23:05] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[04:23:05] [PASSED] drm_test_damage_iter_no_damage_no_fb
[04:23:05] [PASSED] drm_test_damage_iter_simple_damage
[04:23:05] [PASSED] drm_test_damage_iter_single_damage
[04:23:05] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[04:23:05] [PASSED] drm_test_damage_iter_single_damage_outside_src
[04:23:05] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[04:23:05] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[04:23:05] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[04:23:05] [PASSED] drm_test_damage_iter_single_damage_src_moved
[04:23:05] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[04:23:05] [PASSED] drm_test_damage_iter_damage
[04:23:05] [PASSED] drm_test_damage_iter_damage_one_intersect
[04:23:05] [PASSED] drm_test_damage_iter_damage_one_outside
[04:23:05] [PASSED] drm_test_damage_iter_damage_src_moved
[04:23:05] [PASSED] drm_test_damage_iter_damage_not_visible
[04:23:05] ================ [PASSED] drm_damage_helper ================
[04:23:05] ============== drm_dp_mst_helper (3 subtests) ==============
[04:23:05] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[04:23:05] [PASSED] Clock 154000 BPP 30 DSC disabled
[04:23:05] [PASSED] Clock 234000 BPP 30 DSC disabled
[04:23:05] [PASSED] Clock 297000 BPP 24 DSC disabled
[04:23:05] [PASSED] Clock 332880 BPP 24 DSC enabled
[04:23:05] [PASSED] Clock 324540 BPP 24 DSC enabled
[04:23:05] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[04:23:05] ============== drm_test_dp_mst_calc_pbn_div  ===============
[04:23:05] [PASSED] Link rate 2000000 lane count 4
[04:23:05] [PASSED] Link rate 2000000 lane count 2
[04:23:05] [PASSED] Link rate 2000000 lane count 1
[04:23:05] [PASSED] Link rate 1350000 lane count 4
[04:23:05] [PASSED] Link rate 1350000 lane count 2
[04:23:05] [PASSED] Link rate 1350000 lane count 1
[04:23:05] [PASSED] Link rate 1000000 lane count 4
[04:23:05] [PASSED] Link rate 1000000 lane count 2
[04:23:05] [PASSED] Link rate 1000000 lane count 1
[04:23:05] [PASSED] Link rate 810000 lane count 4
[04:23:05] [PASSED] Link rate 810000 lane count 2
[04:23:05] [PASSED] Link rate 810000 lane count 1
[04:23:05] [PASSED] Link rate 540000 lane count 4
[04:23:05] [PASSED] Link rate 540000 lane count 2
[04:23:05] [PASSED] Link rate 540000 lane count 1
[04:23:05] [PASSED] Link rate 270000 lane count 4
[04:23:05] [PASSED] Link rate 270000 lane count 2
[04:23:05] [PASSED] Link rate 270000 lane count 1
[04:23:05] [PASSED] Link rate 162000 lane count 4
[04:23:05] [PASSED] Link rate 162000 lane count 2
[04:23:05] [PASSED] Link rate 162000 lane count 1
[04:23:05] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[04:23:05] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[04:23:05] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[04:23:05] [PASSED] DP_POWER_UP_PHY with port number
[04:23:05] [PASSED] DP_POWER_DOWN_PHY with port number
[04:23:05] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[04:23:05] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[04:23:05] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[04:23:05] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[04:23:05] [PASSED] DP_QUERY_PAYLOAD with port number
[04:23:05] [PASSED] DP_QUERY_PAYLOAD with VCPI
[04:23:05] [PASSED] DP_REMOTE_DPCD_READ with port number
[04:23:05] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[04:23:05] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[04:23:05] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[04:23:05] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[04:23:05] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[04:23:05] [PASSED] DP_REMOTE_I2C_READ with port number
[04:23:05] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[04:23:05] [PASSED] DP_REMOTE_I2C_READ with transactions array
[04:23:05] [PASSED] DP_REMOTE_I2C_WRITE with port number
[04:23:05] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[04:23:05] [PASSED] DP_REMOTE_I2C_WRITE with data array
[04:23:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[04:23:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[04:23:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[04:23:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[04:23:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[04:23:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[04:23:05] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[04:23:05] ================ [PASSED] drm_dp_mst_helper ================
[04:23:05] ================== drm_exec (7 subtests) ===================
[04:23:05] [PASSED] sanitycheck
[04:23:05] [PASSED] test_lock
[04:23:05] [PASSED] test_lock_unlock
[04:23:05] [PASSED] test_duplicates
[04:23:05] [PASSED] test_prepare
[04:23:05] [PASSED] test_prepare_array
[04:23:05] [PASSED] test_multiple_loops
[04:23:05] ==================== [PASSED] drm_exec =====================
[04:23:05] =========== drm_format_helper_test (17 subtests) ===========
[04:23:05] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[04:23:05] [PASSED] single_pixel_source_buffer
[04:23:05] [PASSED] single_pixel_clip_rectangle
[04:23:05] [PASSED] well_known_colors
[04:23:05] [PASSED] destination_pitch
[04:23:05] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[04:23:05] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[04:23:05] [PASSED] single_pixel_source_buffer
[04:23:05] [PASSED] single_pixel_clip_rectangle
[04:23:05] [PASSED] well_known_colors
[04:23:05] [PASSED] destination_pitch
[04:23:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[04:23:05] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[04:23:05] [PASSED] single_pixel_source_buffer
[04:23:05] [PASSED] single_pixel_clip_rectangle
[04:23:05] [PASSED] well_known_colors
[04:23:05] [PASSED] destination_pitch
[04:23:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[04:23:05] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[04:23:05] [PASSED] single_pixel_source_buffer
[04:23:05] [PASSED] single_pixel_clip_rectangle
[04:23:05] [PASSED] well_known_colors
[04:23:05] [PASSED] destination_pitch
[04:23:05] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[04:23:05] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[04:23:05] [PASSED] single_pixel_source_buffer
[04:23:05] [PASSED] single_pixel_clip_rectangle
[04:23:05] [PASSED] well_known_colors
[04:23:05] [PASSED] destination_pitch
[04:23:05] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[04:23:05] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[04:23:05] [PASSED] single_pixel_source_buffer
[04:23:05] [PASSED] single_pixel_clip_rectangle
[04:23:05] [PASSED] well_known_colors
[04:23:05] [PASSED] destination_pitch
[04:23:05] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[04:23:05] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[04:23:05] [PASSED] single_pixel_source_buffer
[04:23:05] [PASSED] single_pixel_clip_rectangle
[04:23:05] [PASSED] well_known_colors
[04:23:05] [PASSED] destination_pitch
[04:23:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[04:23:05] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[04:23:05] [PASSED] single_pixel_source_buffer
[04:23:05] [PASSED] single_pixel_clip_rectangle
[04:23:05] [PASSED] well_known_colors
[04:23:05] [PASSED] destination_pitch
[04:23:05] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[04:23:05] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[04:23:05] [PASSED] single_pixel_source_buffer
[04:23:05] [PASSED] single_pixel_clip_rectangle
[04:23:05] [PASSED] well_known_colors
[04:23:05] [PASSED] destination_pitch
[04:23:05] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[04:23:05] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[04:23:05] [PASSED] single_pixel_source_buffer
[04:23:05] [PASSED] single_pixel_clip_rectangle
[04:23:05] [PASSED] well_known_colors
[04:23:05] [PASSED] destination_pitch
[04:23:05] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[04:23:05] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[04:23:05] [PASSED] single_pixel_source_buffer
[04:23:05] [PASSED] single_pixel_clip_rectangle
[04:23:05] [PASSED] well_known_colors
[04:23:05] [PASSED] destination_pitch
[04:23:05] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[04:23:05] ============== drm_test_fb_xrgb8888_to_mono  ===============
[04:23:05] [PASSED] single_pixel_source_buffer
[04:23:05] [PASSED] single_pixel_clip_rectangle
[04:23:05] [PASSED] well_known_colors
[04:23:05] [PASSED] destination_pitch
[04:23:05] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[04:23:05] ==================== drm_test_fb_swab  =====================
[04:23:05] [PASSED] single_pixel_source_buffer
[04:23:05] [PASSED] single_pixel_clip_rectangle
[04:23:05] [PASSED] well_known_colors
[04:23:05] [PASSED] destination_pitch
[04:23:05] ================ [PASSED] drm_test_fb_swab =================
[04:23:05] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[04:23:05] [PASSED] single_pixel_source_buffer
[04:23:05] [PASSED] single_pixel_clip_rectangle
[04:23:05] [PASSED] well_known_colors
[04:23:05] [PASSED] destination_pitch
[04:23:05] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[04:23:05] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[04:23:05] [PASSED] single_pixel_source_buffer
[04:23:05] [PASSED] single_pixel_clip_rectangle
[04:23:05] [PASSED] well_known_colors
[04:23:05] [PASSED] destination_pitch
[04:23:05] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[04:23:05] ================= drm_test_fb_clip_offset  =================
[04:23:05] [PASSED] pass through
[04:23:05] [PASSED] horizontal offset
[04:23:05] [PASSED] vertical offset
[04:23:05] [PASSED] horizontal and vertical offset
[04:23:05] [PASSED] horizontal offset (custom pitch)
[04:23:05] [PASSED] vertical offset (custom pitch)
[04:23:05] [PASSED] horizontal and vertical offset (custom pitch)
[04:23:05] ============= [PASSED] drm_test_fb_clip_offset =============
[04:23:05] =================== drm_test_fb_memcpy  ====================
[04:23:05] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[04:23:05] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[04:23:05] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[04:23:05] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[04:23:05] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[04:23:05] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[04:23:05] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[04:23:05] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[04:23:05] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[04:23:05] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[04:23:05] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[04:23:05] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[04:23:05] =============== [PASSED] drm_test_fb_memcpy ================
[04:23:05] ============= [PASSED] drm_format_helper_test ==============
[04:23:05] ================= drm_format (18 subtests) =================
[04:23:05] [PASSED] drm_test_format_block_width_invalid
[04:23:05] [PASSED] drm_test_format_block_width_one_plane
[04:23:05] [PASSED] drm_test_format_block_width_two_plane
[04:23:05] [PASSED] drm_test_format_block_width_three_plane
[04:23:05] [PASSED] drm_test_format_block_width_tiled
[04:23:05] [PASSED] drm_test_format_block_height_invalid
[04:23:05] [PASSED] drm_test_format_block_height_one_plane
[04:23:05] [PASSED] drm_test_format_block_height_two_plane
[04:23:05] [PASSED] drm_test_format_block_height_three_plane
[04:23:05] [PASSED] drm_test_format_block_height_tiled
[04:23:05] [PASSED] drm_test_format_min_pitch_invalid
[04:23:05] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[04:23:05] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[04:23:05] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[04:23:05] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[04:23:05] [PASSED] drm_test_format_min_pitch_two_plane
[04:23:05] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[04:23:05] [PASSED] drm_test_format_min_pitch_tiled
[04:23:05] =================== [PASSED] drm_format ====================
[04:23:05] ============== drm_framebuffer (10 subtests) ===============
[04:23:05] ========== drm_test_framebuffer_check_src_coords  ==========
[04:23:05] [PASSED] Success: source fits into fb
[04:23:05] [PASSED] Fail: overflowing fb with x-axis coordinate
[04:23:05] [PASSED] Fail: overflowing fb with y-axis coordinate
[04:23:05] [PASSED] Fail: overflowing fb with source width
[04:23:05] [PASSED] Fail: overflowing fb with source height
[04:23:05] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[04:23:05] [PASSED] drm_test_framebuffer_cleanup
[04:23:05] =============== drm_test_framebuffer_create  ===============
[04:23:05] [PASSED] ABGR8888 normal sizes
[04:23:05] [PASSED] ABGR8888 max sizes
[04:23:05] [PASSED] ABGR8888 pitch greater than min required
[04:23:05] [PASSED] ABGR8888 pitch less than min required
[04:23:05] [PASSED] ABGR8888 Invalid width
[04:23:05] [PASSED] ABGR8888 Invalid buffer handle
[04:23:05] [PASSED] No pixel format
[04:23:05] [PASSED] ABGR8888 Width 0
[04:23:05] [PASSED] ABGR8888 Height 0
[04:23:05] [PASSED] ABGR8888 Out of bound height * pitch combination
[04:23:05] [PASSED] ABGR8888 Large buffer offset
[04:23:05] [PASSED] ABGR8888 Buffer offset for inexistent plane
[04:23:05] [PASSED] ABGR8888 Invalid flag
[04:23:05] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[04:23:05] [PASSED] ABGR8888 Valid buffer modifier
[04:23:05] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[04:23:05] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[04:23:05] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[04:23:05] [PASSED] NV12 Normal sizes
[04:23:05] [PASSED] NV12 Max sizes
[04:23:05] [PASSED] NV12 Invalid pitch
[04:23:05] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[04:23:05] [PASSED] NV12 different  modifier per-plane
[04:23:05] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[04:23:05] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[04:23:05] [PASSED] NV12 Modifier for inexistent plane
[04:23:05] [PASSED] NV12 Handle for inexistent plane
[04:23:05] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[04:23:05] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[04:23:05] [PASSED] YVU420 Normal sizes
[04:23:05] [PASSED] YVU420 Max sizes
[04:23:05] [PASSED] YVU420 Invalid pitch
[04:23:05] [PASSED] YVU420 Different pitches
[04:23:05] [PASSED] YVU420 Different buffer offsets/pitches
[04:23:05] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[04:23:05] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[04:23:05] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[04:23:05] [PASSED] YVU420 Valid modifier
[04:23:05] [PASSED] YVU420 Different modifiers per plane
[04:23:05] [PASSED] YVU420 Modifier for inexistent plane
[04:23:05] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[04:23:05] [PASSED] X0L2 Normal sizes
[04:23:05] [PASSED] X0L2 Max sizes
[04:23:05] [PASSED] X0L2 Invalid pitch
[04:23:05] [PASSED] X0L2 Pitch greater than minimum required
[04:23:05] [PASSED] X0L2 Handle for inexistent plane
[04:23:05] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[04:23:05] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[04:23:05] [PASSED] X0L2 Valid modifier
[04:23:05] [PASSED] X0L2 Modifier for inexistent plane
[04:23:05] =========== [PASSED] drm_test_framebuffer_create ===========
[04:23:05] [PASSED] drm_test_framebuffer_free
[04:23:05] [PASSED] drm_test_framebuffer_init
[04:23:05] [PASSED] drm_test_framebuffer_init_bad_format
[04:23:05] [PASSED] drm_test_framebuffer_init_dev_mismatch
[04:23:05] [PASSED] drm_test_framebuffer_lookup
[04:23:05] [PASSED] drm_test_framebuffer_lookup_inexistent
[04:23:05] [PASSED] drm_test_framebuffer_modifiers_not_supported
[04:23:05] ================= [PASSED] drm_framebuffer =================
[04:23:05] ================ drm_gem_shmem (8 subtests) ================
[04:23:05] [PASSED] drm_gem_shmem_test_obj_create
[04:23:05] [PASSED] drm_gem_shmem_test_obj_create_private
[04:23:05] [PASSED] drm_gem_shmem_test_pin_pages
[04:23:05] [PASSED] drm_gem_shmem_test_vmap
[04:23:05] [PASSED] drm_gem_shmem_test_get_pages_sgt
[04:23:05] [PASSED] drm_gem_shmem_test_get_sg_table
[04:23:05] [PASSED] drm_gem_shmem_test_madvise
[04:23:05] [PASSED] drm_gem_shmem_test_purge
[04:23:05] ================== [PASSED] drm_gem_shmem ==================
[04:23:05] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[04:23:05] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[04:23:05] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[04:23:05] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[04:23:05] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[04:23:05] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[04:23:05] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[04:23:05] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[04:23:05] [PASSED] Automatic
[04:23:05] [PASSED] Full
[04:23:05] [PASSED] Limited 16:235
[04:23:05] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[04:23:05] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[04:23:05] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[04:23:05] [PASSED] drm_test_check_disable_connector
[04:23:05] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[04:23:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[04:23:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[04:23:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[04:23:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[04:23:05] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[04:23:05] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[04:23:05] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[04:23:05] [PASSED] drm_test_check_output_bpc_dvi
[04:23:05] [PASSED] drm_test_check_output_bpc_format_vic_1
[04:23:05] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[04:23:05] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[04:23:05] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[04:23:05] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[04:23:05] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[04:23:05] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[04:23:05] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[04:23:05] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[04:23:05] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[04:23:05] [PASSED] drm_test_check_broadcast_rgb_value
[04:23:05] [PASSED] drm_test_check_bpc_8_value
[04:23:05] [PASSED] drm_test_check_bpc_10_value
[04:23:05] [PASSED] drm_test_check_bpc_12_value
[04:23:05] [PASSED] drm_test_check_format_value
[04:23:05] [PASSED] drm_test_check_tmds_char_value
[04:23:05] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[04:23:05] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[04:23:05] [PASSED] drm_test_check_mode_valid
[04:23:05] [PASSED] drm_test_check_mode_valid_reject
[04:23:05] [PASSED] drm_test_check_mode_valid_reject_rate
[04:23:05] [PASSED] drm_test_check_mode_valid_reject_max_clock
[04:23:05] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[04:23:05] ================= drm_managed (2 subtests) =================
[04:23:05] [PASSED] drm_test_managed_release_action
[04:23:05] [PASSED] drm_test_managed_run_action
[04:23:05] =================== [PASSED] drm_managed ===================
[04:23:05] =================== drm_mm (6 subtests) ====================
[04:23:05] [PASSED] drm_test_mm_init
[04:23:05] [PASSED] drm_test_mm_debug
[04:23:05] [PASSED] drm_test_mm_align32
[04:23:05] [PASSED] drm_test_mm_align64
[04:23:05] [PASSED] drm_test_mm_lowest
[04:23:05] [PASSED] drm_test_mm_highest
[04:23:05] ===================== [PASSED] drm_mm ======================
[04:23:05] ============= drm_modes_analog_tv (5 subtests) =============
[04:23:05] [PASSED] drm_test_modes_analog_tv_mono_576i
[04:23:05] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[04:23:05] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[04:23:05] [PASSED] drm_test_modes_analog_tv_pal_576i
[04:23:05] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[04:23:05] =============== [PASSED] drm_modes_analog_tv ===============
[04:23:05] ============== drm_plane_helper (2 subtests) ===============
[04:23:05] =============== drm_test_check_plane_state  ================
[04:23:05] [PASSED] clipping_simple
[04:23:05] [PASSED] clipping_rotate_reflect
[04:23:05] [PASSED] positioning_simple
[04:23:05] [PASSED] upscaling
[04:23:05] [PASSED] downscaling
[04:23:05] [PASSED] rounding1
[04:23:05] [PASSED] rounding2
[04:23:05] [PASSED] rounding3
[04:23:05] [PASSED] rounding4
[04:23:05] =========== [PASSED] drm_test_check_plane_state ============
[04:23:05] =========== drm_test_check_invalid_plane_state  ============
[04:23:05] [PASSED] positioning_invalid
[04:23:05] [PASSED] upscaling_invalid
[04:23:05] [PASSED] downscaling_invalid
[04:23:05] ======= [PASSED] drm_test_check_invalid_plane_state ========
[04:23:05] ================ [PASSED] drm_plane_helper =================
[04:23:05] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[04:23:05] ====== drm_test_connector_helper_tv_get_modes_check  =======
[04:23:05] [PASSED] None
[04:23:05] [PASSED] PAL
[04:23:05] [PASSED] NTSC
[04:23:05] [PASSED] Both, NTSC Default
[04:23:05] [PASSED] Both, PAL Default
[04:23:05] [PASSED] Both, NTSC Default, with PAL on command-line
[04:23:05] [PASSED] Both, PAL Default, with NTSC on command-line
[04:23:05] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[04:23:05] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[04:23:05] ================== drm_rect (9 subtests) ===================
[04:23:05] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[04:23:05] [PASSED] drm_test_rect_clip_scaled_not_clipped
[04:23:05] [PASSED] drm_test_rect_clip_scaled_clipped
[04:23:05] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[04:23:05] ================= drm_test_rect_intersect  =================
[04:23:05] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[04:23:05] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[04:23:05] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[04:23:05] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[04:23:05] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[04:23:05] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[04:23:05] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[04:23:05] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[04:23:05] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[04:23:05] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[04:23:05] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[04:23:05] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[04:23:05] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[04:23:05] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[04:23:05] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[04:23:05] ============= [PASSED] drm_test_rect_intersect =============
[04:23:05] ================ drm_test_rect_calc_hscale  ================
[04:23:05] [PASSED] normal use
[04:23:05] [PASSED] out of max range
[04:23:05] [PASSED] out of min range
[04:23:05] [PASSED] zero dst
[04:23:05] [PASSED] negative src
[04:23:05] [PASSED] negative dst
[04:23:05] ============ [PASSED] drm_test_rect_calc_hscale ============
[04:23:05] ================ drm_test_rect_calc_vscale  ================
[04:23:05] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[04:23:05] [PASSED] out of max range
[04:23:05] [PASSED] out of min range
[04:23:05] [PASSED] zero dst
[04:23:05] [PASSED] negative src
[04:23:05] [PASSED] negative dst
[04:23:05] ============ [PASSED] drm_test_rect_calc_vscale ============
[04:23:05] ================== drm_test_rect_rotate  ===================
[04:23:05] [PASSED] reflect-x
[04:23:05] [PASSED] reflect-y
[04:23:05] [PASSED] rotate-0
[04:23:05] [PASSED] rotate-90
[04:23:05] [PASSED] rotate-180
[04:23:05] [PASSED] rotate-270
[04:23:05] ============== [PASSED] drm_test_rect_rotate ===============
[04:23:05] ================ drm_test_rect_rotate_inv  =================
[04:23:05] [PASSED] reflect-x
[04:23:05] [PASSED] reflect-y
[04:23:05] [PASSED] rotate-0
[04:23:05] [PASSED] rotate-90
[04:23:05] [PASSED] rotate-180
[04:23:05] [PASSED] rotate-270
[04:23:05] ============ [PASSED] drm_test_rect_rotate_inv =============
[04:23:05] ==================== [PASSED] drm_rect =====================
[04:23:05] ============ drm_sysfb_modeset_test (1 subtest) ============
[04:23:05] ============ drm_test_sysfb_build_fourcc_list  =============
[04:23:05] [PASSED] no native formats
[04:23:05] [PASSED] XRGB8888 as native format
[04:23:05] [PASSED] remove duplicates
[04:23:05] [PASSED] convert alpha formats
[04:23:05] [PASSED] random formats
[04:23:05] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[04:23:05] ============= [PASSED] drm_sysfb_modeset_test ==============
[04:23:05] ============================================================
[04:23:05] Testing complete. Ran 622 tests: passed: 622
[04:23:05] Elapsed time: 26.734s total, 1.699s configuring, 24.617s building, 0.397s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[04:23:05] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:23:07] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:23:16] Starting KUnit Kernel (1/1)...
[04:23:16] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:23:16] ================= ttm_device (5 subtests) ==================
[04:23:16] [PASSED] ttm_device_init_basic
[04:23:16] [PASSED] ttm_device_init_multiple
[04:23:16] [PASSED] ttm_device_fini_basic
[04:23:16] [PASSED] ttm_device_init_no_vma_man
[04:23:16] ================== ttm_device_init_pools  ==================
[04:23:16] [PASSED] No DMA allocations, no DMA32 required
[04:23:16] [PASSED] DMA allocations, DMA32 required
[04:23:16] [PASSED] No DMA allocations, DMA32 required
[04:23:16] [PASSED] DMA allocations, no DMA32 required
[04:23:16] ============== [PASSED] ttm_device_init_pools ==============
[04:23:16] =================== [PASSED] ttm_device ====================
[04:23:16] ================== ttm_pool (8 subtests) ===================
[04:23:16] ================== ttm_pool_alloc_basic  ===================
[04:23:16] [PASSED] One page
[04:23:16] [PASSED] More than one page
[04:23:16] [PASSED] Above the allocation limit
[04:23:16] [PASSED] One page, with coherent DMA mappings enabled
[04:23:16] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[04:23:16] ============== [PASSED] ttm_pool_alloc_basic ===============
[04:23:16] ============== ttm_pool_alloc_basic_dma_addr  ==============
[04:23:16] [PASSED] One page
[04:23:16] [PASSED] More than one page
[04:23:16] [PASSED] Above the allocation limit
[04:23:16] [PASSED] One page, with coherent DMA mappings enabled
[04:23:16] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[04:23:16] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[04:23:16] [PASSED] ttm_pool_alloc_order_caching_match
[04:23:16] [PASSED] ttm_pool_alloc_caching_mismatch
[04:23:16] [PASSED] ttm_pool_alloc_order_mismatch
[04:23:16] [PASSED] ttm_pool_free_dma_alloc
[04:23:16] [PASSED] ttm_pool_free_no_dma_alloc
[04:23:16] [PASSED] ttm_pool_fini_basic
[04:23:16] ==================== [PASSED] ttm_pool =====================
[04:23:16] ================ ttm_resource (8 subtests) =================
[04:23:16] ================= ttm_resource_init_basic  =================
[04:23:16] [PASSED] Init resource in TTM_PL_SYSTEM
[04:23:16] [PASSED] Init resource in TTM_PL_VRAM
[04:23:16] [PASSED] Init resource in a private placement
[04:23:16] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[04:23:16] ============= [PASSED] ttm_resource_init_basic =============
[04:23:16] [PASSED] ttm_resource_init_pinned
[04:23:16] [PASSED] ttm_resource_fini_basic
[04:23:16] [PASSED] ttm_resource_manager_init_basic
[04:23:16] [PASSED] ttm_resource_manager_usage_basic
[04:23:16] [PASSED] ttm_resource_manager_set_used_basic
[04:23:16] [PASSED] ttm_sys_man_alloc_basic
[04:23:16] [PASSED] ttm_sys_man_free_basic
[04:23:16] ================== [PASSED] ttm_resource ===================
[04:23:16] =================== ttm_tt (15 subtests) ===================
[04:23:16] ==================== ttm_tt_init_basic  ====================
[04:23:16] [PASSED] Page-aligned size
[04:23:16] [PASSED] Extra pages requested
[04:23:16] ================ [PASSED] ttm_tt_init_basic ================
[04:23:16] [PASSED] ttm_tt_init_misaligned
[04:23:16] [PASSED] ttm_tt_fini_basic
[04:23:16] [PASSED] ttm_tt_fini_sg
[04:23:16] [PASSED] ttm_tt_fini_shmem
[04:23:16] [PASSED] ttm_tt_create_basic
[04:23:16] [PASSED] ttm_tt_create_invalid_bo_type
[04:23:16] [PASSED] ttm_tt_create_ttm_exists
[04:23:16] [PASSED] ttm_tt_create_failed
[04:23:16] [PASSED] ttm_tt_destroy_basic
[04:23:16] [PASSED] ttm_tt_populate_null_ttm
[04:23:16] [PASSED] ttm_tt_populate_populated_ttm
[04:23:16] [PASSED] ttm_tt_unpopulate_basic
[04:23:16] [PASSED] ttm_tt_unpopulate_empty_ttm
[04:23:16] [PASSED] ttm_tt_swapin_basic
[04:23:16] ===================== [PASSED] ttm_tt ======================
[04:23:16] =================== ttm_bo (14 subtests) ===================
[04:23:16] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[04:23:16] [PASSED] Cannot be interrupted and sleeps
[04:23:16] [PASSED] Cannot be interrupted, locks straight away
[04:23:16] [PASSED] Can be interrupted, sleeps
[04:23:16] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[04:23:16] [PASSED] ttm_bo_reserve_locked_no_sleep
[04:23:16] [PASSED] ttm_bo_reserve_no_wait_ticket
[04:23:16] [PASSED] ttm_bo_reserve_double_resv
[04:23:16] [PASSED] ttm_bo_reserve_interrupted
[04:23:16] [PASSED] ttm_bo_reserve_deadlock
[04:23:16] [PASSED] ttm_bo_unreserve_basic
[04:23:16] [PASSED] ttm_bo_unreserve_pinned
[04:23:16] [PASSED] ttm_bo_unreserve_bulk
[04:23:16] [PASSED] ttm_bo_fini_basic
[04:23:16] [PASSED] ttm_bo_fini_shared_resv
[04:23:16] [PASSED] ttm_bo_pin_basic
[04:23:16] [PASSED] ttm_bo_pin_unpin_resource
[04:23:16] [PASSED] ttm_bo_multiple_pin_one_unpin
[04:23:16] ===================== [PASSED] ttm_bo ======================
[04:23:16] ============== ttm_bo_validate (21 subtests) ===============
[04:23:16] ============== ttm_bo_init_reserved_sys_man  ===============
[04:23:16] [PASSED] Buffer object for userspace
[04:23:16] [PASSED] Kernel buffer object
[04:23:16] [PASSED] Shared buffer object
[04:23:16] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[04:23:16] ============== ttm_bo_init_reserved_mock_man  ==============
[04:23:16] [PASSED] Buffer object for userspace
[04:23:16] [PASSED] Kernel buffer object
[04:23:16] [PASSED] Shared buffer object
[04:23:16] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[04:23:16] [PASSED] ttm_bo_init_reserved_resv
[04:23:16] ================== ttm_bo_validate_basic  ==================
[04:23:16] [PASSED] Buffer object for userspace
[04:23:16] [PASSED] Kernel buffer object
[04:23:16] [PASSED] Shared buffer object
[04:23:16] ============== [PASSED] ttm_bo_validate_basic ==============
[04:23:16] [PASSED] ttm_bo_validate_invalid_placement
[04:23:16] ============= ttm_bo_validate_same_placement  ==============
[04:23:16] [PASSED] System manager
[04:23:16] [PASSED] VRAM manager
[04:23:16] ========= [PASSED] ttm_bo_validate_same_placement ==========
[04:23:16] [PASSED] ttm_bo_validate_failed_alloc
[04:23:16] [PASSED] ttm_bo_validate_pinned
[04:23:16] [PASSED] ttm_bo_validate_busy_placement
[04:23:16] ================ ttm_bo_validate_multihop  =================
[04:23:16] [PASSED] Buffer object for userspace
[04:23:16] [PASSED] Kernel buffer object
[04:23:16] [PASSED] Shared buffer object
[04:23:16] ============ [PASSED] ttm_bo_validate_multihop =============
[04:23:16] ========== ttm_bo_validate_no_placement_signaled  ==========
[04:23:16] [PASSED] Buffer object in system domain, no page vector
[04:23:16] [PASSED] Buffer object in system domain with an existing page vector
[04:23:16] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[04:23:16] ======== ttm_bo_validate_no_placement_not_signaled  ========
[04:23:16] [PASSED] Buffer object for userspace
[04:23:16] [PASSED] Kernel buffer object
[04:23:16] [PASSED] Shared buffer object
[04:23:16] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[04:23:16] [PASSED] ttm_bo_validate_move_fence_signaled
[04:23:16] ========= ttm_bo_validate_move_fence_not_signaled  =========
[04:23:16] [PASSED] Waits for GPU
[04:23:16] [PASSED] Tries to lock straight away
[04:23:16] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[04:23:16] [PASSED] ttm_bo_validate_happy_evict
[04:23:16] [PASSED] ttm_bo_validate_all_pinned_evict
[04:23:16] [PASSED] ttm_bo_validate_allowed_only_evict
[04:23:16] [PASSED] ttm_bo_validate_deleted_evict
[04:23:16] [PASSED] ttm_bo_validate_busy_domain_evict
[04:23:16] [PASSED] ttm_bo_validate_evict_gutting
[04:23:16] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[04:23:16] ================= [PASSED] ttm_bo_validate =================
[04:23:16] ============================================================
[04:23:16] Testing complete. Ran 101 tests: passed: 101
[04:23:16] Elapsed time: 11.232s total, 1.681s configuring, 9.334s building, 0.178s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for Enable LT PHY

[Patchwork]

== Series Details ==

Series: Enable LT PHY
URL   : https://patchwork.freedesktop.org/series/155954/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2055:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2055:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2055:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_lt_phy.c:1908:35: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file:
+drivers/gpu/drm/i915/intel_uncore.c:1928:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1929:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1931:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1996:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1997:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1998:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2018:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2019:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2020:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Enable LT PHY

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 883 bytes --]

== Series Details ==

Series: Enable LT PHY
URL   : https://patchwork.freedesktop.org/series/155954/
State : success

== Summary ==

CI Bug Log - changes from xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb_BAT -> xe-pw-155954v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_8582 -> IGT_8584
  * Linux: xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb -> xe-pw-155954v1

  IGT_8582: 8582
  IGT_8584: 8584
  xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb: c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb
  xe-pw-155954v1: 155954v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/index.html

[-- Attachment #2: Type: text/html, Size: 1445 bytes --]

✗ Xe.CI.Full: failure for Enable LT PHY

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 71825 bytes --]

== Series Details ==

Series: Enable LT PHY
URL   : https://patchwork.freedesktop.org/series/155954/
State : failure

== Summary ==

CI Bug Log - changes from xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb_FULL -> xe-pw-155954v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-155954v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-155954v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-155954v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@fbdev@read:
    - shard-dg2-set2:     [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-464/igt@fbdev@read.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-435/igt@fbdev@read.html

  * igt@xe_compute_preempt@compute-threadgroup-preempt:
    - shard-adlp:         NOTRUN -> [SKIP][3]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-1/igt@xe_compute_preempt@compute-threadgroup-preempt.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][4]
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-466/igt@xe_compute_preempt@compute-threadgroup-preempt.html

  * igt@xe_pm_residency@cpg-basic:
    - shard-bmg:          [PASS][5] -> [DMESG-WARN][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-5/igt@xe_pm_residency@cpg-basic.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-5/igt@xe_pm_residency@cpg-basic.html

  
#### Warnings ####

  * igt@xe_compute_preempt@compute-preempt:
    - shard-adlp:         [SKIP][7] ([Intel XE#455] / [Intel XE#5632]) -> [SKIP][8] +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-2/igt@xe_compute_preempt@compute-preempt.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-1/igt@xe_compute_preempt@compute-preempt.html
    - shard-dg2-set2:     [SKIP][9] ([Intel XE#1280] / [Intel XE#455]) -> [SKIP][10]
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-433/igt@xe_compute_preempt@compute-preempt.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-433/igt@xe_compute_preempt@compute-preempt.html

  * igt@xe_compute_preempt@compute-preempt-many:
    - shard-dg2-set2:     [FAIL][11] ([Intel XE#5890]) -> [SKIP][12] +1 other test skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-435/igt@xe_compute_preempt@compute-preempt-many.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-432/igt@xe_compute_preempt@compute-preempt-many.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@xe_compute_preempt@compute-preempt-many-vram}:
    - shard-dg2-set2:     [FAIL][13] ([Intel XE#5890]) -> [SKIP][14]
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-433/igt@xe_compute_preempt@compute-preempt-many-vram.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-435/igt@xe_compute_preempt@compute-preempt-many-vram.html

  * {igt@xe_oa@non-zero-reason-all}:
    - shard-adlp:         NOTRUN -> [SKIP][15]
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-8/igt@xe_oa@non-zero-reason-all.html

  
New tests
---------

  New tests have been introduced between xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb_FULL and xe-pw-155954v1_FULL:

### New IGT tests (5) ###

  * igt@xe_oa@buffer-size@oag-0-1m:
    - Statuses : 1 pass(s)
    - Exec time: [0.10] s

  * igt@xe_oa@buffer-size@oag-0-8m:
    - Statuses : 1 pass(s)
    - Exec time: [0.60] s

  * igt@xe_oa@privileged-forked-access-vaddr@oag-0:
    - Statuses : 1 pass(s)
    - Exec time: [0.02] s

  * igt@xe_oa@tail-address-wrap@oag-0-1m:
    - Statuses : 1 pass(s)
    - Exec time: [0.03] s

  * igt@xe_oa@tail-address-wrap@oag-0-4m:
    - Statuses : 1 pass(s)
    - Exec time: [0.10] s

  

Known issues
------------

  Here are the changes found in xe-pw-155954v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_hwmon@hwmon-write:
    - shard-adlp:         NOTRUN -> [SKIP][16] ([Intel XE#1125] / [Intel XE#5574]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-2/igt@intel_hwmon@hwmon-write.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-adlp:         NOTRUN -> [SKIP][17] ([Intel XE#3157])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-6/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1:
    - shard-lnl:          [PASS][18] -> [FAIL][19] ([Intel XE#5993]) +3 other tests fail
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-lnl-2/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-lnl-4/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1.html

  * igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [FAIL][20] ([Intel XE#3884]) +1 other test fail
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-1/igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-adlp:         [PASS][21] -> [FAIL][22] ([Intel XE#3908]) +1 other test fail
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-9/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][23] ([Intel XE#316])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-463/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
    - shard-adlp:         NOTRUN -> [SKIP][24] ([Intel XE#607])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-6/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@4-tiled-addfb-size-overflow:
    - shard-adlp:         NOTRUN -> [SKIP][25] ([Intel XE#610])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@kms_big_fb@4-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-adlp:         NOTRUN -> [SKIP][26] ([Intel XE#316]) +5 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-1/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2328])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-6/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][28] ([Intel XE#1124])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-436/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
    - shard-adlp:         NOTRUN -> [SKIP][29] ([Intel XE#1124]) +13 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p:
    - shard-bmg:          [PASS][30] -> [SKIP][31] ([Intel XE#2314] / [Intel XE#2894])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-1/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html

  * igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
    - shard-adlp:         NOTRUN -> [SKIP][32] ([Intel XE#2191]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#2314] / [Intel XE#2894])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-2/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-4-displays-2560x1440p:
    - shard-adlp:         NOTRUN -> [SKIP][34] ([Intel XE#367]) +4 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc:
    - shard-adlp:         NOTRUN -> [SKIP][35] ([Intel XE#455] / [Intel XE#787]) +51 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-8/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][36] ([Intel XE#2907]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-6/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs@pipe-c-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][37] ([Intel XE#787]) +77 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     [PASS][38] -> [INCOMPLETE][39] ([Intel XE#3862]) +1 other test incomplete
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-432/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-dp-4.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-433/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-dp-4.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#2887])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-lnl-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][41] ([Intel XE#455] / [Intel XE#787]) +7 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-464/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][42] ([Intel XE#787]) +27 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-464/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-dp-4:
    - shard-dg2-set2:     [PASS][43] -> [INCOMPLETE][44] ([Intel XE#4345] / [Intel XE#6168])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-dp-4.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     [PASS][45] -> [DMESG-WARN][46] ([Intel XE#1727] / [Intel XE#3113])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_chamelium_color@degamma:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#2325])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-8/igt@kms_chamelium_color@degamma.html
    - shard-adlp:         NOTRUN -> [SKIP][48] ([Intel XE#306]) +2 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@kms_chamelium_color@degamma.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][49] ([Intel XE#306])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-435/igt@kms_chamelium_color@degamma.html
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#306])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-lnl-2/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_edid@hdmi-edid-change-during-hibernate:
    - shard-adlp:         NOTRUN -> [SKIP][51] ([Intel XE#373]) +13 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-1/igt@kms_chamelium_edid@hdmi-edid-change-during-hibernate.html

  * igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#2252])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-5/igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-adlp:         NOTRUN -> [SKIP][53] ([Intel XE#307]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-2/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@srm@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][54] ([Intel XE#1178])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-2/igt@kms_content_protection@srm@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x512:
    - shard-adlp:         NOTRUN -> [SKIP][55] ([Intel XE#308])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-2/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html

  * igt@kms_cursor_crc@cursor-sliding-32x32:
    - shard-dg2-set2:     NOTRUN -> [SKIP][56] ([Intel XE#455]) +2 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-436/igt@kms_cursor_crc@cursor-sliding-32x32.html
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#2320])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-4/igt@kms_cursor_crc@cursor-sliding-32x32.html

  * igt@kms_cursor_crc@cursor-sliding-max-size:
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#1424]) +1 other test skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-lnl-3/igt@kms_cursor_crc@cursor-sliding-max-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][59] -> [SKIP][60] ([Intel XE#2291]) +3 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-5/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-adlp:         NOTRUN -> [SKIP][61] ([Intel XE#309]) +8 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-dg2-set2:     NOTRUN -> [SKIP][62] ([Intel XE#323])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-463/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-bmg:          [PASS][63] -> [SKIP][64] ([Intel XE#4302])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-7/igt@kms_display_modes@extended-mode-basic.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-6/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-lnl:          NOTRUN -> [SKIP][65] ([Intel XE#2244])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-lnl-4/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
    - shard-adlp:         NOTRUN -> [SKIP][66] ([Intel XE#4422]) +1 other test skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-1/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html

  * igt@kms_fbcon_fbt@fbc:
    - shard-bmg:          NOTRUN -> [SKIP][67] ([Intel XE#5425])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-1/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-adlp:         NOTRUN -> [SKIP][68] ([Intel XE#776])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-1/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@chamelium:
    - shard-dg2-set2:     NOTRUN -> [SKIP][69] ([Intel XE#701])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-434/igt@kms_feature_discovery@chamelium.html
    - shard-adlp:         NOTRUN -> [SKIP][70] ([Intel XE#701])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@kms_feature_discovery@chamelium.html

  * igt@kms_feature_discovery@psr1:
    - shard-adlp:         NOTRUN -> [SKIP][71] ([Intel XE#1135]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-6/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-flip-vs-modeset-vs-hang:
    - shard-adlp:         NOTRUN -> [SKIP][72] ([Intel XE#310]) +6 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-6/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#1421])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-lnl-3/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-bmg:          [PASS][74] -> [SKIP][75] ([Intel XE#2316]) +4 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-8/igt@kms_flip@2x-plain-flip-fb-recreate.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-6/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip@basic-flip-vs-dpms:
    - shard-adlp:         NOTRUN -> [DMESG-WARN][76] ([Intel XE#4543]) +5 other tests dmesg-warn
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-1/igt@kms_flip@basic-flip-vs-dpms.html

  * igt@kms_flip@basic-flip-vs-modeset@c-hdmi-a1:
    - shard-adlp:         [PASS][77] -> [DMESG-WARN][78] ([Intel XE#4543]) +4 other tests dmesg-warn
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-9/igt@kms_flip@basic-flip-vs-modeset@c-hdmi-a1.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@kms_flip@basic-flip-vs-modeset@c-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-adlp:         [PASS][79] -> [DMESG-WARN][80] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-1/igt@kms_flip@flip-vs-suspend-interruptible.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-2/igt@kms_flip@flip-vs-suspend-interruptible.html
    - shard-bmg:          [PASS][81] -> [INCOMPLETE][82] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-8/igt@kms_flip@flip-vs-suspend-interruptible.html
    - shard-dg2-set2:     [PASS][83] -> [INCOMPLETE][84] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-433/igt@kms_flip@flip-vs-suspend-interruptible.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-466/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a1:
    - shard-adlp:         [PASS][85] -> [DMESG-WARN][86] ([Intel XE#2953] / [Intel XE#4173]) +1 other test dmesg-warn
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-1/igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a1.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-2/igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][87] ([Intel XE#2293] / [Intel XE#2380])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
    - shard-lnl:          NOTRUN -> [SKIP][88] ([Intel XE#1401] / [Intel XE#1745])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-lnl-5/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][89] ([Intel XE#1401])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-lnl-5/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][90] ([Intel XE#2293])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][91] ([Intel XE#4543] / [Intel XE#4921]) +1 other test dmesg-fail
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-x:
    - shard-adlp:         [PASS][92] -> [DMESG-FAIL][93] ([Intel XE#4543])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-9/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-x.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-x.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen:
    - shard-adlp:         NOTRUN -> [SKIP][94] ([Intel XE#651]) +17 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-8/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][95] ([Intel XE#651]) +5 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-463/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-plflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][96] ([Intel XE#656]) +3 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-lnl-7/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][97] ([Intel XE#5390]) +1 other test skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-adlp:         NOTRUN -> [SKIP][98] ([Intel XE#656]) +46 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][99] ([Intel XE#4543]) +11 other tests dmesg-fail
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][100] ([Intel XE#2311]) +5 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
    - shard-adlp:         NOTRUN -> [SKIP][101] ([Intel XE#653]) +15 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-2/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-adlp:         NOTRUN -> [SKIP][102] ([Intel XE#1151])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-8/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@plane-fbc-rte:
    - shard-adlp:         NOTRUN -> [SKIP][103] ([Intel XE#1158])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-6/igt@kms_frontbuffer_tracking@plane-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][104] ([Intel XE#2313]) +2 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
    - shard-dg2-set2:     NOTRUN -> [SKIP][105] ([Intel XE#653]) +5 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-bmg:          [PASS][106] -> [SKIP][107] ([Intel XE#1503])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-3/igt@kms_hdr@invalid-metadata-sizes.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-6/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-adlp:         NOTRUN -> [SKIP][108] ([Intel XE#346])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-2/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][109] ([Intel XE#2934])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-7/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_panel_fitting@legacy:
    - shard-adlp:         NOTRUN -> [SKIP][110] ([Intel XE#455]) +30 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@kms_panel_fitting@legacy.html

  * igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256:
    - shard-dg2-set2:     NOTRUN -> [FAIL][111] ([Intel XE#616]) +5 other tests fail
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-435/igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-bmg:          [PASS][112] -> [SKIP][113] ([Intel XE#4596])
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-none.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][114] ([Intel XE#5021])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-7/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_plane_multiple@tiling-4:
    - shard-adlp:         NOTRUN -> [SKIP][115] ([Intel XE#5020])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-1/igt@kms_plane_multiple@tiling-4.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-adlp:         NOTRUN -> [SKIP][116] ([Intel XE#870])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-8/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-adlp:         NOTRUN -> [SKIP][117] ([Intel XE#1129])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-lnl:          [PASS][118] -> [FAIL][119] ([Intel XE#718]) +1 other test fail
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-lnl-3/igt@kms_pm_dc@dc6-dpms.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-lnl-1/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-bmg:          NOTRUN -> [SKIP][120] ([Intel XE#2392])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-5/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_rpm@basic-pci-d3-state:
    - shard-dg2-set2:     [PASS][121] -> [FAIL][122] ([Intel XE#4741])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-463/igt@kms_pm_rpm@basic-pci-d3-state.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-434/igt@kms_pm_rpm@basic-pci-d3-state.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-adlp:         NOTRUN -> [SKIP][123] ([Intel XE#836])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-1/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-adlp:         NOTRUN -> [SKIP][124] ([Intel XE#1406] / [Intel XE#1489]) +8 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
    - shard-dg2-set2:     NOTRUN -> [SKIP][125] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-463/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][126] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-6/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-adlp:         NOTRUN -> [SKIP][127] ([Intel XE#1122] / [Intel XE#1406] / [Intel XE#5580]) +1 other test skip
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@fbc-psr2-cursor-plane-move:
    - shard-adlp:         NOTRUN -> [SKIP][128] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +13 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@kms_psr@fbc-psr2-cursor-plane-move.html

  * igt@kms_psr@fbc-psr2-primary-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][129] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-434/igt@kms_psr@fbc-psr2-primary-blt.html

  * igt@kms_psr@pr-primary-blt:
    - shard-bmg:          NOTRUN -> [SKIP][130] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-6/igt@kms_psr@pr-primary-blt.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-adlp:         NOTRUN -> [SKIP][131] ([Intel XE#3414]) +3 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-adlp:         NOTRUN -> [SKIP][132] ([Intel XE#330])
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-6/igt@kms_tv_load_detect@load-detect.html

  * igt@xe_ccs@suspend-resume:
    - shard-adlp:         NOTRUN -> [SKIP][133] ([Intel XE#455] / [Intel XE#488] / [Intel XE#5607]) +1 other test skip
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-2/igt@xe_ccs@suspend-resume.html

  * igt@xe_compute@ccs-mode-compute-kernel:
    - shard-adlp:         NOTRUN -> [SKIP][134] ([Intel XE#1447] / [Intel XE#5596])
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-1/igt@xe_compute@ccs-mode-compute-kernel.html

  * igt@xe_configfs@survivability-mode:
    - shard-adlp:         NOTRUN -> [SKIP][135] ([Intel XE#6010])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-1/igt@xe_configfs@survivability-mode.html

  * igt@xe_copy_basic@mem-copy-linear-0xfd:
    - shard-adlp:         NOTRUN -> [SKIP][136] ([Intel XE#1123])
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-1/igt@xe_copy_basic@mem-copy-linear-0xfd.html

  * igt@xe_create@create-big-vram:
    - shard-adlp:         NOTRUN -> [SKIP][137] ([Intel XE#1062])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-2/igt@xe_create@create-big-vram.html

  * igt@xe_eudebug@basic-read-event:
    - shard-adlp:         NOTRUN -> [SKIP][138] ([Intel XE#4837] / [Intel XE#5565]) +17 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-8/igt@xe_eudebug@basic-read-event.html

  * igt@xe_eudebug@read-metadata:
    - shard-lnl:          NOTRUN -> [SKIP][139] ([Intel XE#4837]) +1 other test skip
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-lnl-1/igt@xe_eudebug@read-metadata.html

  * igt@xe_eudebug_online@interrupt-other-debuggable:
    - shard-dg2-set2:     NOTRUN -> [SKIP][140] ([Intel XE#4837]) +3 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-433/igt@xe_eudebug_online@interrupt-other-debuggable.html

  * igt@xe_eudebug_online@stopped-thread:
    - shard-bmg:          NOTRUN -> [SKIP][141] ([Intel XE#4837]) +3 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-3/igt@xe_eudebug_online@stopped-thread.html

  * igt@xe_evict@evict-large-cm:
    - shard-adlp:         NOTRUN -> [SKIP][142] ([Intel XE#261] / [Intel XE#5564]) +1 other test skip
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-2/igt@xe_evict@evict-large-cm.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-adlp:         NOTRUN -> [SKIP][143] ([Intel XE#261]) +7 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-6/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_evict@evict-mixed-threads-small:
    - shard-adlp:         NOTRUN -> [SKIP][144] ([Intel XE#261] / [Intel XE#688])
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-8/igt@xe_evict@evict-mixed-threads-small.html

  * igt@xe_evict@evict-small-external-cm:
    - shard-adlp:         NOTRUN -> [SKIP][145] ([Intel XE#261] / [Intel XE#5564] / [Intel XE#688]) +2 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@xe_evict@evict-small-external-cm.html

  * igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-samefd:
    - shard-adlp:         NOTRUN -> [SKIP][146] ([Intel XE#688]) +2 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-6/igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-samefd.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][147] ([Intel XE#2322])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-5/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind.html
    - shard-lnl:          NOTRUN -> [SKIP][148] ([Intel XE#1392])
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-lnl-2/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr:
    - shard-dg2-set2:     [PASS][149] -> [SKIP][150] ([Intel XE#1392])
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-464/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-432/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate:
    - shard-adlp:         NOTRUN -> [SKIP][151] ([Intel XE#1392] / [Intel XE#5575]) +10 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-1/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race-imm:
    - shard-adlp:         NOTRUN -> [SKIP][152] ([Intel XE#288] / [Intel XE#5561]) +34 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-1/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race-imm.html

  * igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-race-imm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][153] ([Intel XE#288]) +3 other tests skip
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-433/igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-race-imm.html

  * igt@xe_exec_mix_modes@exec-spinner-interrupted-lr:
    - shard-adlp:         NOTRUN -> [SKIP][154] ([Intel XE#2360])
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@xe_exec_mix_modes@exec-spinner-interrupted-lr.html

  * igt@xe_exec_system_allocator@process-many-execqueues-free:
    - shard-adlp:         NOTRUN -> [SKIP][155] ([Intel XE#4915]) +339 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-6/igt@xe_exec_system_allocator@process-many-execqueues-free.html

  * igt@xe_exec_system_allocator@threads-many-stride-mmap-huge:
    - shard-bmg:          NOTRUN -> [SKIP][156] ([Intel XE#4943])
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-6/igt@xe_exec_system_allocator@threads-many-stride-mmap-huge.html
    - shard-lnl:          NOTRUN -> [SKIP][157] ([Intel XE#4943])
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-lnl-3/igt@xe_exec_system_allocator@threads-many-stride-mmap-huge.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-remap-eocheck:
    - shard-dg2-set2:     NOTRUN -> [SKIP][158] ([Intel XE#4915]) +47 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-435/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-remap-eocheck.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-dg2-set2:     NOTRUN -> [ABORT][159] ([Intel XE#5466])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-463/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
    - shard-adlp:         NOTRUN -> [ABORT][160] ([Intel XE#5530])
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-8/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv:
    - shard-dg2-set2:     [PASS][161] -> [DMESG-WARN][162] ([Intel XE#5893])
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-433/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-432/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html

  * igt@xe_oa@mmio-triggered-reports-read:
    - shard-adlp:         NOTRUN -> [SKIP][163] ([Intel XE#6032])
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-1/igt@xe_oa@mmio-triggered-reports-read.html

  * igt@xe_oa@syncs-syncobj-cfg:
    - shard-adlp:         NOTRUN -> [SKIP][164] ([Intel XE#3573]) +7 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-1/igt@xe_oa@syncs-syncobj-cfg.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][165] ([Intel XE#3573])
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-463/igt@xe_oa@syncs-syncobj-cfg.html

  * igt@xe_pat@display-vs-wb-transient:
    - shard-adlp:         NOTRUN -> [SKIP][166] ([Intel XE#1337] / [Intel XE#5572])
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-6/igt@xe_pat@display-vs-wb-transient.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][167] ([Intel XE#1337])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-436/igt@xe_pat@display-vs-wb-transient.html

  * igt@xe_pat@pat-index-xe2:
    - shard-adlp:         NOTRUN -> [SKIP][168] ([Intel XE#977])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@xe_pat@pat-index-xe2.html

  * igt@xe_peer2peer@read:
    - shard-adlp:         NOTRUN -> [SKIP][169] ([Intel XE#1061] / [Intel XE#5568])
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@xe_peer2peer@read.html

  * igt@xe_pm@d3cold-mocs:
    - shard-adlp:         NOTRUN -> [SKIP][170] ([Intel XE#2284])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-2/igt@xe_pm@d3cold-mocs.html

  * igt@xe_pm@s3-d3cold-basic-exec:
    - shard-adlp:         NOTRUN -> [SKIP][171] ([Intel XE#2284] / [Intel XE#366]) +1 other test skip
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-6/igt@xe_pm@s3-d3cold-basic-exec.html

  * igt@xe_pm@s4-basic:
    - shard-adlp:         NOTRUN -> [FAIL][172] ([Intel XE#6339]) +1 other test fail
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-2/igt@xe_pm@s4-basic.html
    - shard-lnl:          [PASS][173] -> [FAIL][174] ([Intel XE#6339]) +1 other test fail
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-lnl-8/igt@xe_pm@s4-basic.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-lnl-1/igt@xe_pm@s4-basic.html

  * igt@xe_pmu@fn-engine-activity-load:
    - shard-dg2-set2:     NOTRUN -> [SKIP][175] ([Intel XE#4650]) +1 other test skip
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-434/igt@xe_pmu@fn-engine-activity-load.html

  * igt@xe_pmu@fn-engine-activity-sched-if-idle:
    - shard-bmg:          [PASS][176] -> [DMESG-WARN][177] ([Intel XE#3876])
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-3/igt@xe_pmu@fn-engine-activity-sched-if-idle.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-3/igt@xe_pmu@fn-engine-activity-sched-if-idle.html

  * igt@xe_pxp@display-pxp-fb:
    - shard-adlp:         NOTRUN -> [SKIP][178] ([Intel XE#4733]) +1 other test skip
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@xe_pxp@display-pxp-fb.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][179] ([Intel XE#4733])
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-435/igt@xe_pxp@display-pxp-fb.html

  * igt@xe_pxp@pxp-stale-queue-post-suspend:
    - shard-adlp:         NOTRUN -> [SKIP][180] ([Intel XE#4733] / [Intel XE#5594]) +3 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-1/igt@xe_pxp@pxp-stale-queue-post-suspend.html

  * igt@xe_query@multigpu-query-uc-fw-version-huc:
    - shard-adlp:         NOTRUN -> [SKIP][181] ([Intel XE#944]) +3 other tests skip
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-2/igt@xe_query@multigpu-query-uc-fw-version-huc.html

  * igt@xe_render_copy@render-stress-4-copies:
    - shard-adlp:         NOTRUN -> [SKIP][182] ([Intel XE#4814] / [Intel XE#5614]) +2 other tests skip
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-6/igt@xe_render_copy@render-stress-4-copies.html

  * igt@xe_spin_batch@spin-mem-copy:
    - shard-adlp:         NOTRUN -> [SKIP][183] ([Intel XE#4821])
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-2/igt@xe_spin_batch@spin-mem-copy.html

  * igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs:
    - shard-bmg:          [PASS][184] -> [FAIL][185] ([Intel XE#5937]) +1 other test fail
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-7/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-5/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs.html

  
#### Possible fixes ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][186] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [PASS][187]
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][188] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522]) -> [PASS][189]
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [SKIP][190] ([Intel XE#2291]) -> [PASS][191] +3 other tests pass
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-7/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [FAIL][192] ([Intel XE#5299]) -> [PASS][193]
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_dp_aux_dev:
    - shard-bmg:          [SKIP][194] ([Intel XE#3009]) -> [PASS][195]
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_dp_aux_dev.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-3/igt@kms_dp_aux_dev.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-bmg:          [SKIP][196] ([Intel XE#4354]) -> [PASS][197]
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_dp_link_training@non-uhbr-sst.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-8/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible:
    - shard-bmg:          [SKIP][198] ([Intel XE#2316]) -> [PASS][199] +1 other test pass
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-3/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-adlp:         [DMESG-WARN][200] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543]) -> [PASS][201]
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-1/igt@kms_flip@flip-vs-suspend.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-6/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][202] ([Intel XE#4543]) -> [PASS][203] +4 other tests pass
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-1/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-6/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-x:
    - shard-adlp:         [FAIL][204] ([Intel XE#1874]) -> [PASS][205]
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-9/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-x.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-x.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-x:
    - shard-adlp:         [DMESG-FAIL][206] ([Intel XE#4543]) -> [PASS][207]
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-9/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-x.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-x.html

  * igt@kms_plane_scaling@planes-upscale-20x20:
    - shard-adlp:         [DMESG-WARN][208] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][209] +5 other tests pass
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-1/igt@kms_plane_scaling@planes-upscale-20x20.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-8/igt@kms_plane_scaling@planes-upscale-20x20.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-lnl:          [FAIL][210] ([Intel XE#718]) -> [PASS][211]
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-lnl-7/igt@kms_pm_dc@dc6-psr.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-lnl-2/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_setmode@invalid-clone-single-crtc-stealing:
    - shard-bmg:          [SKIP][212] ([Intel XE#1435]) -> [PASS][213]
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-5/igt@kms_setmode@invalid-clone-single-crtc-stealing.html

  * igt@xe_ccs@suspend-resume@tile64-compressed-compfmt0-vram01-vram01:
    - shard-dg2-set2:     [INCOMPLETE][214] -> [PASS][215] +1 other test pass
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-466/igt@xe_ccs@suspend-resume@tile64-compressed-compfmt0-vram01-vram01.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-466/igt@xe_ccs@suspend-resume@tile64-compressed-compfmt0-vram01-vram01.html

  * igt@xe_pm@s4-vm-bind-userptr:
    - shard-lnl:          [FAIL][216] ([Intel XE#6339]) -> [PASS][217] +1 other test pass
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-lnl-1/igt@xe_pm@s4-vm-bind-userptr.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-lnl-2/igt@xe_pm@s4-vm-bind-userptr.html

  
#### Warnings ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][218] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [INCOMPLETE][219] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168])
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_content_protection@lic-type-0:
    - shard-bmg:          [FAIL][220] ([Intel XE#1178]) -> [SKIP][221] ([Intel XE#2341])
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-1/igt@kms_content_protection@lic-type-0.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-6/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@srm:
    - shard-bmg:          [SKIP][222] ([Intel XE#2341]) -> [FAIL][223] ([Intel XE#1178])
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_content_protection@srm.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-2/igt@kms_content_protection@srm.html

  * igt@kms_content_protection@uevent:
    - shard-bmg:          [FAIL][224] ([Intel XE#1188]) -> [SKIP][225] ([Intel XE#2341])
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-8/igt@kms_content_protection@uevent.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-6/igt@kms_content_protection@uevent.html

  * igt@kms_flip@flip-vs-rmfb:
    - shard-adlp:         [DMESG-WARN][226] ([Intel XE#5208]) -> [DMESG-WARN][227] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#5208])
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-9/igt@kms_flip@flip-vs-rmfb.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-adlp-9/igt@kms_flip@flip-vs-rmfb.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][228] ([Intel XE#2312]) -> [SKIP][229] ([Intel XE#2311]) +10 other tests skip
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][230] ([Intel XE#2312]) -> [SKIP][231] ([Intel XE#5390]) +4 other tests skip
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-move:
    - shard-bmg:          [SKIP][232] ([Intel XE#2311]) -> [SKIP][233] ([Intel XE#2312]) +9 other tests skip
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-move.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][234] ([Intel XE#2313]) -> [SKIP][235] ([Intel XE#2312]) +6 other tests skip
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][236] ([Intel XE#2312]) -> [SKIP][237] ([Intel XE#2313]) +6 other tests skip
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][238] ([Intel XE#1729]) -> [SKIP][239] ([Intel XE#2426])
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-dg2-set2:     [SKIP][240] ([Intel XE#362]) -> [SKIP][241] ([Intel XE#1500])
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/shard-dg2-435/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1062]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1062
  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
  [Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129
  [Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135
  [Intel XE#1151]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1151
  [Intel XE#1158]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1158
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
  [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
  [Intel XE#1337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1337
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1447
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2934]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2934
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#3009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3009
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3157]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3157
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
  [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
  [Intel XE#3884]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3884
  [Intel XE#3908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3908
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4741]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4741
  [Intel XE#4814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4814
  [Intel XE#4821]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4821
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/488
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4921]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4921
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
  [Intel XE#5300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5300
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5425]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5425
  [Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
  [Intel XE#5530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5530
  [Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
  [Intel XE#5564]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5564
  [Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
  [Intel XE#5568]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5568
  [Intel XE#5572]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5572
  [Intel XE#5574]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5574
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#5580]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5580
  [Intel XE#5594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5594
  [Intel XE#5596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5596
  [Intel XE#5607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5607
  [Intel XE#5614]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5614
  [Intel XE#5632]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5632
  [Intel XE#5786]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5786
  [Intel XE#5890]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5890
  [Intel XE#5893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5893
  [Intel XE#5937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5937
  [Intel XE#5993]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5993
  [Intel XE#6010]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6010
  [Intel XE#6032]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6032
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#6168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6168
  [Intel XE#6281]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6281
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6320
  [Intel XE#6326]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6326
  [Intel XE#6339]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6339
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977


Build changes
-------------

  * IGT: IGT_8582 -> IGT_8584
  * Linux: xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb -> xe-pw-155954v1

  IGT_8582: 8582
  IGT_8584: 8584
  xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb: c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb
  xe-pw-155954v1: 155954v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155954v1/index.html

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